[deliverable/linux.git] / arch / arm / mach-s5p64x0 / clock-s5p6440.c

/* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
 *
 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * S5P6440 - Clock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/s5p64x0-clock.h>

#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/s5p6440.h>

static u32 epll_div[][5] = {
	{ 36000000,	0,	48, 1, 4 },
	{ 48000000,	0,	32, 1, 3 },
	{ 60000000,	0,	40, 1, 3 },
	{ 72000000,	0,	48, 1, 3 },
	{ 84000000,	0,	28, 1, 2 },
	{ 96000000,	0,	32, 1, 2 },
	{ 32768000,	45264,	43, 1, 4 },
	{ 45158000,	6903,	30, 1, 3 },
	{ 49152000,	50332,	32, 1, 3 },
	{ 67738000,	10398,	45, 1, 3 },
	{ 73728000,	9961,	49, 1, 3 }
};

static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned int epll_con, epll_con_k;
	unsigned int i;

	if (clk->rate == rate)	/* Return if nothing changed */
		return 0;

	epll_con = __raw_readl(S5P64X0_EPLL_CON);
	epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);

	epll_con_k &= ~(PLL90XX_KDIV_MASK);
	epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);

	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
		 if (epll_div[i][0] == rate) {
			epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
			epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
				    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
				    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
			break;
		}
	}

	if (i == ARRAY_SIZE(epll_div)) {
		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
		return -EINVAL;
	}

	__raw_writel(epll_con, S5P64X0_EPLL_CON);
	__raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);

	printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
			clk->rate, rate);

	clk->rate = rate;

	return 0;
}

static struct clk_ops s5p6440_epll_ops = {
	.get_rate = s5p_epll_get_rate,
	.set_rate = s5p6440_epll_set_rate,
};

static struct clksrc_clk clk_hclk = {
	.clk	= {
		.name		= "clk_hclk",
		.parent		= &clk_armclk.clk,
	},
	.reg_div	= { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
};

static struct clksrc_clk clk_pclk = {
	.clk	= {
		.name		= "clk_pclk",
		.parent		= &clk_hclk.clk,
	},
	.reg_div	= { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
};
static struct clksrc_clk clk_hclk_low = {
	.clk	= {
		.name		= "clk_hclk_low",
	},
	.sources	= &clkset_hclk_low,
	.reg_src	= { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
	.reg_div	= { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
};

static struct clksrc_clk clk_pclk_low = {
	.clk	= {
		.name		= "clk_pclk_low",
		.parent		= &clk_hclk_low.clk,
	},
	.reg_div	= { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
};

/*
 * The following clocks will be disabled during clock initialization. It is
 * recommended to keep the following clocks disabled until the driver requests
 * for enabling the clock.
 */
static struct clk init_clocks_off[] = {
	{
		.name		= "nand",
		.parent		= &clk_hclk.clk,
		.enable		= s5p64x0_mem_ctrl,
		.ctrlbit	= (1 << 2),
	}, {
		.name		= "post",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 5)
	}, {
		.name		= "2d",
		.parent		= &clk_hclk.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 8),
	}, {
		.name		= "dma",
		.devname	= "dma-pl330",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 12),
	}, {
		.name		= "hsmmc",
		.devname	= "s3c-sdhci.0",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 17),
	}, {
		.name		= "hsmmc",
		.devname	= "s3c-sdhci.1",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 18),
	}, {
		.name		= "hsmmc",
		.devname	= "s3c-sdhci.2",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 19),
	}, {
		.name		= "otg",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 20)
	}, {
		.name		= "irom",
		.parent		= &clk_hclk.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 25),
	}, {
		.name		= "lcd",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk1_ctrl,
		.ctrlbit	= (1 << 1),
	}, {
		.name		= "hclk_fimgvg",
		.parent		= &clk_hclk.clk,
		.enable		= s5p64x0_hclk1_ctrl,
		.ctrlbit	= (1 << 2),
	}, {
		.name		= "tsi",
		.parent		= &clk_hclk_low.clk,
		.enable		= s5p64x0_hclk1_ctrl,
		.ctrlbit	= (1 << 0),
	}, {
		.name		= "watchdog",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 5),
	}, {
		.name		= "rtc",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 6),
	}, {
		.name		= "timers",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 7),
	}, {
		.name		= "pcm",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 8),
	}, {
		.name		= "adc",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 12),
	}, {
		.name		= "i2c",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 17),
	}, {
		.name		= "spi",
		.devname	= "s3c64xx-spi.0",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 21),
	}, {
		.name		= "spi",
		.devname	= "s3c64xx-spi.1",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 22),
	}, {
		.name		= "gps",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 25),
	}, {
		.name		= "iis",
		.devname	= "samsung-i2s.0",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 26),
	}, {
		.name		= "dsim",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 28),
	}, {
		.name		= "etm",
		.parent		= &clk_pclk.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 29),
	}, {
		.name		= "dmc0",
		.parent		= &clk_pclk.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 30),
	}, {
		.name		= "pclk_fimgvg",
		.parent		= &clk_pclk.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 31),
	}, {
		.name		= "sclk_spi_48",
		.devname	= "s3c64xx-spi.0",
		.parent		= &clk_48m,
		.enable		= s5p64x0_sclk_ctrl,
		.ctrlbit	= (1 << 22),
	}, {
		.name		= "sclk_spi_48",
		.devname	= "s3c64xx-spi.1",
		.parent		= &clk_48m,
		.enable		= s5p64x0_sclk_ctrl,
		.ctrlbit	= (1 << 23),
	}, {
		.name		= "mmc_48m",
		.devname	= "s3c-sdhci.0",
		.parent		= &clk_48m,
		.enable		= s5p64x0_sclk_ctrl,
		.ctrlbit	= (1 << 27),
	}, {
		.name		= "mmc_48m",
		.devname	= "s3c-sdhci.1",
		.parent		= &clk_48m,
		.enable		= s5p64x0_sclk_ctrl,
		.ctrlbit	= (1 << 28),
	}, {
		.name		= "mmc_48m",
		.devname	= "s3c-sdhci.2",
		.parent		= &clk_48m,
		.enable		= s5p64x0_sclk_ctrl,
		.ctrlbit	= (1 << 29),
	},
};

/*
 * The following clocks will be enabled during clock initialization.
 */
static struct clk init_clocks[] = {
	{
		.name		= "intc",
		.parent		= &clk_hclk.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 1),
	}, {
		.name		= "mem",
		.parent		= &clk_hclk.clk,
		.enable		= s5p64x0_hclk0_ctrl,
		.ctrlbit	= (1 << 21),
	}, {
		.name		= "uart",
		.devname	= "s3c6400-uart.0",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 1),
	}, {
		.name		= "uart",
		.devname	= "s3c6400-uart.1",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 2),
	}, {
		.name		= "uart",
		.devname	= "s3c6400-uart.2",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 3),
	}, {
		.name		= "uart",
		.devname	= "s3c6400-uart.3",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "gpio",
		.parent		= &clk_pclk_low.clk,
		.enable		= s5p64x0_pclk_ctrl,
		.ctrlbit	= (1 << 18),
	},
};

static struct clk clk_iis_cd_v40 = {
	.name		= "iis_cdclk_v40",
};

static struct clk clk_pcm_cd = {
	.name		= "pcm_cdclk",
};

static struct clk *clkset_group1_list[] = {
	&clk_mout_epll.clk,
	&clk_dout_mpll.clk,
	&clk_fin_epll,
};

static struct clksrc_sources clkset_group1 = {
	.sources	= clkset_group1_list,
	.nr_sources	= ARRAY_SIZE(clkset_group1_list),
};

static struct clk *clkset_uart_list[] = {
	&clk_mout_epll.clk,
	&clk_dout_mpll.clk,
};

static struct clksrc_sources clkset_uart = {
	.sources	= clkset_uart_list,
	.nr_sources	= ARRAY_SIZE(clkset_uart_list),
};

static struct clk *clkset_audio_list[] = {
	&clk_mout_epll.clk,
	&clk_dout_mpll.clk,
	&clk_fin_epll,
	&clk_iis_cd_v40,
	&clk_pcm_cd,
};

static struct clksrc_sources clkset_audio = {
	.sources	= clkset_audio_list,
	.nr_sources	= ARRAY_SIZE(clkset_audio_list),
};

static struct clksrc_clk clksrcs[] = {
	{
		.clk	= {
			.name		= "sclk_mmc",
			.devname	= "s3c-sdhci.0",
			.ctrlbit	= (1 << 24),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_group1,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_mmc",
			.devname	= "s3c-sdhci.1",
			.ctrlbit	= (1 << 25),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_group1,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_mmc",
			.devname	= "s3c-sdhci.2",
			.ctrlbit	= (1 << 26),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_group1,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
	}, {
		.clk	= {
			.name		= "uclk1",
			.ctrlbit	= (1 << 5),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_uart,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_spi",
			.devname	= "s3c64xx-spi.0",
			.ctrlbit	= (1 << 20),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_group1,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_spi",
			.devname	= "s3c64xx-spi.1",
			.ctrlbit	= (1 << 21),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_group1,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_post",
			.ctrlbit	= (1 << 10),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_group1,
		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_dispcon",
			.ctrlbit	= (1 << 1),
			.enable		= s5p64x0_sclk1_ctrl,
		},
		.sources = &clkset_group1,
		.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_fimgvg",
			.ctrlbit	= (1 << 2),
			.enable		= s5p64x0_sclk1_ctrl,
		},
		.sources = &clkset_group1,
		.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
		.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
	}, {
		.clk	= {
			.name		= "sclk_audio2",
			.ctrlbit	= (1 << 11),
			.enable		= s5p64x0_sclk_ctrl,
		},
		.sources = &clkset_audio,
		.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
	},
};

/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
	&clk_mout_apll,
	&clk_mout_epll,
	&clk_mout_mpll,
	&clk_dout_mpll,
	&clk_armclk,
	&clk_hclk,
	&clk_pclk,
	&clk_hclk_low,
	&clk_pclk_low,
};

static struct clk dummy_apb_pclk = {
	.name		= "apb_pclk",
	.id		= -1,
};

void __init_or_cpufreq s5p6440_setup_clocks(void)
{
	struct clk *xtal_clk;

	unsigned long xtal;
	unsigned long fclk;
	unsigned long hclk;
	unsigned long hclk_low;
	unsigned long pclk;
	unsigned long pclk_low;

	unsigned long apll;
	unsigned long mpll;
	unsigned long epll;
	unsigned int ptr;

	/* Set S5P6440 functions for clk_fout_epll */

	clk_fout_epll.enable = s5p_epll_enable;
	clk_fout_epll.ops = &s5p6440_epll_ops;

	clk_48m.enable = s5p64x0_clk48m_ctrl;

	xtal_clk = clk_get(NULL, "ext_xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
	epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
				__raw_readl(S5P64X0_EPLL_CON_K));

	clk_fout_apll.rate = apll;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;

	printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
			" E=%ld.%ldMHz\n",
			print_mhz(apll), print_mhz(mpll), print_mhz(epll));

	fclk = clk_get_rate(&clk_armclk.clk);
	hclk = clk_get_rate(&clk_hclk.clk);
	pclk = clk_get_rate(&clk_pclk.clk);
	hclk_low = clk_get_rate(&clk_hclk_low.clk);
	pclk_low = clk_get_rate(&clk_pclk_low.clk);

	printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
			" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
			print_mhz(hclk), print_mhz(hclk_low),
			print_mhz(pclk), print_mhz(pclk_low));

	clk_f.rate = fclk;
	clk_h.rate = hclk;
	clk_p.rate = pclk;

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}

static struct clk *clks[] __initdata = {
	&clk_ext,
	&clk_iis_cd_v40,
	&clk_pcm_cd,
};

void __init s5p6440_register_clocks(void)
{
	int ptr;

	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));

	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
		s3c_register_clksrc(sysclks[ptr], 1);

	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));

	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	s3c24xx_register_clock(&dummy_apb_pclk);

	s3c_pwmclk_init();
}
Commit	Line	Data
3109e550 KK	1	/* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
	2	*
	3	* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* S5P6440 - Clock support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/list.h>
	17	#include <linux/errno.h>
	18	#include <linux/err.h>
	19	#include <linux/clk.h>
	20	#include <linux/sysdev.h>
	21	#include <linux/io.h>
	22
	23	#include <mach/hardware.h>
	24	#include <mach/map.h>
	25	#include <mach/regs-clock.h>
	26	#include <mach/s5p64x0-clock.h>
	27
	28	#include <plat/cpu-freq.h>
	29	#include <plat/clock.h>
	30	#include <plat/cpu.h>
	31	#include <plat/pll.h>
	32	#include <plat/s5p-clock.h>
	33	#include <plat/clock-clksrc.h>
	34	#include <plat/s5p6440.h>
	35
	36	static u32 epll_div[][5] = {
	37	{ 36000000, 0, 48, 1, 4 },
	38	{ 48000000, 0, 32, 1, 3 },
	39	{ 60000000, 0, 40, 1, 3 },
	40	{ 72000000, 0, 48, 1, 3 },
	41	{ 84000000, 0, 28, 1, 2 },
	42	{ 96000000, 0, 32, 1, 2 },
	43	{ 32768000, 45264, 43, 1, 4 },
	44	{ 45158000, 6903, 30, 1, 3 },
	45	{ 49152000, 50332, 32, 1, 3 },
	46	{ 67738000, 10398, 45, 1, 3 },
	47	{ 73728000, 9961, 49, 1, 3 }
	48	};
	49
	50	static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
	51	{
	52	unsigned int epll_con, epll_con_k;
	53	unsigned int i;
	54
	55	if (clk->rate == rate) /* Return if nothing changed */
	56	return 0;
	57
	58	epll_con = __raw_readl(S5P64X0_EPLL_CON);
	59	epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
	60
	61	epll_con_k &= ~(PLL90XX_KDIV_MASK);
	62	epll_con &= ~(PLL90XX_MDIV_MASK \| PLL90XX_PDIV_MASK \| PLL90XX_SDIV_MASK);
	63
	64	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
65	if (epll_div[i][0] == rate) {
66	epll_con_k \|= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
67	epll_con \|= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) \|
68	(epll_div[i][3] << PLL90XX_PDIV_SHIFT) \|
69	(epll_div[i][4] << PLL90XX_SDIV_SHIFT);
70	break;
71	}
72	}
73
74	if (i == ARRAY_SIZE(epll_div)) {
75	printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
76	return -EINVAL;
77	}
78
79	__raw_writel(epll_con, S5P64X0_EPLL_CON);
80	__raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
81
9616674a SY	82	printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
	83	clk->rate, rate);
	84
3109e550 KK	85	clk->rate = rate;
	86
	87	return 0;
	88	}
	89
	90	static struct clk_ops s5p6440_epll_ops = {
d4b34c6c	91	.get_rate = s5p_epll_get_rate,
3109e550 KK	92	.set_rate = s5p6440_epll_set_rate,
	93	};
	94
	95	static struct clksrc_clk clk_hclk = {
	96	.clk = {
	97	.name = "clk_hclk",
3109e550 KK	98	.parent = &clk_armclk.clk,
	99	},
	100	.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
	101	};
	102
	103	static struct clksrc_clk clk_pclk = {
	104	.clk = {
	105	.name = "clk_pclk",
3109e550 KK	106	.parent = &clk_hclk.clk,
	107	},
	108	.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
	109	};
	110	static struct clksrc_clk clk_hclk_low = {
	111	.clk = {
	112	.name = "clk_hclk_low",
3109e550 KK	113	},
	114	.sources = &clkset_hclk_low,
	115	.reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
	116	.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
	117	};
	118
	119	static struct clksrc_clk clk_pclk_low = {
	120	.clk = {
	121	.name = "clk_pclk_low",
3109e550 KK	122	.parent = &clk_hclk_low.clk,
	123	},
	124	.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
	125	};
	126
	127	/*
	128	* The following clocks will be disabled during clock initialization. It is
	129	* recommended to keep the following clocks disabled until the driver requests
	130	* for enabling the clock.
	131	*/
9f6bb3f5	132	static struct clk init_clocks_off[] = {
3109e550 KK	133	{
3109e550 KK	134	.name = "nand",
3109e550 KK	135	.parent = &clk_hclk.clk,
	136	.enable = s5p64x0_mem_ctrl,
	137	.ctrlbit = (1 << 2),
	138	}, {
	139	.name = "post",
3109e550 KK	140	.parent = &clk_hclk_low.clk,
	141	.enable = s5p64x0_hclk0_ctrl,
	142	.ctrlbit = (1 << 5)
	143	}, {
	144	.name = "2d",
3109e550 KK	145	.parent = &clk_hclk.clk,
	146	.enable = s5p64x0_hclk0_ctrl,
	147	.ctrlbit = (1 << 8),
b05d8535	148	}, {
3091e611	149	.name = "dma",
2213d0c0	150	.devname = "dma-pl330",
b05d8535 SY	151	.parent = &clk_hclk_low.clk,
	152	.enable = s5p64x0_hclk0_ctrl,
	153	.ctrlbit = (1 << 12),
3109e550 KK	154	}, {
3109e550 KK	155	.name = "hsmmc",
d8b22d25	156	.devname = "s3c-sdhci.0",
3109e550 KK	157	.parent = &clk_hclk_low.clk,
	158	.enable = s5p64x0_hclk0_ctrl,
	159	.ctrlbit = (1 << 17),
	160	}, {
	161	.name = "hsmmc",
d8b22d25	162	.devname = "s3c-sdhci.1",
3109e550 KK	163	.parent = &clk_hclk_low.clk,
	164	.enable = s5p64x0_hclk0_ctrl,
	165	.ctrlbit = (1 << 18),
	166	}, {
	167	.name = "hsmmc",
d8b22d25	168	.devname = "s3c-sdhci.2",
3109e550 KK	169	.parent = &clk_hclk_low.clk,
	170	.enable = s5p64x0_hclk0_ctrl,
	171	.ctrlbit = (1 << 19),
	172	}, {
	173	.name = "otg",
3109e550 KK	174	.parent = &clk_hclk_low.clk,
	175	.enable = s5p64x0_hclk0_ctrl,
	176	.ctrlbit = (1 << 20)
	177	}, {
	178	.name = "irom",
3109e550 KK	179	.parent = &clk_hclk.clk,
	180	.enable = s5p64x0_hclk0_ctrl,
	181	.ctrlbit = (1 << 25),
	182	}, {
	183	.name = "lcd",
3109e550 KK	184	.parent = &clk_hclk_low.clk,
	185	.enable = s5p64x0_hclk1_ctrl,
	186	.ctrlbit = (1 << 1),
	187	}, {
	188	.name = "hclk_fimgvg",
3109e550 KK	189	.parent = &clk_hclk.clk,
	190	.enable = s5p64x0_hclk1_ctrl,
	191	.ctrlbit = (1 << 2),
	192	}, {
	193	.name = "tsi",
3109e550 KK	194	.parent = &clk_hclk_low.clk,
	195	.enable = s5p64x0_hclk1_ctrl,
	196	.ctrlbit = (1 << 0),
	197	}, {
	198	.name = "watchdog",
3109e550 KK	199	.parent = &clk_pclk_low.clk,
	200	.enable = s5p64x0_pclk_ctrl,
	201	.ctrlbit = (1 << 5),
	202	}, {
	203	.name = "rtc",
3109e550 KK	204	.parent = &clk_pclk_low.clk,
	205	.enable = s5p64x0_pclk_ctrl,
	206	.ctrlbit = (1 << 6),
	207	}, {
	208	.name = "timers",
3109e550 KK	209	.parent = &clk_pclk_low.clk,
	210	.enable = s5p64x0_pclk_ctrl,
	211	.ctrlbit = (1 << 7),
	212	}, {
	213	.name = "pcm",
3109e550 KK	214	.parent = &clk_pclk_low.clk,
	215	.enable = s5p64x0_pclk_ctrl,
	216	.ctrlbit = (1 << 8),
	217	}, {
	218	.name = "adc",
3109e550 KK	219	.parent = &clk_pclk_low.clk,
	220	.enable = s5p64x0_pclk_ctrl,
	221	.ctrlbit = (1 << 12),
	222	}, {
	223	.name = "i2c",
3109e550 KK	224	.parent = &clk_pclk_low.clk,
	225	.enable = s5p64x0_pclk_ctrl,
	226	.ctrlbit = (1 << 17),
	227	}, {
	228	.name = "spi",
d8b22d25	229	.devname = "s3c64xx-spi.0",
3109e550 KK	230	.parent = &clk_pclk_low.clk,
	231	.enable = s5p64x0_pclk_ctrl,
	232	.ctrlbit = (1 << 21),
	233	}, {
	234	.name = "spi",
d8b22d25	235	.devname = "s3c64xx-spi.1",
3109e550 KK	236	.parent = &clk_pclk_low.clk,
	237	.enable = s5p64x0_pclk_ctrl,
	238	.ctrlbit = (1 << 22),
	239	}, {
	240	.name = "gps",
3109e550 KK	241	.parent = &clk_pclk_low.clk,
	242	.enable = s5p64x0_pclk_ctrl,
	243	.ctrlbit = (1 << 25),
	244	}, {
d9a93c34	245	.name = "iis",
d8b22d25	246	.devname = "samsung-i2s.0",
3109e550 KK	247	.parent = &clk_pclk_low.clk,
	248	.enable = s5p64x0_pclk_ctrl,
	249	.ctrlbit = (1 << 26),
	250	}, {
	251	.name = "dsim",
3109e550 KK	252	.parent = &clk_pclk_low.clk,
	253	.enable = s5p64x0_pclk_ctrl,
	254	.ctrlbit = (1 << 28),
	255	}, {
	256	.name = "etm",
3109e550 KK	257	.parent = &clk_pclk.clk,
	258	.enable = s5p64x0_pclk_ctrl,
	259	.ctrlbit = (1 << 29),
	260	}, {
	261	.name = "dmc0",
3109e550 KK	262	.parent = &clk_pclk.clk,
	263	.enable = s5p64x0_pclk_ctrl,
	264	.ctrlbit = (1 << 30),
	265	}, {
	266	.name = "pclk_fimgvg",
3109e550 KK	267	.parent = &clk_pclk.clk,
	268	.enable = s5p64x0_pclk_ctrl,
	269	.ctrlbit = (1 << 31),
	270	}, {
	271	.name = "sclk_spi_48",
d8b22d25	272	.devname = "s3c64xx-spi.0",
3109e550 KK	273	.parent = &clk_48m,
	274	.enable = s5p64x0_sclk_ctrl,
	275	.ctrlbit = (1 << 22),
	276	}, {
	277	.name = "sclk_spi_48",
d8b22d25	278	.devname = "s3c64xx-spi.1",
3109e550 KK	279	.parent = &clk_48m,
	280	.enable = s5p64x0_sclk_ctrl,
	281	.ctrlbit = (1 << 23),
	282	}, {
	283	.name = "mmc_48m",
d8b22d25	284	.devname = "s3c-sdhci.0",
3109e550 KK	285	.parent = &clk_48m,
	286	.enable = s5p64x0_sclk_ctrl,
	287	.ctrlbit = (1 << 27),
	288	}, {
	289	.name = "mmc_48m",
d8b22d25	290	.devname = "s3c-sdhci.1",
3109e550 KK	291	.parent = &clk_48m,
	292	.enable = s5p64x0_sclk_ctrl,
	293	.ctrlbit = (1 << 28),
	294	}, {
	295	.name = "mmc_48m",
d8b22d25	296	.devname = "s3c-sdhci.2",
3109e550 KK	297	.parent = &clk_48m,
	298	.enable = s5p64x0_sclk_ctrl,
	299	.ctrlbit = (1 << 29),
	300	},
	301	};
	302
	303	/*
	304	* The following clocks will be enabled during clock initialization.
	305	*/
	306	static struct clk init_clocks[] = {
	307	{
	308	.name = "intc",
3109e550 KK	309	.parent = &clk_hclk.clk,
	310	.enable = s5p64x0_hclk0_ctrl,
	311	.ctrlbit = (1 << 1),
	312	}, {
	313	.name = "mem",
3109e550 KK	314	.parent = &clk_hclk.clk,
	315	.enable = s5p64x0_hclk0_ctrl,
	316	.ctrlbit = (1 << 21),
3109e550 KK	317	}, {
3109e550 KK	318	.name = "uart",
d8b22d25	319	.devname = "s3c6400-uart.0",
3109e550 KK	320	.parent = &clk_pclk_low.clk,
	321	.enable = s5p64x0_pclk_ctrl,
	322	.ctrlbit = (1 << 1),
	323	}, {
	324	.name = "uart",
d8b22d25	325	.devname = "s3c6400-uart.1",
3109e550 KK	326	.parent = &clk_pclk_low.clk,
	327	.enable = s5p64x0_pclk_ctrl,
	328	.ctrlbit = (1 << 2),
	329	}, {
	330	.name = "uart",
d8b22d25	331	.devname = "s3c6400-uart.2",
3109e550 KK	332	.parent = &clk_pclk_low.clk,
	333	.enable = s5p64x0_pclk_ctrl,
	334	.ctrlbit = (1 << 3),
	335	}, {
	336	.name = "uart",
d8b22d25	337	.devname = "s3c6400-uart.3",
3109e550 KK	338	.parent = &clk_pclk_low.clk,
	339	.enable = s5p64x0_pclk_ctrl,
	340	.ctrlbit = (1 << 4),
	341	}, {
	342	.name = "gpio",
3109e550 KK	343	.parent = &clk_pclk_low.clk,
	344	.enable = s5p64x0_pclk_ctrl,
	345	.ctrlbit = (1 << 18),
	346	},
	347	};
	348
	349	static struct clk clk_iis_cd_v40 = {
	350	.name = "iis_cdclk_v40",
3109e550 KK	351	};
	352
	353	static struct clk clk_pcm_cd = {
	354	.name = "pcm_cdclk",
3109e550 KK	355	};
	356
	357	static struct clk *clkset_group1_list[] = {
	358	&clk_mout_epll.clk,
	359	&clk_dout_mpll.clk,
	360	&clk_fin_epll,
	361	};
	362
	363	static struct clksrc_sources clkset_group1 = {
	364	.sources = clkset_group1_list,
	365	.nr_sources = ARRAY_SIZE(clkset_group1_list),
	366	};
	367
	368	static struct clk *clkset_uart_list[] = {
	369	&clk_mout_epll.clk,
	370	&clk_dout_mpll.clk,
	371	};
	372
	373	static struct clksrc_sources clkset_uart = {
	374	.sources = clkset_uart_list,
	375	.nr_sources = ARRAY_SIZE(clkset_uart_list),
	376	};
	377
	378	static struct clk *clkset_audio_list[] = {
	379	&clk_mout_epll.clk,
	380	&clk_dout_mpll.clk,
	381	&clk_fin_epll,
	382	&clk_iis_cd_v40,
	383	&clk_pcm_cd,
	384	};
	385
	386	static struct clksrc_sources clkset_audio = {
	387	.sources = clkset_audio_list,
	388	.nr_sources = ARRAY_SIZE(clkset_audio_list),
	389	};
	390
	391	static struct clksrc_clk clksrcs[] = {
	392	{
	393	.clk = {
9af7d94f	394	.name = "sclk_mmc",
d8b22d25	395	.devname = "s3c-sdhci.0",
3109e550 KK	396	.ctrlbit = (1 << 24),
	397	.enable = s5p64x0_sclk_ctrl,
	398	},
	399	.sources = &clkset_group1,
	400	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
	401	.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
	402	}, {
	403	.clk = {
9af7d94f	404	.name = "sclk_mmc",
d8b22d25	405	.devname = "s3c-sdhci.1",
3109e550 KK	406	.ctrlbit = (1 << 25),
	407	.enable = s5p64x0_sclk_ctrl,
	408	},
	409	.sources = &clkset_group1,
	410	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
	411	.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
	412	}, {
	413	.clk = {
9af7d94f	414	.name = "sclk_mmc",
d8b22d25	415	.devname = "s3c-sdhci.2",
3109e550 KK	416	.ctrlbit = (1 << 26),
	417	.enable = s5p64x0_sclk_ctrl,
	418	},
	419	.sources = &clkset_group1,
	420	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
	421	.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
	422	}, {
	423	.clk = {
	424	.name = "uclk1",
3109e550 KK	425	.ctrlbit = (1 << 5),
	426	.enable = s5p64x0_sclk_ctrl,
	427	},
	428	.sources = &clkset_uart,
	429	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
	430	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
	431	}, {
	432	.clk = {
	433	.name = "sclk_spi",
d8b22d25	434	.devname = "s3c64xx-spi.0",
3109e550 KK	435	.ctrlbit = (1 << 20),
	436	.enable = s5p64x0_sclk_ctrl,
	437	},
	438	.sources = &clkset_group1,
	439	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
	440	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
	441	}, {
	442	.clk = {
	443	.name = "sclk_spi",
d8b22d25	444	.devname = "s3c64xx-spi.1",
3109e550 KK	445	.ctrlbit = (1 << 21),
	446	.enable = s5p64x0_sclk_ctrl,
	447	},
	448	.sources = &clkset_group1,
	449	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
	450	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
	451	}, {
	452	.clk = {
	453	.name = "sclk_post",
3109e550 KK	454	.ctrlbit = (1 << 10),
	455	.enable = s5p64x0_sclk_ctrl,
	456	},
	457	.sources = &clkset_group1,
	458	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
	459	.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
	460	}, {
	461	.clk = {
	462	.name = "sclk_dispcon",
3109e550 KK	463	.ctrlbit = (1 << 1),
	464	.enable = s5p64x0_sclk1_ctrl,
	465	},
	466	.sources = &clkset_group1,
	467	.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
	468	.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
	469	}, {
	470	.clk = {
	471	.name = "sclk_fimgvg",
3109e550 KK	472	.ctrlbit = (1 << 2),
	473	.enable = s5p64x0_sclk1_ctrl,
	474	},
	475	.sources = &clkset_group1,
	476	.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
	477	.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
	478	}, {
	479	.clk = {
	480	.name = "sclk_audio2",
3109e550 KK	481	.ctrlbit = (1 << 11),
	482	.enable = s5p64x0_sclk_ctrl,
	483	},
	484	.sources = &clkset_audio,
	485	.reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
	486	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
	487	},
	488	};
	489
	490	/* Clock initialization code */
	491	static struct clksrc_clk *sysclks[] = {
	492	&clk_mout_apll,
	493	&clk_mout_epll,
	494	&clk_mout_mpll,
	495	&clk_dout_mpll,
	496	&clk_armclk,
	497	&clk_hclk,
	498	&clk_pclk,
	499	&clk_hclk_low,
	500	&clk_pclk_low,
	501	};
	502
3091e611 BK	503	static struct clk dummy_apb_pclk = {
	504	.name = "apb_pclk",
	505	.id = -1,
	506	};
	507
3109e550 KK	508	void __init_or_cpufreq s5p6440_setup_clocks(void)
	509	{
	510	struct clk *xtal_clk;
	511
	512	unsigned long xtal;
	513	unsigned long fclk;
	514	unsigned long hclk;
	515	unsigned long hclk_low;
	516	unsigned long pclk;
	517	unsigned long pclk_low;
	518
	519	unsigned long apll;
	520	unsigned long mpll;
	521	unsigned long epll;
	522	unsigned int ptr;
	523
	524	/* Set S5P6440 functions for clk_fout_epll */
	525
d4b34c6c	526	clk_fout_epll.enable = s5p_epll_enable;
3109e550 KK	527	clk_fout_epll.ops = &s5p6440_epll_ops;
	528
	529	clk_48m.enable = s5p64x0_clk48m_ctrl;
	530
	531	xtal_clk = clk_get(NULL, "ext_xtal");
	532	BUG_ON(IS_ERR(xtal_clk));
	533
	534	xtal = clk_get_rate(xtal_clk);
	535	clk_put(xtal_clk);
	536
	537	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
	538	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
	539	epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
	540	__raw_readl(S5P64X0_EPLL_CON_K));
	541
	542	clk_fout_apll.rate = apll;
	543	clk_fout_mpll.rate = mpll;
	544	clk_fout_epll.rate = epll;
	545
	546	printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
	547	" E=%ld.%ldMHz\n",
	548	print_mhz(apll), print_mhz(mpll), print_mhz(epll));
	549
	550	fclk = clk_get_rate(&clk_armclk.clk);
	551	hclk = clk_get_rate(&clk_hclk.clk);
	552	pclk = clk_get_rate(&clk_pclk.clk);
	553	hclk_low = clk_get_rate(&clk_hclk_low.clk);
	554	pclk_low = clk_get_rate(&clk_pclk_low.clk);
	555
	556	printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
	557	" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
	558	print_mhz(hclk), print_mhz(hclk_low),
	559	print_mhz(pclk), print_mhz(pclk_low));
	560
	561	clk_f.rate = fclk;
	562	clk_h.rate = hclk;
	563	clk_p.rate = pclk;
	564
	565	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
	566	s3c_set_clksrc(&clksrcs[ptr], true);
	567	}
	568
	569	static struct clk *clks[] __initdata = {
	570	&clk_ext,
	571	&clk_iis_cd_v40,
	572	&clk_pcm_cd,
	573	};
	574
	575	void __init s5p6440_register_clocks(void)
	576	{
3109e550 KK	577	int ptr;
	578
	579	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
	580
	581	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
	582	s3c_register_clksrc(sysclks[ptr], 1);
	583
	584	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
	585	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
	586
9f6bb3f5 KK	587	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
9f6bb3f5 KK	588	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
3109e550	589
3091e611 BK	590	s3c24xx_register_clock(&dummy_apb_pclk);
3091e611 BK	591
3109e550 KK	592	s3c_pwmclk_init();
3109e550 KK	593	}