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3109e550 KK |
1 | /* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c |
2 | * | |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * S5P6450 - Clock support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/sysdev.h> | |
21 | #include <linux/io.h> | |
22 | ||
23 | #include <mach/hardware.h> | |
24 | #include <mach/map.h> | |
25 | #include <mach/regs-clock.h> | |
26 | #include <mach/s5p64x0-clock.h> | |
27 | ||
28 | #include <plat/cpu-freq.h> | |
29 | #include <plat/clock.h> | |
30 | #include <plat/cpu.h> | |
31 | #include <plat/pll.h> | |
32 | #include <plat/s5p-clock.h> | |
33 | #include <plat/clock-clksrc.h> | |
34 | #include <plat/s5p6450.h> | |
35 | ||
36 | static struct clksrc_clk clk_mout_dpll = { | |
37 | .clk = { | |
38 | .name = "mout_dpll", | |
3109e550 KK |
39 | }, |
40 | .sources = &clk_src_dpll, | |
41 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 }, | |
42 | }; | |
43 | ||
44 | static u32 epll_div[][5] = { | |
45 | { 133000000, 27307, 55, 2, 2 }, | |
46 | { 100000000, 43691, 41, 2, 2 }, | |
47 | { 480000000, 0, 80, 2, 0 }, | |
48 | }; | |
49 | ||
50 | static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate) | |
51 | { | |
52 | unsigned int epll_con, epll_con_k; | |
53 | unsigned int i; | |
54 | ||
55 | if (clk->rate == rate) /* Return if nothing changed */ | |
56 | return 0; | |
57 | ||
58 | epll_con = __raw_readl(S5P64X0_EPLL_CON); | |
59 | epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K); | |
60 | ||
61 | epll_con_k &= ~(PLL90XX_KDIV_MASK); | |
62 | epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK); | |
63 | ||
64 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { | |
65 | if (epll_div[i][0] == rate) { | |
66 | epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT); | |
67 | epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) | | |
68 | (epll_div[i][3] << PLL90XX_PDIV_SHIFT) | | |
69 | (epll_div[i][4] << PLL90XX_SDIV_SHIFT); | |
70 | break; | |
71 | } | |
72 | } | |
73 | ||
74 | if (i == ARRAY_SIZE(epll_div)) { | |
75 | printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__); | |
76 | return -EINVAL; | |
77 | } | |
78 | ||
79 | __raw_writel(epll_con, S5P64X0_EPLL_CON); | |
80 | __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K); | |
81 | ||
9616674a SY |
82 | printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", |
83 | clk->rate, rate); | |
84 | ||
3109e550 KK |
85 | clk->rate = rate; |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
90 | static struct clk_ops s5p6450_epll_ops = { | |
d4b34c6c | 91 | .get_rate = s5p_epll_get_rate, |
3109e550 KK |
92 | .set_rate = s5p6450_epll_set_rate, |
93 | }; | |
94 | ||
95 | static struct clksrc_clk clk_dout_epll = { | |
96 | .clk = { | |
97 | .name = "dout_epll", | |
3109e550 KK |
98 | .parent = &clk_mout_epll.clk, |
99 | }, | |
100 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 }, | |
101 | }; | |
102 | ||
103 | static struct clksrc_clk clk_mout_hclk_sel = { | |
104 | .clk = { | |
105 | .name = "mout_hclk_sel", | |
3109e550 KK |
106 | }, |
107 | .sources = &clkset_hclk_low, | |
108 | .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 }, | |
109 | }; | |
110 | ||
111 | static struct clk *clkset_hclk_list[] = { | |
112 | &clk_mout_hclk_sel.clk, | |
113 | &clk_armclk.clk, | |
114 | }; | |
115 | ||
116 | static struct clksrc_sources clkset_hclk = { | |
117 | .sources = clkset_hclk_list, | |
118 | .nr_sources = ARRAY_SIZE(clkset_hclk_list), | |
119 | }; | |
120 | ||
121 | static struct clksrc_clk clk_hclk = { | |
122 | .clk = { | |
123 | .name = "clk_hclk", | |
3109e550 KK |
124 | }, |
125 | .sources = &clkset_hclk, | |
126 | .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 }, | |
127 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 }, | |
128 | }; | |
129 | ||
130 | static struct clksrc_clk clk_pclk = { | |
131 | .clk = { | |
132 | .name = "clk_pclk", | |
3109e550 KK |
133 | .parent = &clk_hclk.clk, |
134 | }, | |
135 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, | |
136 | }; | |
137 | static struct clksrc_clk clk_dout_pwm_ratio0 = { | |
138 | .clk = { | |
139 | .name = "clk_dout_pwm_ratio0", | |
3109e550 KK |
140 | .parent = &clk_mout_hclk_sel.clk, |
141 | }, | |
142 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 }, | |
143 | }; | |
144 | ||
145 | static struct clksrc_clk clk_pclk_to_wdt_pwm = { | |
146 | .clk = { | |
147 | .name = "clk_pclk_to_wdt_pwm", | |
3109e550 KK |
148 | .parent = &clk_dout_pwm_ratio0.clk, |
149 | }, | |
150 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 }, | |
151 | }; | |
152 | ||
153 | static struct clksrc_clk clk_hclk_low = { | |
154 | .clk = { | |
155 | .name = "clk_hclk_low", | |
3109e550 KK |
156 | }, |
157 | .sources = &clkset_hclk_low, | |
158 | .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 }, | |
159 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 }, | |
160 | }; | |
161 | ||
162 | static struct clksrc_clk clk_pclk_low = { | |
163 | .clk = { | |
164 | .name = "clk_pclk_low", | |
3109e550 KK |
165 | .parent = &clk_hclk_low.clk, |
166 | }, | |
167 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, | |
168 | }; | |
169 | ||
170 | /* | |
171 | * The following clocks will be disabled during clock initialization. It is | |
172 | * recommended to keep the following clocks disabled until the driver requests | |
173 | * for enabling the clock. | |
174 | */ | |
1526631d | 175 | static struct clk init_clocks_off[] = { |
3109e550 KK |
176 | { |
177 | .name = "usbhost", | |
3109e550 KK |
178 | .parent = &clk_hclk_low.clk, |
179 | .enable = s5p64x0_hclk0_ctrl, | |
180 | .ctrlbit = (1 << 3), | |
b05d8535 SY |
181 | }, { |
182 | .name = "pdma", | |
b05d8535 SY |
183 | .parent = &clk_hclk_low.clk, |
184 | .enable = s5p64x0_hclk0_ctrl, | |
185 | .ctrlbit = (1 << 12), | |
3109e550 KK |
186 | }, { |
187 | .name = "hsmmc", | |
d8b22d25 | 188 | .devname = "s3c-sdhci.0", |
3109e550 KK |
189 | .parent = &clk_hclk_low.clk, |
190 | .enable = s5p64x0_hclk0_ctrl, | |
191 | .ctrlbit = (1 << 17), | |
192 | }, { | |
193 | .name = "hsmmc", | |
d8b22d25 | 194 | .devname = "s3c-sdhci.1", |
3109e550 KK |
195 | .parent = &clk_hclk_low.clk, |
196 | .enable = s5p64x0_hclk0_ctrl, | |
197 | .ctrlbit = (1 << 18), | |
198 | }, { | |
199 | .name = "hsmmc", | |
d8b22d25 | 200 | .devname = "s3c-sdhci.2", |
3109e550 KK |
201 | .parent = &clk_hclk_low.clk, |
202 | .enable = s5p64x0_hclk0_ctrl, | |
203 | .ctrlbit = (1 << 19), | |
204 | }, { | |
205 | .name = "usbotg", | |
3109e550 KK |
206 | .parent = &clk_hclk_low.clk, |
207 | .enable = s5p64x0_hclk0_ctrl, | |
208 | .ctrlbit = (1 << 20), | |
209 | }, { | |
210 | .name = "lcd", | |
3109e550 KK |
211 | .parent = &clk_h, |
212 | .enable = s5p64x0_hclk1_ctrl, | |
213 | .ctrlbit = (1 << 1), | |
214 | }, { | |
215 | .name = "watchdog", | |
3109e550 KK |
216 | .parent = &clk_pclk_low.clk, |
217 | .enable = s5p64x0_pclk_ctrl, | |
218 | .ctrlbit = (1 << 5), | |
232d1006 AD |
219 | }, { |
220 | .name = "rtc", | |
232d1006 AD |
221 | .parent = &clk_pclk_low.clk, |
222 | .enable = s5p64x0_pclk_ctrl, | |
223 | .ctrlbit = (1 << 6), | |
3109e550 KK |
224 | }, { |
225 | .name = "adc", | |
3109e550 KK |
226 | .parent = &clk_pclk_low.clk, |
227 | .enable = s5p64x0_pclk_ctrl, | |
228 | .ctrlbit = (1 << 12), | |
229 | }, { | |
230 | .name = "i2c", | |
d8b22d25 | 231 | .devname = "s3c2440-i2c.0", |
3109e550 KK |
232 | .parent = &clk_pclk_low.clk, |
233 | .enable = s5p64x0_pclk_ctrl, | |
234 | .ctrlbit = (1 << 17), | |
235 | }, { | |
236 | .name = "spi", | |
d8b22d25 | 237 | .devname = "s3c64xx-spi.0", |
3109e550 KK |
238 | .parent = &clk_pclk_low.clk, |
239 | .enable = s5p64x0_pclk_ctrl, | |
240 | .ctrlbit = (1 << 21), | |
241 | }, { | |
242 | .name = "spi", | |
d8b22d25 | 243 | .devname = "s3c64xx-spi.1", |
3109e550 KK |
244 | .parent = &clk_pclk_low.clk, |
245 | .enable = s5p64x0_pclk_ctrl, | |
246 | .ctrlbit = (1 << 22), | |
247 | }, { | |
248 | .name = "iis", | |
d8b22d25 | 249 | .devname = "samsung-i2s.0", |
3109e550 KK |
250 | .parent = &clk_pclk_low.clk, |
251 | .enable = s5p64x0_pclk_ctrl, | |
252 | .ctrlbit = (1 << 26), | |
6cb26da8 JB |
253 | }, { |
254 | .name = "iis", | |
d8b22d25 | 255 | .devname = "samsung-i2s.1", |
6cb26da8 JB |
256 | .parent = &clk_pclk_low.clk, |
257 | .enable = s5p64x0_pclk_ctrl, | |
258 | .ctrlbit = (1 << 15), | |
259 | }, { | |
260 | .name = "iis", | |
d8b22d25 | 261 | .devname = "samsung-i2s.2", |
6cb26da8 JB |
262 | .parent = &clk_pclk_low.clk, |
263 | .enable = s5p64x0_pclk_ctrl, | |
264 | .ctrlbit = (1 << 16), | |
3109e550 KK |
265 | }, { |
266 | .name = "i2c", | |
d8b22d25 | 267 | .devname = "s3c2440-i2c.1", |
3109e550 KK |
268 | .parent = &clk_pclk_low.clk, |
269 | .enable = s5p64x0_pclk_ctrl, | |
270 | .ctrlbit = (1 << 27), | |
271 | }, { | |
272 | .name = "dmc0", | |
3109e550 KK |
273 | .parent = &clk_pclk.clk, |
274 | .enable = s5p64x0_pclk_ctrl, | |
275 | .ctrlbit = (1 << 30), | |
276 | } | |
277 | }; | |
278 | ||
279 | /* | |
280 | * The following clocks will be enabled during clock initialization. | |
281 | */ | |
282 | static struct clk init_clocks[] = { | |
283 | { | |
284 | .name = "intc", | |
3109e550 KK |
285 | .parent = &clk_hclk.clk, |
286 | .enable = s5p64x0_hclk0_ctrl, | |
287 | .ctrlbit = (1 << 1), | |
288 | }, { | |
289 | .name = "mem", | |
3109e550 KK |
290 | .parent = &clk_hclk.clk, |
291 | .enable = s5p64x0_hclk0_ctrl, | |
292 | .ctrlbit = (1 << 21), | |
3109e550 KK |
293 | }, { |
294 | .name = "uart", | |
d8b22d25 | 295 | .devname = "s3c6400-uart.0", |
3109e550 KK |
296 | .parent = &clk_pclk_low.clk, |
297 | .enable = s5p64x0_pclk_ctrl, | |
298 | .ctrlbit = (1 << 1), | |
299 | }, { | |
300 | .name = "uart", | |
d8b22d25 | 301 | .devname = "s3c6400-uart.1", |
3109e550 KK |
302 | .parent = &clk_pclk_low.clk, |
303 | .enable = s5p64x0_pclk_ctrl, | |
304 | .ctrlbit = (1 << 2), | |
305 | }, { | |
306 | .name = "uart", | |
d8b22d25 | 307 | .devname = "s3c6400-uart.2", |
3109e550 KK |
308 | .parent = &clk_pclk_low.clk, |
309 | .enable = s5p64x0_pclk_ctrl, | |
310 | .ctrlbit = (1 << 3), | |
311 | }, { | |
312 | .name = "uart", | |
d8b22d25 | 313 | .devname = "s3c6400-uart.3", |
3109e550 KK |
314 | .parent = &clk_pclk_low.clk, |
315 | .enable = s5p64x0_pclk_ctrl, | |
316 | .ctrlbit = (1 << 4), | |
317 | }, { | |
318 | .name = "timers", | |
3109e550 KK |
319 | .parent = &clk_pclk_to_wdt_pwm.clk, |
320 | .enable = s5p64x0_pclk_ctrl, | |
321 | .ctrlbit = (1 << 7), | |
322 | }, { | |
323 | .name = "gpio", | |
3109e550 KK |
324 | .parent = &clk_pclk_low.clk, |
325 | .enable = s5p64x0_pclk_ctrl, | |
326 | .ctrlbit = (1 << 18), | |
327 | }, | |
328 | }; | |
329 | ||
330 | static struct clk *clkset_uart_list[] = { | |
331 | &clk_dout_epll.clk, | |
332 | &clk_dout_mpll.clk, | |
333 | }; | |
334 | ||
335 | static struct clksrc_sources clkset_uart = { | |
336 | .sources = clkset_uart_list, | |
337 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | |
338 | }; | |
339 | ||
340 | static struct clk *clkset_mali_list[] = { | |
341 | &clk_mout_epll.clk, | |
342 | &clk_mout_apll.clk, | |
343 | &clk_mout_mpll.clk, | |
344 | }; | |
345 | ||
346 | static struct clksrc_sources clkset_mali = { | |
347 | .sources = clkset_mali_list, | |
348 | .nr_sources = ARRAY_SIZE(clkset_mali_list), | |
349 | }; | |
350 | ||
351 | static struct clk *clkset_group2_list[] = { | |
352 | &clk_dout_epll.clk, | |
353 | &clk_dout_mpll.clk, | |
354 | &clk_ext_xtal_mux, | |
355 | }; | |
356 | ||
357 | static struct clksrc_sources clkset_group2 = { | |
358 | .sources = clkset_group2_list, | |
359 | .nr_sources = ARRAY_SIZE(clkset_group2_list), | |
360 | }; | |
361 | ||
362 | static struct clk *clkset_dispcon_list[] = { | |
363 | &clk_dout_epll.clk, | |
364 | &clk_dout_mpll.clk, | |
365 | &clk_ext_xtal_mux, | |
366 | &clk_mout_dpll.clk, | |
367 | }; | |
368 | ||
369 | static struct clksrc_sources clkset_dispcon = { | |
370 | .sources = clkset_dispcon_list, | |
371 | .nr_sources = ARRAY_SIZE(clkset_dispcon_list), | |
372 | }; | |
373 | ||
374 | static struct clk *clkset_hsmmc44_list[] = { | |
375 | &clk_dout_epll.clk, | |
376 | &clk_dout_mpll.clk, | |
377 | &clk_ext_xtal_mux, | |
378 | &s5p_clk_27m, | |
379 | &clk_48m, | |
380 | }; | |
381 | ||
382 | static struct clksrc_sources clkset_hsmmc44 = { | |
383 | .sources = clkset_hsmmc44_list, | |
384 | .nr_sources = ARRAY_SIZE(clkset_hsmmc44_list), | |
385 | }; | |
386 | ||
387 | static struct clk *clkset_sclk_audio0_list[] = { | |
388 | [0] = &clk_dout_epll.clk, | |
389 | [1] = &clk_dout_mpll.clk, | |
390 | [2] = &clk_ext_xtal_mux, | |
391 | [3] = NULL, | |
392 | [4] = NULL, | |
393 | }; | |
394 | ||
395 | static struct clksrc_sources clkset_sclk_audio0 = { | |
396 | .sources = clkset_sclk_audio0_list, | |
397 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list), | |
398 | }; | |
399 | ||
400 | static struct clksrc_clk clk_sclk_audio0 = { | |
401 | .clk = { | |
402 | .name = "audio-bus", | |
3109e550 KK |
403 | .enable = s5p64x0_sclk_ctrl, |
404 | .ctrlbit = (1 << 8), | |
405 | .parent = &clk_dout_epll.clk, | |
406 | }, | |
407 | .sources = &clkset_sclk_audio0, | |
408 | .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 }, | |
409 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 }, | |
410 | }; | |
411 | ||
412 | static struct clksrc_clk clksrcs[] = { | |
413 | { | |
414 | .clk = { | |
415 | .name = "sclk_mmc", | |
d8b22d25 | 416 | .devname = "s3c-sdhci.0", |
3109e550 KK |
417 | .ctrlbit = (1 << 24), |
418 | .enable = s5p64x0_sclk_ctrl, | |
419 | }, | |
420 | .sources = &clkset_group2, | |
421 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 }, | |
422 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, | |
423 | }, { | |
424 | .clk = { | |
425 | .name = "sclk_mmc", | |
d8b22d25 | 426 | .devname = "s3c-sdhci.1", |
3109e550 KK |
427 | .ctrlbit = (1 << 25), |
428 | .enable = s5p64x0_sclk_ctrl, | |
429 | }, | |
430 | .sources = &clkset_group2, | |
431 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 }, | |
432 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, | |
433 | }, { | |
434 | .clk = { | |
435 | .name = "sclk_mmc", | |
d8b22d25 | 436 | .devname = "s3c-sdhci.2", |
3109e550 KK |
437 | .ctrlbit = (1 << 26), |
438 | .enable = s5p64x0_sclk_ctrl, | |
439 | }, | |
440 | .sources = &clkset_group2, | |
441 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 }, | |
442 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, | |
443 | }, { | |
444 | .clk = { | |
445 | .name = "uclk1", | |
3109e550 KK |
446 | .ctrlbit = (1 << 5), |
447 | .enable = s5p64x0_sclk_ctrl, | |
448 | }, | |
449 | .sources = &clkset_uart, | |
450 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 }, | |
451 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, | |
452 | }, { | |
453 | .clk = { | |
454 | .name = "sclk_spi", | |
d8b22d25 | 455 | .devname = "s3c64xx-spi.0", |
3109e550 KK |
456 | .ctrlbit = (1 << 20), |
457 | .enable = s5p64x0_sclk_ctrl, | |
458 | }, | |
459 | .sources = &clkset_group2, | |
460 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 }, | |
461 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 }, | |
462 | }, { | |
463 | .clk = { | |
464 | .name = "sclk_spi", | |
d8b22d25 | 465 | .devname = "s3c64xx-spi.1", |
3109e550 KK |
466 | .ctrlbit = (1 << 21), |
467 | .enable = s5p64x0_sclk_ctrl, | |
468 | }, | |
469 | .sources = &clkset_group2, | |
470 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 }, | |
471 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 }, | |
472 | }, { | |
473 | .clk = { | |
474 | .name = "sclk_fimc", | |
3109e550 KK |
475 | .ctrlbit = (1 << 10), |
476 | .enable = s5p64x0_sclk_ctrl, | |
477 | }, | |
478 | .sources = &clkset_group2, | |
479 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 }, | |
480 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 }, | |
481 | }, { | |
482 | .clk = { | |
483 | .name = "aclk_mali", | |
3109e550 KK |
484 | .ctrlbit = (1 << 2), |
485 | .enable = s5p64x0_sclk1_ctrl, | |
486 | }, | |
487 | .sources = &clkset_mali, | |
488 | .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 }, | |
489 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 }, | |
490 | }, { | |
491 | .clk = { | |
492 | .name = "sclk_2d", | |
3109e550 KK |
493 | .ctrlbit = (1 << 12), |
494 | .enable = s5p64x0_sclk_ctrl, | |
495 | }, | |
496 | .sources = &clkset_mali, | |
497 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 }, | |
498 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 }, | |
499 | }, { | |
500 | .clk = { | |
501 | .name = "sclk_usi", | |
3109e550 KK |
502 | .ctrlbit = (1 << 7), |
503 | .enable = s5p64x0_sclk_ctrl, | |
504 | }, | |
505 | .sources = &clkset_group2, | |
506 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 }, | |
507 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 }, | |
508 | }, { | |
509 | .clk = { | |
510 | .name = "sclk_camif", | |
3109e550 KK |
511 | .ctrlbit = (1 << 6), |
512 | .enable = s5p64x0_sclk_ctrl, | |
513 | }, | |
514 | .sources = &clkset_group2, | |
515 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 }, | |
516 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 }, | |
517 | }, { | |
518 | .clk = { | |
519 | .name = "sclk_dispcon", | |
3109e550 KK |
520 | .ctrlbit = (1 << 1), |
521 | .enable = s5p64x0_sclk1_ctrl, | |
522 | }, | |
523 | .sources = &clkset_dispcon, | |
524 | .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 }, | |
525 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 }, | |
526 | }, { | |
527 | .clk = { | |
528 | .name = "sclk_hsmmc44", | |
3109e550 KK |
529 | .ctrlbit = (1 << 30), |
530 | .enable = s5p64x0_sclk_ctrl, | |
531 | }, | |
532 | .sources = &clkset_hsmmc44, | |
533 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 }, | |
534 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 }, | |
535 | }, | |
536 | }; | |
537 | ||
538 | /* Clock initialization code */ | |
539 | static struct clksrc_clk *sysclks[] = { | |
540 | &clk_mout_apll, | |
541 | &clk_mout_epll, | |
542 | &clk_dout_epll, | |
543 | &clk_mout_mpll, | |
544 | &clk_dout_mpll, | |
545 | &clk_armclk, | |
546 | &clk_mout_hclk_sel, | |
547 | &clk_dout_pwm_ratio0, | |
548 | &clk_pclk_to_wdt_pwm, | |
549 | &clk_hclk, | |
550 | &clk_pclk, | |
551 | &clk_hclk_low, | |
552 | &clk_pclk_low, | |
553 | &clk_sclk_audio0, | |
554 | }; | |
555 | ||
556 | void __init_or_cpufreq s5p6450_setup_clocks(void) | |
557 | { | |
558 | struct clk *xtal_clk; | |
559 | ||
560 | unsigned long xtal; | |
561 | unsigned long fclk; | |
562 | unsigned long hclk; | |
563 | unsigned long hclk_low; | |
564 | unsigned long pclk; | |
565 | unsigned long pclk_low; | |
566 | ||
567 | unsigned long apll; | |
568 | unsigned long mpll; | |
569 | unsigned long epll; | |
570 | unsigned long dpll; | |
571 | unsigned int ptr; | |
572 | ||
573 | /* Set S5P6450 functions for clk_fout_epll */ | |
574 | ||
d4b34c6c | 575 | clk_fout_epll.enable = s5p_epll_enable; |
3109e550 KK |
576 | clk_fout_epll.ops = &s5p6450_epll_ops; |
577 | ||
578 | clk_48m.enable = s5p64x0_clk48m_ctrl; | |
579 | ||
580 | xtal_clk = clk_get(NULL, "ext_xtal"); | |
581 | BUG_ON(IS_ERR(xtal_clk)); | |
582 | ||
583 | xtal = clk_get_rate(xtal_clk); | |
584 | clk_put(xtal_clk); | |
585 | ||
586 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502); | |
587 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502); | |
588 | epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON), | |
589 | __raw_readl(S5P64X0_EPLL_CON_K)); | |
590 | dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON), | |
591 | __raw_readl(S5P6450_DPLL_CON_K), pll_4650c); | |
592 | ||
593 | clk_fout_apll.rate = apll; | |
594 | clk_fout_mpll.rate = mpll; | |
595 | clk_fout_epll.rate = epll; | |
596 | clk_fout_dpll.rate = dpll; | |
597 | ||
598 | printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ | |
599 | " E=%ld.%ldMHz, D=%ld.%ldMHz\n", | |
600 | print_mhz(apll), print_mhz(mpll), print_mhz(epll), | |
601 | print_mhz(dpll)); | |
602 | ||
603 | fclk = clk_get_rate(&clk_armclk.clk); | |
604 | hclk = clk_get_rate(&clk_hclk.clk); | |
605 | pclk = clk_get_rate(&clk_pclk.clk); | |
606 | hclk_low = clk_get_rate(&clk_hclk_low.clk); | |
607 | pclk_low = clk_get_rate(&clk_pclk_low.clk); | |
608 | ||
609 | printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ | |
610 | " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", | |
611 | print_mhz(hclk), print_mhz(hclk_low), | |
612 | print_mhz(pclk), print_mhz(pclk_low)); | |
613 | ||
614 | clk_f.rate = fclk; | |
615 | clk_h.rate = hclk; | |
616 | clk_p.rate = pclk; | |
617 | ||
618 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | |
619 | s3c_set_clksrc(&clksrcs[ptr], true); | |
620 | } | |
621 | ||
622 | void __init s5p6450_register_clocks(void) | |
623 | { | |
3109e550 KK |
624 | int ptr; |
625 | ||
626 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | |
627 | s3c_register_clksrc(sysclks[ptr], 1); | |
628 | ||
629 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | |
630 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | |
631 | ||
1526631d KK |
632 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
633 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | |
3109e550 KK |
634 | |
635 | s3c_pwmclk_init(); | |
636 | } |