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f1fee582 KK |
1 | /* linux/arch/arm/mach-s5p64x0/dma.c |
2 | * | |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
d8b5065b JB |
6 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. |
7 | * Jaswinder Singh <jassi.brar@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
f1fee582 | 22 | */ |
d8b5065b | 23 | |
d8b5065b | 24 | #include <linux/dma-mapping.h> |
3091e611 BK |
25 | #include <linux/amba/bus.h> |
26 | #include <linux/amba/pl330.h> | |
27 | ||
28 | #include <asm/irq.h> | |
d8b5065b | 29 | |
d8b5065b JB |
30 | #include <mach/map.h> |
31 | #include <mach/irqs.h> | |
f1fee582 | 32 | #include <mach/regs-clock.h> |
3091e611 | 33 | #include <mach/dma.h> |
d8b5065b | 34 | |
a3d93584 | 35 | #include <plat/cpu.h> |
f1fee582 | 36 | #include <plat/devs.h> |
3091e611 | 37 | #include <plat/irqs.h> |
d8b5065b | 38 | |
15545026 | 39 | static u8 s5p6440_pdma_peri[] = { |
dc732f50 TA |
40 | DMACH_UART0_RX, |
41 | DMACH_UART0_TX, | |
42 | DMACH_UART1_RX, | |
43 | DMACH_UART1_TX, | |
44 | DMACH_UART2_RX, | |
45 | DMACH_UART2_TX, | |
46 | DMACH_UART3_RX, | |
47 | DMACH_UART3_TX, | |
48 | DMACH_MAX, | |
49 | DMACH_MAX, | |
50 | DMACH_PCM0_TX, | |
51 | DMACH_PCM0_RX, | |
52 | DMACH_I2S0_TX, | |
53 | DMACH_I2S0_RX, | |
54 | DMACH_SPI0_TX, | |
55 | DMACH_SPI0_RX, | |
56 | DMACH_MAX, | |
57 | DMACH_MAX, | |
58 | DMACH_MAX, | |
59 | DMACH_MAX, | |
60 | DMACH_SPI1_TX, | |
61 | DMACH_SPI1_RX, | |
d8b5065b JB |
62 | }; |
63 | ||
15545026 | 64 | static struct dma_pl330_platdata s5p6440_pdma_pdata = { |
3091e611 | 65 | .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri), |
dc732f50 | 66 | .peri_id = s5p6440_pdma_peri, |
d8b5065b JB |
67 | }; |
68 | ||
15545026 | 69 | static u8 s5p6450_pdma_peri[] = { |
dc732f50 TA |
70 | DMACH_UART0_RX, |
71 | DMACH_UART0_TX, | |
72 | DMACH_UART1_RX, | |
73 | DMACH_UART1_TX, | |
74 | DMACH_UART2_RX, | |
75 | DMACH_UART2_TX, | |
76 | DMACH_UART3_RX, | |
77 | DMACH_UART3_TX, | |
78 | DMACH_UART4_RX, | |
79 | DMACH_UART4_TX, | |
80 | DMACH_PCM0_TX, | |
81 | DMACH_PCM0_RX, | |
82 | DMACH_I2S0_TX, | |
83 | DMACH_I2S0_RX, | |
84 | DMACH_SPI0_TX, | |
85 | DMACH_SPI0_RX, | |
86 | DMACH_PCM1_TX, | |
87 | DMACH_PCM1_RX, | |
88 | DMACH_PCM2_TX, | |
89 | DMACH_PCM2_RX, | |
90 | DMACH_SPI1_TX, | |
91 | DMACH_SPI1_RX, | |
92 | DMACH_USI_TX, | |
93 | DMACH_USI_RX, | |
94 | DMACH_MAX, | |
95 | DMACH_I2S1_TX, | |
96 | DMACH_I2S1_RX, | |
97 | DMACH_I2S2_TX, | |
98 | DMACH_I2S2_RX, | |
99 | DMACH_PWM, | |
100 | DMACH_UART5_RX, | |
101 | DMACH_UART5_TX, | |
f1fee582 KK |
102 | }; |
103 | ||
15545026 | 104 | static struct dma_pl330_platdata s5p6450_pdma_pdata = { |
3091e611 | 105 | .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri), |
dc732f50 | 106 | .peri_id = s5p6450_pdma_peri, |
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107 | }; |
108 | ||
60571f98 KK |
109 | static AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330, |
110 | S5P64X0_PA_PDMA, {IRQ_DMA0}, NULL); | |
d8b5065b | 111 | |
f1fee582 | 112 | static int __init s5p64x0_dma_init(void) |
d8b5065b | 113 | { |
dc732f50 TA |
114 | if (soc_is_s5p6450()) { |
115 | dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask); | |
116 | dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask); | |
75c06963 | 117 | s5p64x0_pdma_device.dev.platform_data = &s5p6450_pdma_pdata; |
dc732f50 TA |
118 | } else { |
119 | dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask); | |
120 | dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask); | |
75c06963 | 121 | s5p64x0_pdma_device.dev.platform_data = &s5p6440_pdma_pdata; |
dc732f50 | 122 | } |
f1fee582 | 123 | |
75c06963 | 124 | amba_device_register(&s5p64x0_pdma_device, &iomem_resource); |
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125 | |
126 | return 0; | |
127 | } | |
f1fee582 | 128 | arch_initcall(s5p64x0_dma_init); |