[deliverable/linux.git] / arch / arm / mach-s5p64x0 / dma.c

/* linux/arch/arm/mach-s5p64x0/dma.c
 *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
 *	Jaswinder Singh <jassi.brar@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#include <linux/dma-mapping.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl330.h>

#include <asm/irq.h>

#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/regs-clock.h>
#include <mach/dma.h>

#include <plat/devs.h>
#include <plat/irqs.h>

static u64 dma_dmamask = DMA_BIT_MASK(32);

struct dma_pl330_peri s5p6440_pdma_peri[22] = {
	{
		.peri_id = (u8)DMACH_UART0_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_UART0_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_UART1_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_UART1_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_UART2_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_UART2_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_UART3_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_UART3_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = DMACH_MAX,
	}, {
		.peri_id = DMACH_MAX,
	}, {
		.peri_id = (u8)DMACH_PCM0_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_PCM0_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_I2S0_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_I2S0_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_SPI0_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_SPI0_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_MAX,
	}, {
		.peri_id = (u8)DMACH_MAX,
	}, {
		.peri_id = (u8)DMACH_MAX,
	}, {
		.peri_id = (u8)DMACH_MAX,
	}, {
		.peri_id = (u8)DMACH_SPI1_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_SPI1_RX,
		.rqtype = DEVTOMEM,
	},
};

struct dma_pl330_platdata s5p6440_pdma_pdata = {
	.nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
	.peri = s5p6440_pdma_peri,
};

struct dma_pl330_peri s5p6450_pdma_peri[32] = {
	{
		.peri_id = (u8)DMACH_UART0_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_UART0_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_UART1_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_UART1_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_UART2_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_UART2_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_UART3_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_UART3_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_UART4_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_UART4_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_PCM0_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_PCM0_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_I2S0_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_I2S0_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_SPI0_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_SPI0_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_PCM1_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_PCM1_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_PCM2_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_PCM2_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_SPI1_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_SPI1_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_USI_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_USI_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_MAX,
	}, {
		.peri_id = (u8)DMACH_I2S1_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_I2S1_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_I2S2_TX,
		.rqtype = MEMTODEV,
	}, {
		.peri_id = (u8)DMACH_I2S2_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_PWM,
	}, {
		.peri_id = (u8)DMACH_UART5_RX,
		.rqtype = DEVTOMEM,
	}, {
		.peri_id = (u8)DMACH_UART5_TX,
		.rqtype = MEMTODEV,
	},
};

struct dma_pl330_platdata s5p6450_pdma_pdata = {
	.nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
	.peri = s5p6450_pdma_peri,
};

struct amba_device s5p64x0_device_pdma = {
	.dev = {
		.init_name = "dma-pl330",
		.dma_mask = &dma_dmamask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.res = {
		.start = S5P64X0_PA_PDMA,
		.end = S5P64X0_PA_PDMA + SZ_4K,
		.flags = IORESOURCE_MEM,
	},
	.irq = {IRQ_DMA0, NO_IRQ},
	.periphid = 0x00041330,
};

static int __init s5p64x0_dma_init(void)
{
	unsigned int id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;

	if (id == 0x50000)
		s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
	else
		s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;

	amba_device_register(&s5p64x0_device_pdma, &iomem_resource);

	return 0;
}
arch_initcall(s5p64x0_dma_init);
Commit	Line	Data
f1fee582 KK	1	/* linux/arch/arm/mach-s5p64x0/dma.c
	2	*
	3	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
d8b5065b JB	6	* Copyright (C) 2010 Samsung Electronics Co. Ltd.
	7	* Jaswinder Singh <jassi.brar@samsung.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
f1fee582	22	*/
d8b5065b	23
d8b5065b	24	#include <linux/dma-mapping.h>
3091e611 BK	25	#include <linux/amba/bus.h>
	26	#include <linux/amba/pl330.h>
	27
	28	#include <asm/irq.h>
d8b5065b	29
d8b5065b JB	30	#include <mach/map.h>
d8b5065b JB	31	#include <mach/irqs.h>
f1fee582	32	#include <mach/regs-clock.h>
3091e611	33	#include <mach/dma.h>
d8b5065b	34
f1fee582	35	#include <plat/devs.h>
3091e611	36	#include <plat/irqs.h>
d8b5065b JB	37
	38	static u64 dma_dmamask = DMA_BIT_MASK(32);
	39
3091e611 BK	40	struct dma_pl330_peri s5p6440_pdma_peri[22] = {
	41	{
	42	.peri_id = (u8)DMACH_UART0_RX,
	43	.rqtype = DEVTOMEM,
	44	}, {
	45	.peri_id = (u8)DMACH_UART0_TX,
	46	.rqtype = MEMTODEV,
	47	}, {
	48	.peri_id = (u8)DMACH_UART1_RX,
	49	.rqtype = DEVTOMEM,
	50	}, {
	51	.peri_id = (u8)DMACH_UART1_TX,
	52	.rqtype = MEMTODEV,
	53	}, {
	54	.peri_id = (u8)DMACH_UART2_RX,
	55	.rqtype = DEVTOMEM,
	56	}, {
	57	.peri_id = (u8)DMACH_UART2_TX,
	58	.rqtype = MEMTODEV,
	59	}, {
	60	.peri_id = (u8)DMACH_UART3_RX,
	61	.rqtype = DEVTOMEM,
	62	}, {
	63	.peri_id = (u8)DMACH_UART3_TX,
	64	.rqtype = MEMTODEV,
	65	}, {
	66	.peri_id = DMACH_MAX,
	67	}, {
	68	.peri_id = DMACH_MAX,
	69	}, {
	70	.peri_id = (u8)DMACH_PCM0_TX,
	71	.rqtype = MEMTODEV,
	72	}, {
	73	.peri_id = (u8)DMACH_PCM0_RX,
	74	.rqtype = DEVTOMEM,
	75	}, {
	76	.peri_id = (u8)DMACH_I2S0_TX,
	77	.rqtype = MEMTODEV,
	78	}, {
	79	.peri_id = (u8)DMACH_I2S0_RX,
	80	.rqtype = DEVTOMEM,
	81	}, {
	82	.peri_id = (u8)DMACH_SPI0_TX,
	83	.rqtype = MEMTODEV,
	84	}, {
	85	.peri_id = (u8)DMACH_SPI0_RX,
	86	.rqtype = DEVTOMEM,
	87	}, {
	88	.peri_id = (u8)DMACH_MAX,
	89	}, {
	90	.peri_id = (u8)DMACH_MAX,
	91	}, {
	92	.peri_id = (u8)DMACH_MAX,
	93	}, {
	94	.peri_id = (u8)DMACH_MAX,
	95	}, {
	96	.peri_id = (u8)DMACH_SPI1_TX,
	97	.rqtype = MEMTODEV,
	98	}, {
	99	.peri_id = (u8)DMACH_SPI1_RX,
	100	.rqtype = DEVTOMEM,
d8b5065b JB	101	},
	102	};
	103
3091e611 BK	104	struct dma_pl330_platdata s5p6440_pdma_pdata = {
	105	.nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
	106	.peri = s5p6440_pdma_peri,
d8b5065b JB	107	};
d8b5065b JB	108
3091e611 BK	109	struct dma_pl330_peri s5p6450_pdma_peri[32] = {
	110	{
	111	.peri_id = (u8)DMACH_UART0_RX,
	112	.rqtype = DEVTOMEM,
	113	}, {
	114	.peri_id = (u8)DMACH_UART0_TX,
	115	.rqtype = MEMTODEV,
	116	}, {
	117	.peri_id = (u8)DMACH_UART1_RX,
	118	.rqtype = DEVTOMEM,
	119	}, {
	120	.peri_id = (u8)DMACH_UART1_TX,
	121	.rqtype = MEMTODEV,
	122	}, {
	123	.peri_id = (u8)DMACH_UART2_RX,
	124	.rqtype = DEVTOMEM,
	125	}, {
	126	.peri_id = (u8)DMACH_UART2_TX,
	127	.rqtype = MEMTODEV,
	128	}, {
	129	.peri_id = (u8)DMACH_UART3_RX,
	130	.rqtype = DEVTOMEM,
	131	}, {
	132	.peri_id = (u8)DMACH_UART3_TX,
	133	.rqtype = MEMTODEV,
	134	}, {
	135	.peri_id = (u8)DMACH_UART4_RX,
	136	.rqtype = DEVTOMEM,
	137	}, {
	138	.peri_id = (u8)DMACH_UART4_TX,
	139	.rqtype = MEMTODEV,
	140	}, {
	141	.peri_id = (u8)DMACH_PCM0_TX,
	142	.rqtype = MEMTODEV,
	143	}, {
	144	.peri_id = (u8)DMACH_PCM0_RX,
	145	.rqtype = DEVTOMEM,
	146	}, {
	147	.peri_id = (u8)DMACH_I2S0_TX,
	148	.rqtype = MEMTODEV,
	149	}, {
	150	.peri_id = (u8)DMACH_I2S0_RX,
	151	.rqtype = DEVTOMEM,
	152	}, {
	153	.peri_id = (u8)DMACH_SPI0_TX,
	154	.rqtype = MEMTODEV,
	155	}, {
	156	.peri_id = (u8)DMACH_SPI0_RX,
	157	.rqtype = DEVTOMEM,
	158	}, {
	159	.peri_id = (u8)DMACH_PCM1_TX,
	160	.rqtype = MEMTODEV,
	161	}, {
	162	.peri_id = (u8)DMACH_PCM1_RX,
	163	.rqtype = DEVTOMEM,
	164	}, {
	165	.peri_id = (u8)DMACH_PCM2_TX,
	166	.rqtype = MEMTODEV,
	167	}, {
	168	.peri_id = (u8)DMACH_PCM2_RX,
	169	.rqtype = DEVTOMEM,
	170	}, {
	171	.peri_id = (u8)DMACH_SPI1_TX,
	172	.rqtype = MEMTODEV,
173	}, {
174	.peri_id = (u8)DMACH_SPI1_RX,
175	.rqtype = DEVTOMEM,
176	}, {
177	.peri_id = (u8)DMACH_USI_TX,
178	.rqtype = MEMTODEV,
179	}, {
180	.peri_id = (u8)DMACH_USI_RX,
181	.rqtype = DEVTOMEM,
182	}, {
183	.peri_id = (u8)DMACH_MAX,
184	}, {
185	.peri_id = (u8)DMACH_I2S1_TX,
186	.rqtype = MEMTODEV,
187	}, {
188	.peri_id = (u8)DMACH_I2S1_RX,
189	.rqtype = DEVTOMEM,
190	}, {
191	.peri_id = (u8)DMACH_I2S2_TX,
192	.rqtype = MEMTODEV,
193	}, {
194	.peri_id = (u8)DMACH_I2S2_RX,
195	.rqtype = DEVTOMEM,
196	}, {
197	.peri_id = (u8)DMACH_PWM,
198	}, {
199	.peri_id = (u8)DMACH_UART5_RX,
200	.rqtype = DEVTOMEM,
201	}, {
202	.peri_id = (u8)DMACH_UART5_TX,
203	.rqtype = MEMTODEV,
f1fee582 KK	204	},
	205	};
	206
3091e611 BK	207	struct dma_pl330_platdata s5p6450_pdma_pdata = {
	208	.nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
	209	.peri = s5p6450_pdma_peri,
	210	};
	211
	212	struct amba_device s5p64x0_device_pdma = {
	213	.dev = {
	214	.init_name = "dma-pl330",
d8b5065b JB	215	.dma_mask = &dma_dmamask,
d8b5065b JB	216	.coherent_dma_mask = DMA_BIT_MASK(32),
d8b5065b	217	},
3091e611 BK	218	.res = {
	219	.start = S5P64X0_PA_PDMA,
	220	.end = S5P64X0_PA_PDMA + SZ_4K,
	221	.flags = IORESOURCE_MEM,
	222	},
	223	.irq = {IRQ_DMA0, NO_IRQ},
	224	.periphid = 0x00041330,
d8b5065b JB	225	};
d8b5065b JB	226
f1fee582	227	static int __init s5p64x0_dma_init(void)
d8b5065b	228	{
3091e611	229	unsigned int id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
f1fee582 KK	230
	231	if (id == 0x50000)
	232	s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
	233	else
	234	s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
	235
3091e611	236	amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
d8b5065b JB	237
	238	return 0;
	239	}
f1fee582	240	arch_initcall(s5p64x0_dma_init);