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a443a637 TA |
1 | /* linux/arch/arm/mach-s5pc100/clock.c |
2 | * | |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * S5PC100 - Clock support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/io.h> | |
20 | ||
21 | #include <mach/map.h> | |
22 | ||
23 | #include <plat/cpu-freq.h> | |
24 | #include <mach/regs-clock.h> | |
25 | #include <plat/clock.h> | |
26 | #include <plat/cpu.h> | |
27 | #include <plat/pll.h> | |
28 | #include <plat/s5p-clock.h> | |
29 | #include <plat/clock-clksrc.h> | |
dd4153d9 KK |
30 | |
31 | #include "common.h" | |
a443a637 TA |
32 | |
33 | static struct clk s5p_clk_otgphy = { | |
34 | .name = "otg_phy", | |
a443a637 TA |
35 | }; |
36 | ||
a422bd0f BK |
37 | static struct clk dummy_apb_pclk = { |
38 | .name = "apb_pclk", | |
39 | .id = -1, | |
40 | }; | |
41 | ||
a443a637 TA |
42 | static struct clk *clk_src_mout_href_list[] = { |
43 | [0] = &s5p_clk_27m, | |
44 | [1] = &clk_fin_hpll, | |
45 | }; | |
46 | ||
47 | static struct clksrc_sources clk_src_mout_href = { | |
48 | .sources = clk_src_mout_href_list, | |
49 | .nr_sources = ARRAY_SIZE(clk_src_mout_href_list), | |
50 | }; | |
51 | ||
52 | static struct clksrc_clk clk_mout_href = { | |
53 | .clk = { | |
54 | .name = "mout_href", | |
a443a637 TA |
55 | }, |
56 | .sources = &clk_src_mout_href, | |
57 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, | |
58 | }; | |
59 | ||
60 | static struct clk *clk_src_mout_48m_list[] = { | |
61 | [0] = &clk_xusbxti, | |
62 | [1] = &s5p_clk_otgphy, | |
63 | }; | |
64 | ||
65 | static struct clksrc_sources clk_src_mout_48m = { | |
66 | .sources = clk_src_mout_48m_list, | |
67 | .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list), | |
68 | }; | |
69 | ||
70 | static struct clksrc_clk clk_mout_48m = { | |
71 | .clk = { | |
72 | .name = "mout_48m", | |
a443a637 TA |
73 | }, |
74 | .sources = &clk_src_mout_48m, | |
75 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 }, | |
76 | }; | |
77 | ||
78 | static struct clksrc_clk clk_mout_mpll = { | |
79 | .clk = { | |
80 | .name = "mout_mpll", | |
a443a637 TA |
81 | }, |
82 | .sources = &clk_src_mpll, | |
83 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, | |
84 | }; | |
85 | ||
86 | ||
87 | static struct clksrc_clk clk_mout_apll = { | |
88 | .clk = { | |
89 | .name = "mout_apll", | |
a443a637 TA |
90 | }, |
91 | .sources = &clk_src_apll, | |
92 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | |
93 | }; | |
94 | ||
95 | static struct clksrc_clk clk_mout_epll = { | |
96 | .clk = { | |
97 | .name = "mout_epll", | |
a443a637 TA |
98 | }, |
99 | .sources = &clk_src_epll, | |
100 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, | |
101 | }; | |
102 | ||
103 | static struct clk *clk_src_mout_hpll_list[] = { | |
104 | [0] = &s5p_clk_27m, | |
105 | }; | |
106 | ||
107 | static struct clksrc_sources clk_src_mout_hpll = { | |
108 | .sources = clk_src_mout_hpll_list, | |
109 | .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list), | |
110 | }; | |
111 | ||
112 | static struct clksrc_clk clk_mout_hpll = { | |
113 | .clk = { | |
114 | .name = "mout_hpll", | |
a443a637 TA |
115 | }, |
116 | .sources = &clk_src_mout_hpll, | |
117 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, | |
118 | }; | |
119 | ||
120 | static struct clksrc_clk clk_div_apll = { | |
121 | .clk = { | |
122 | .name = "div_apll", | |
a443a637 TA |
123 | .parent = &clk_mout_apll.clk, |
124 | }, | |
125 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, | |
126 | }; | |
127 | ||
128 | static struct clksrc_clk clk_div_arm = { | |
129 | .clk = { | |
130 | .name = "div_arm", | |
a443a637 TA |
131 | .parent = &clk_div_apll.clk, |
132 | }, | |
133 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, | |
134 | }; | |
135 | ||
136 | static struct clksrc_clk clk_div_d0_bus = { | |
137 | .clk = { | |
138 | .name = "div_d0_bus", | |
a443a637 TA |
139 | .parent = &clk_div_arm.clk, |
140 | }, | |
141 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, | |
142 | }; | |
143 | ||
144 | static struct clksrc_clk clk_div_pclkd0 = { | |
145 | .clk = { | |
146 | .name = "div_pclkd0", | |
a443a637 TA |
147 | .parent = &clk_div_d0_bus.clk, |
148 | }, | |
149 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, | |
150 | }; | |
151 | ||
152 | static struct clksrc_clk clk_div_secss = { | |
153 | .clk = { | |
154 | .name = "div_secss", | |
a443a637 TA |
155 | .parent = &clk_div_d0_bus.clk, |
156 | }, | |
157 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 }, | |
158 | }; | |
159 | ||
160 | static struct clksrc_clk clk_div_apll2 = { | |
161 | .clk = { | |
162 | .name = "div_apll2", | |
a443a637 TA |
163 | .parent = &clk_mout_apll.clk, |
164 | }, | |
165 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 }, | |
166 | }; | |
167 | ||
168 | static struct clk *clk_src_mout_am_list[] = { | |
169 | [0] = &clk_mout_mpll.clk, | |
170 | [1] = &clk_div_apll2.clk, | |
171 | }; | |
172 | ||
ad016770 | 173 | static struct clksrc_sources clk_src_mout_am = { |
a443a637 TA |
174 | .sources = clk_src_mout_am_list, |
175 | .nr_sources = ARRAY_SIZE(clk_src_mout_am_list), | |
176 | }; | |
177 | ||
178 | static struct clksrc_clk clk_mout_am = { | |
179 | .clk = { | |
180 | .name = "mout_am", | |
a443a637 TA |
181 | }, |
182 | .sources = &clk_src_mout_am, | |
183 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, | |
184 | }; | |
185 | ||
186 | static struct clksrc_clk clk_div_d1_bus = { | |
187 | .clk = { | |
188 | .name = "div_d1_bus", | |
a443a637 TA |
189 | .parent = &clk_mout_am.clk, |
190 | }, | |
191 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 }, | |
192 | }; | |
193 | ||
194 | static struct clksrc_clk clk_div_mpll2 = { | |
195 | .clk = { | |
196 | .name = "div_mpll2", | |
a443a637 TA |
197 | .parent = &clk_mout_am.clk, |
198 | }, | |
199 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 }, | |
200 | }; | |
201 | ||
202 | static struct clksrc_clk clk_div_mpll = { | |
203 | .clk = { | |
204 | .name = "div_mpll", | |
a443a637 TA |
205 | .parent = &clk_mout_am.clk, |
206 | }, | |
207 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 }, | |
208 | }; | |
209 | ||
210 | static struct clk *clk_src_mout_onenand_list[] = { | |
211 | [0] = &clk_div_d0_bus.clk, | |
212 | [1] = &clk_div_d1_bus.clk, | |
213 | }; | |
214 | ||
ad016770 | 215 | static struct clksrc_sources clk_src_mout_onenand = { |
a443a637 TA |
216 | .sources = clk_src_mout_onenand_list, |
217 | .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list), | |
218 | }; | |
219 | ||
220 | static struct clksrc_clk clk_mout_onenand = { | |
221 | .clk = { | |
222 | .name = "mout_onenand", | |
a443a637 TA |
223 | }, |
224 | .sources = &clk_src_mout_onenand, | |
225 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, | |
226 | }; | |
227 | ||
228 | static struct clksrc_clk clk_div_onenand = { | |
229 | .clk = { | |
230 | .name = "div_onenand", | |
a443a637 TA |
231 | .parent = &clk_mout_onenand.clk, |
232 | }, | |
233 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 }, | |
234 | }; | |
235 | ||
236 | static struct clksrc_clk clk_div_pclkd1 = { | |
237 | .clk = { | |
238 | .name = "div_pclkd1", | |
a443a637 TA |
239 | .parent = &clk_div_d1_bus.clk, |
240 | }, | |
241 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 }, | |
242 | }; | |
243 | ||
244 | static struct clksrc_clk clk_div_cam = { | |
245 | .clk = { | |
246 | .name = "div_cam", | |
a443a637 TA |
247 | .parent = &clk_div_mpll2.clk, |
248 | }, | |
249 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 }, | |
250 | }; | |
251 | ||
252 | static struct clksrc_clk clk_div_hdmi = { | |
253 | .clk = { | |
254 | .name = "div_hdmi", | |
a443a637 TA |
255 | .parent = &clk_mout_hpll.clk, |
256 | }, | |
257 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, | |
258 | }; | |
259 | ||
a443a637 TA |
260 | static u32 epll_div[][4] = { |
261 | { 32750000, 131, 3, 4 }, | |
262 | { 32768000, 131, 3, 4 }, | |
263 | { 36000000, 72, 3, 3 }, | |
264 | { 45000000, 90, 3, 3 }, | |
265 | { 45158000, 90, 3, 3 }, | |
266 | { 45158400, 90, 3, 3 }, | |
267 | { 48000000, 96, 3, 3 }, | |
268 | { 49125000, 131, 4, 3 }, | |
269 | { 49152000, 131, 4, 3 }, | |
270 | { 60000000, 120, 3, 3 }, | |
271 | { 67737600, 226, 5, 3 }, | |
272 | { 67738000, 226, 5, 3 }, | |
273 | { 73800000, 246, 5, 3 }, | |
274 | { 73728000, 246, 5, 3 }, | |
275 | { 72000000, 144, 3, 3 }, | |
276 | { 84000000, 168, 3, 3 }, | |
277 | { 96000000, 96, 3, 2 }, | |
278 | { 144000000, 144, 3, 2 }, | |
279 | { 192000000, 96, 3, 1 } | |
280 | }; | |
281 | ||
282 | static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate) | |
283 | { | |
284 | unsigned int epll_con; | |
285 | unsigned int i; | |
286 | ||
287 | if (clk->rate == rate) /* Return if nothing changed */ | |
288 | return 0; | |
289 | ||
290 | epll_con = __raw_readl(S5P_EPLL_CON); | |
291 | ||
292 | epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK); | |
293 | ||
294 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { | |
295 | if (epll_div[i][0] == rate) { | |
296 | epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) | | |
297 | (epll_div[i][2] << PLL65XX_PDIV_SHIFT) | | |
298 | (epll_div[i][3] << PLL65XX_SDIV_SHIFT); | |
299 | break; | |
300 | } | |
301 | } | |
302 | ||
303 | if (i == ARRAY_SIZE(epll_div)) { | |
304 | printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__); | |
305 | return -EINVAL; | |
306 | } | |
307 | ||
308 | __raw_writel(epll_con, S5P_EPLL_CON); | |
309 | ||
9616674a SY |
310 | printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", |
311 | clk->rate, rate); | |
312 | ||
a443a637 TA |
313 | clk->rate = rate; |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
318 | static struct clk_ops s5pc100_epll_ops = { | |
d4b34c6c | 319 | .get_rate = s5p_epll_get_rate, |
a443a637 TA |
320 | .set_rate = s5pc100_epll_set_rate, |
321 | }; | |
322 | ||
323 | static int s5pc100_d0_0_ctrl(struct clk *clk, int enable) | |
324 | { | |
325 | return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable); | |
326 | } | |
327 | ||
328 | static int s5pc100_d0_1_ctrl(struct clk *clk, int enable) | |
329 | { | |
330 | return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable); | |
331 | } | |
332 | ||
333 | static int s5pc100_d0_2_ctrl(struct clk *clk, int enable) | |
334 | { | |
335 | return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable); | |
336 | } | |
337 | ||
338 | static int s5pc100_d1_0_ctrl(struct clk *clk, int enable) | |
339 | { | |
340 | return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable); | |
341 | } | |
342 | ||
343 | static int s5pc100_d1_1_ctrl(struct clk *clk, int enable) | |
344 | { | |
345 | return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable); | |
346 | } | |
347 | ||
348 | static int s5pc100_d1_2_ctrl(struct clk *clk, int enable) | |
349 | { | |
350 | return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable); | |
351 | } | |
352 | ||
353 | static int s5pc100_d1_3_ctrl(struct clk *clk, int enable) | |
354 | { | |
355 | return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable); | |
356 | } | |
357 | ||
358 | static int s5pc100_d1_4_ctrl(struct clk *clk, int enable) | |
359 | { | |
360 | return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable); | |
361 | } | |
362 | ||
363 | static int s5pc100_d1_5_ctrl(struct clk *clk, int enable) | |
364 | { | |
365 | return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable); | |
366 | } | |
367 | ||
368 | static int s5pc100_sclk0_ctrl(struct clk *clk, int enable) | |
369 | { | |
370 | return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable); | |
371 | } | |
372 | ||
373 | static int s5pc100_sclk1_ctrl(struct clk *clk, int enable) | |
374 | { | |
375 | return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable); | |
376 | } | |
377 | ||
378 | /* | |
379 | * The following clocks will be disabled during clock initialization. It is | |
380 | * recommended to keep the following clocks disabled until the driver requests | |
381 | * for enabling the clock. | |
382 | */ | |
96ee39c4 | 383 | static struct clk init_clocks_off[] = { |
a443a637 TA |
384 | { |
385 | .name = "cssys", | |
a443a637 TA |
386 | .parent = &clk_div_d0_bus.clk, |
387 | .enable = s5pc100_d0_0_ctrl, | |
388 | .ctrlbit = (1 << 6), | |
389 | }, { | |
390 | .name = "secss", | |
a443a637 TA |
391 | .parent = &clk_div_d0_bus.clk, |
392 | .enable = s5pc100_d0_0_ctrl, | |
393 | .ctrlbit = (1 << 5), | |
394 | }, { | |
395 | .name = "g2d", | |
a443a637 TA |
396 | .parent = &clk_div_d0_bus.clk, |
397 | .enable = s5pc100_d0_0_ctrl, | |
398 | .ctrlbit = (1 << 4), | |
399 | }, { | |
400 | .name = "mdma", | |
a443a637 TA |
401 | .parent = &clk_div_d0_bus.clk, |
402 | .enable = s5pc100_d0_0_ctrl, | |
403 | .ctrlbit = (1 << 3), | |
404 | }, { | |
405 | .name = "cfcon", | |
a443a637 TA |
406 | .parent = &clk_div_d0_bus.clk, |
407 | .enable = s5pc100_d0_0_ctrl, | |
408 | .ctrlbit = (1 << 2), | |
409 | }, { | |
410 | .name = "nfcon", | |
a443a637 TA |
411 | .parent = &clk_div_d0_bus.clk, |
412 | .enable = s5pc100_d0_1_ctrl, | |
413 | .ctrlbit = (1 << 3), | |
414 | }, { | |
415 | .name = "onenandc", | |
a443a637 TA |
416 | .parent = &clk_div_d0_bus.clk, |
417 | .enable = s5pc100_d0_1_ctrl, | |
418 | .ctrlbit = (1 << 2), | |
419 | }, { | |
420 | .name = "sdm", | |
a443a637 TA |
421 | .parent = &clk_div_d0_bus.clk, |
422 | .enable = s5pc100_d0_2_ctrl, | |
423 | .ctrlbit = (1 << 2), | |
424 | }, { | |
425 | .name = "seckey", | |
a443a637 TA |
426 | .parent = &clk_div_d0_bus.clk, |
427 | .enable = s5pc100_d0_2_ctrl, | |
428 | .ctrlbit = (1 << 1), | |
a443a637 TA |
429 | }, { |
430 | .name = "modemif", | |
a443a637 TA |
431 | .parent = &clk_div_d1_bus.clk, |
432 | .enable = s5pc100_d1_0_ctrl, | |
433 | .ctrlbit = (1 << 4), | |
434 | }, { | |
435 | .name = "otg", | |
a443a637 TA |
436 | .parent = &clk_div_d1_bus.clk, |
437 | .enable = s5pc100_d1_0_ctrl, | |
438 | .ctrlbit = (1 << 3), | |
439 | }, { | |
440 | .name = "usbhost", | |
a443a637 TA |
441 | .parent = &clk_div_d1_bus.clk, |
442 | .enable = s5pc100_d1_0_ctrl, | |
443 | .ctrlbit = (1 << 2), | |
444 | }, { | |
a422bd0f | 445 | .name = "dma", |
d20cc4c1 | 446 | .devname = "dma-pl330.1", |
a443a637 TA |
447 | .parent = &clk_div_d1_bus.clk, |
448 | .enable = s5pc100_d1_0_ctrl, | |
449 | .ctrlbit = (1 << 1), | |
450 | }, { | |
a422bd0f | 451 | .name = "dma", |
d20cc4c1 | 452 | .devname = "dma-pl330.0", |
a443a637 TA |
453 | .parent = &clk_div_d1_bus.clk, |
454 | .enable = s5pc100_d1_0_ctrl, | |
455 | .ctrlbit = (1 << 0), | |
456 | }, { | |
457 | .name = "lcd", | |
a443a637 TA |
458 | .parent = &clk_div_d1_bus.clk, |
459 | .enable = s5pc100_d1_1_ctrl, | |
460 | .ctrlbit = (1 << 0), | |
461 | }, { | |
462 | .name = "rotator", | |
a443a637 TA |
463 | .parent = &clk_div_d1_bus.clk, |
464 | .enable = s5pc100_d1_1_ctrl, | |
465 | .ctrlbit = (1 << 1), | |
466 | }, { | |
467 | .name = "fimc", | |
29e8eb0f | 468 | .devname = "s5p-fimc.0", |
a443a637 TA |
469 | .parent = &clk_div_d1_bus.clk, |
470 | .enable = s5pc100_d1_1_ctrl, | |
471 | .ctrlbit = (1 << 2), | |
472 | }, { | |
473 | .name = "fimc", | |
29e8eb0f | 474 | .devname = "s5p-fimc.1", |
a443a637 TA |
475 | .parent = &clk_div_d1_bus.clk, |
476 | .enable = s5pc100_d1_1_ctrl, | |
477 | .ctrlbit = (1 << 3), | |
478 | }, { | |
479 | .name = "fimc", | |
29e8eb0f | 480 | .devname = "s5p-fimc.2", |
a443a637 TA |
481 | .enable = s5pc100_d1_1_ctrl, |
482 | .ctrlbit = (1 << 4), | |
483 | }, { | |
484 | .name = "jpeg", | |
a443a637 TA |
485 | .parent = &clk_div_d1_bus.clk, |
486 | .enable = s5pc100_d1_1_ctrl, | |
487 | .ctrlbit = (1 << 5), | |
488 | }, { | |
489 | .name = "mipi-dsim", | |
a443a637 TA |
490 | .parent = &clk_div_d1_bus.clk, |
491 | .enable = s5pc100_d1_1_ctrl, | |
492 | .ctrlbit = (1 << 6), | |
493 | }, { | |
494 | .name = "mipi-csis", | |
a443a637 TA |
495 | .parent = &clk_div_d1_bus.clk, |
496 | .enable = s5pc100_d1_1_ctrl, | |
497 | .ctrlbit = (1 << 7), | |
498 | }, { | |
499 | .name = "g3d", | |
a443a637 TA |
500 | .parent = &clk_div_d1_bus.clk, |
501 | .enable = s5pc100_d1_0_ctrl, | |
502 | .ctrlbit = (1 << 8), | |
503 | }, { | |
504 | .name = "tv", | |
a443a637 TA |
505 | .parent = &clk_div_d1_bus.clk, |
506 | .enable = s5pc100_d1_2_ctrl, | |
507 | .ctrlbit = (1 << 0), | |
508 | }, { | |
509 | .name = "vp", | |
a443a637 TA |
510 | .parent = &clk_div_d1_bus.clk, |
511 | .enable = s5pc100_d1_2_ctrl, | |
512 | .ctrlbit = (1 << 1), | |
513 | }, { | |
514 | .name = "mixer", | |
a443a637 TA |
515 | .parent = &clk_div_d1_bus.clk, |
516 | .enable = s5pc100_d1_2_ctrl, | |
517 | .ctrlbit = (1 << 2), | |
518 | }, { | |
519 | .name = "hdmi", | |
a443a637 TA |
520 | .parent = &clk_div_d1_bus.clk, |
521 | .enable = s5pc100_d1_2_ctrl, | |
522 | .ctrlbit = (1 << 3), | |
523 | }, { | |
524 | .name = "mfc", | |
a443a637 TA |
525 | .parent = &clk_div_d1_bus.clk, |
526 | .enable = s5pc100_d1_2_ctrl, | |
527 | .ctrlbit = (1 << 4), | |
528 | }, { | |
529 | .name = "apc", | |
a443a637 TA |
530 | .parent = &clk_div_d1_bus.clk, |
531 | .enable = s5pc100_d1_3_ctrl, | |
532 | .ctrlbit = (1 << 2), | |
533 | }, { | |
534 | .name = "iec", | |
a443a637 TA |
535 | .parent = &clk_div_d1_bus.clk, |
536 | .enable = s5pc100_d1_3_ctrl, | |
537 | .ctrlbit = (1 << 3), | |
538 | }, { | |
539 | .name = "systimer", | |
a443a637 TA |
540 | .parent = &clk_div_d1_bus.clk, |
541 | .enable = s5pc100_d1_3_ctrl, | |
542 | .ctrlbit = (1 << 7), | |
543 | }, { | |
544 | .name = "watchdog", | |
a443a637 TA |
545 | .parent = &clk_div_d1_bus.clk, |
546 | .enable = s5pc100_d1_3_ctrl, | |
547 | .ctrlbit = (1 << 8), | |
548 | }, { | |
549 | .name = "rtc", | |
a443a637 TA |
550 | .parent = &clk_div_d1_bus.clk, |
551 | .enable = s5pc100_d1_3_ctrl, | |
552 | .ctrlbit = (1 << 9), | |
553 | }, { | |
554 | .name = "i2c", | |
29e8eb0f | 555 | .devname = "s3c2440-i2c.0", |
a443a637 TA |
556 | .parent = &clk_div_d1_bus.clk, |
557 | .enable = s5pc100_d1_4_ctrl, | |
558 | .ctrlbit = (1 << 4), | |
559 | }, { | |
560 | .name = "i2c", | |
29e8eb0f | 561 | .devname = "s3c2440-i2c.1", |
a443a637 TA |
562 | .parent = &clk_div_d1_bus.clk, |
563 | .enable = s5pc100_d1_4_ctrl, | |
564 | .ctrlbit = (1 << 5), | |
565 | }, { | |
566 | .name = "spi", | |
a5238e36 | 567 | .devname = "s5pc100-spi.0", |
a443a637 TA |
568 | .parent = &clk_div_d1_bus.clk, |
569 | .enable = s5pc100_d1_4_ctrl, | |
570 | .ctrlbit = (1 << 6), | |
571 | }, { | |
572 | .name = "spi", | |
a5238e36 | 573 | .devname = "s5pc100-spi.1", |
a443a637 TA |
574 | .parent = &clk_div_d1_bus.clk, |
575 | .enable = s5pc100_d1_4_ctrl, | |
576 | .ctrlbit = (1 << 7), | |
577 | }, { | |
578 | .name = "spi", | |
a5238e36 | 579 | .devname = "s5pc100-spi.2", |
a443a637 TA |
580 | .parent = &clk_div_d1_bus.clk, |
581 | .enable = s5pc100_d1_4_ctrl, | |
582 | .ctrlbit = (1 << 8), | |
583 | }, { | |
584 | .name = "irda", | |
a443a637 TA |
585 | .parent = &clk_div_d1_bus.clk, |
586 | .enable = s5pc100_d1_4_ctrl, | |
587 | .ctrlbit = (1 << 9), | |
588 | }, { | |
589 | .name = "ccan", | |
a443a637 TA |
590 | .parent = &clk_div_d1_bus.clk, |
591 | .enable = s5pc100_d1_4_ctrl, | |
592 | .ctrlbit = (1 << 10), | |
593 | }, { | |
594 | .name = "ccan", | |
a443a637 TA |
595 | .parent = &clk_div_d1_bus.clk, |
596 | .enable = s5pc100_d1_4_ctrl, | |
597 | .ctrlbit = (1 << 11), | |
598 | }, { | |
599 | .name = "hsitx", | |
a443a637 TA |
600 | .parent = &clk_div_d1_bus.clk, |
601 | .enable = s5pc100_d1_4_ctrl, | |
602 | .ctrlbit = (1 << 12), | |
603 | }, { | |
604 | .name = "hsirx", | |
a443a637 TA |
605 | .parent = &clk_div_d1_bus.clk, |
606 | .enable = s5pc100_d1_4_ctrl, | |
607 | .ctrlbit = (1 << 13), | |
a443a637 TA |
608 | }, { |
609 | .name = "ac97", | |
05daf079 | 610 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
611 | .enable = s5pc100_d1_5_ctrl, |
612 | .ctrlbit = (1 << 3), | |
613 | }, { | |
614 | .name = "pcm", | |
29e8eb0f | 615 | .devname = "samsung-pcm.0", |
05daf079 | 616 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
617 | .enable = s5pc100_d1_5_ctrl, |
618 | .ctrlbit = (1 << 4), | |
619 | }, { | |
620 | .name = "pcm", | |
29e8eb0f | 621 | .devname = "samsung-pcm.1", |
05daf079 | 622 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
623 | .enable = s5pc100_d1_5_ctrl, |
624 | .ctrlbit = (1 << 5), | |
625 | }, { | |
626 | .name = "spdif", | |
05daf079 | 627 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
628 | .enable = s5pc100_d1_5_ctrl, |
629 | .ctrlbit = (1 << 6), | |
630 | }, { | |
631 | .name = "adc", | |
05daf079 | 632 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
633 | .enable = s5pc100_d1_5_ctrl, |
634 | .ctrlbit = (1 << 7), | |
635 | }, { | |
32018a8c | 636 | .name = "keypad", |
05daf079 | 637 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
638 | .enable = s5pc100_d1_5_ctrl, |
639 | .ctrlbit = (1 << 8), | |
a443a637 TA |
640 | }, { |
641 | .name = "mmc_48m", | |
29e8eb0f | 642 | .devname = "s3c-sdhci.0", |
a443a637 TA |
643 | .parent = &clk_mout_48m.clk, |
644 | .enable = s5pc100_sclk0_ctrl, | |
645 | .ctrlbit = (1 << 15), | |
646 | }, { | |
647 | .name = "mmc_48m", | |
29e8eb0f | 648 | .devname = "s3c-sdhci.1", |
a443a637 TA |
649 | .parent = &clk_mout_48m.clk, |
650 | .enable = s5pc100_sclk0_ctrl, | |
651 | .ctrlbit = (1 << 16), | |
652 | }, { | |
653 | .name = "mmc_48m", | |
29e8eb0f | 654 | .devname = "s3c-sdhci.2", |
a443a637 TA |
655 | .parent = &clk_mout_48m.clk, |
656 | .enable = s5pc100_sclk0_ctrl, | |
657 | .ctrlbit = (1 << 17), | |
658 | }, | |
659 | }; | |
660 | ||
a361d10a RS |
661 | static struct clk clk_hsmmc2 = { |
662 | .name = "hsmmc", | |
663 | .devname = "s3c-sdhci.2", | |
664 | .parent = &clk_div_d1_bus.clk, | |
665 | .enable = s5pc100_d1_0_ctrl, | |
666 | .ctrlbit = (1 << 7), | |
667 | }; | |
668 | ||
669 | static struct clk clk_hsmmc1 = { | |
670 | .name = "hsmmc", | |
671 | .devname = "s3c-sdhci.1", | |
672 | .parent = &clk_div_d1_bus.clk, | |
673 | .enable = s5pc100_d1_0_ctrl, | |
674 | .ctrlbit = (1 << 6), | |
675 | }; | |
676 | ||
677 | static struct clk clk_hsmmc0 = { | |
678 | .name = "hsmmc", | |
679 | .devname = "s3c-sdhci.0", | |
680 | .parent = &clk_div_d1_bus.clk, | |
681 | .enable = s5pc100_d1_0_ctrl, | |
682 | .ctrlbit = (1 << 5), | |
683 | }; | |
684 | ||
02717bb9 PV |
685 | static struct clk clk_48m_spi0 = { |
686 | .name = "spi_48m", | |
a5238e36 | 687 | .devname = "s5pc100-spi.0", |
02717bb9 PV |
688 | .parent = &clk_mout_48m.clk, |
689 | .enable = s5pc100_sclk0_ctrl, | |
690 | .ctrlbit = (1 << 7), | |
691 | }; | |
692 | ||
693 | static struct clk clk_48m_spi1 = { | |
694 | .name = "spi_48m", | |
a5238e36 | 695 | .devname = "s5pc100-spi.1", |
02717bb9 PV |
696 | .parent = &clk_mout_48m.clk, |
697 | .enable = s5pc100_sclk0_ctrl, | |
698 | .ctrlbit = (1 << 8), | |
699 | }; | |
700 | ||
701 | static struct clk clk_48m_spi2 = { | |
702 | .name = "spi_48m", | |
a5238e36 | 703 | .devname = "s5pc100-spi.2", |
02717bb9 PV |
704 | .parent = &clk_mout_48m.clk, |
705 | .enable = s5pc100_sclk0_ctrl, | |
706 | .ctrlbit = (1 << 9), | |
707 | }; | |
708 | ||
eaff82ed PV |
709 | static struct clk clk_i2s0 = { |
710 | .name = "iis", | |
711 | .devname = "samsung-i2s.0", | |
712 | .parent = &clk_div_pclkd1.clk, | |
713 | .enable = s5pc100_d1_5_ctrl, | |
714 | .ctrlbit = (1 << 0), | |
715 | }; | |
716 | ||
717 | static struct clk clk_i2s1 = { | |
718 | .name = "iis", | |
719 | .devname = "samsung-i2s.1", | |
720 | .parent = &clk_div_pclkd1.clk, | |
721 | .enable = s5pc100_d1_5_ctrl, | |
722 | .ctrlbit = (1 << 1), | |
723 | }; | |
724 | ||
725 | static struct clk clk_i2s2 = { | |
726 | .name = "iis", | |
727 | .devname = "samsung-i2s.2", | |
728 | .parent = &clk_div_pclkd1.clk, | |
729 | .enable = s5pc100_d1_5_ctrl, | |
730 | .ctrlbit = (1 << 2), | |
731 | }; | |
732 | ||
a443a637 TA |
733 | static struct clk clk_vclk54m = { |
734 | .name = "vclk_54m", | |
a443a637 TA |
735 | .rate = 54000000, |
736 | }; | |
737 | ||
738 | static struct clk clk_i2scdclk0 = { | |
739 | .name = "i2s_cdclk0", | |
a443a637 TA |
740 | }; |
741 | ||
742 | static struct clk clk_i2scdclk1 = { | |
743 | .name = "i2s_cdclk1", | |
a443a637 TA |
744 | }; |
745 | ||
746 | static struct clk clk_i2scdclk2 = { | |
747 | .name = "i2s_cdclk2", | |
a443a637 TA |
748 | }; |
749 | ||
750 | static struct clk clk_pcmcdclk0 = { | |
751 | .name = "pcm_cdclk0", | |
a443a637 TA |
752 | }; |
753 | ||
754 | static struct clk clk_pcmcdclk1 = { | |
755 | .name = "pcm_cdclk1", | |
a443a637 TA |
756 | }; |
757 | ||
758 | static struct clk *clk_src_group1_list[] = { | |
759 | [0] = &clk_mout_epll.clk, | |
760 | [1] = &clk_div_mpll2.clk, | |
761 | [2] = &clk_fin_epll, | |
762 | [3] = &clk_mout_hpll.clk, | |
763 | }; | |
764 | ||
ad016770 | 765 | static struct clksrc_sources clk_src_group1 = { |
a443a637 TA |
766 | .sources = clk_src_group1_list, |
767 | .nr_sources = ARRAY_SIZE(clk_src_group1_list), | |
768 | }; | |
769 | ||
770 | static struct clk *clk_src_group2_list[] = { | |
771 | [0] = &clk_mout_epll.clk, | |
772 | [1] = &clk_div_mpll.clk, | |
773 | }; | |
774 | ||
ad016770 | 775 | static struct clksrc_sources clk_src_group2 = { |
a443a637 TA |
776 | .sources = clk_src_group2_list, |
777 | .nr_sources = ARRAY_SIZE(clk_src_group2_list), | |
778 | }; | |
779 | ||
780 | static struct clk *clk_src_group3_list[] = { | |
781 | [0] = &clk_mout_epll.clk, | |
782 | [1] = &clk_div_mpll.clk, | |
783 | [2] = &clk_fin_epll, | |
784 | [3] = &clk_i2scdclk0, | |
785 | [4] = &clk_pcmcdclk0, | |
786 | [5] = &clk_mout_hpll.clk, | |
787 | }; | |
788 | ||
ad016770 | 789 | static struct clksrc_sources clk_src_group3 = { |
a443a637 TA |
790 | .sources = clk_src_group3_list, |
791 | .nr_sources = ARRAY_SIZE(clk_src_group3_list), | |
792 | }; | |
793 | ||
4cfd9c25 SY |
794 | static struct clksrc_clk clk_sclk_audio0 = { |
795 | .clk = { | |
796 | .name = "sclk_audio", | |
29e8eb0f | 797 | .devname = "samsung-pcm.0", |
4cfd9c25 SY |
798 | .ctrlbit = (1 << 8), |
799 | .enable = s5pc100_sclk1_ctrl, | |
800 | }, | |
801 | .sources = &clk_src_group3, | |
802 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 }, | |
803 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, | |
804 | }; | |
805 | ||
a443a637 TA |
806 | static struct clk *clk_src_group4_list[] = { |
807 | [0] = &clk_mout_epll.clk, | |
808 | [1] = &clk_div_mpll.clk, | |
809 | [2] = &clk_fin_epll, | |
810 | [3] = &clk_i2scdclk1, | |
811 | [4] = &clk_pcmcdclk1, | |
812 | [5] = &clk_mout_hpll.clk, | |
813 | }; | |
814 | ||
ad016770 | 815 | static struct clksrc_sources clk_src_group4 = { |
a443a637 TA |
816 | .sources = clk_src_group4_list, |
817 | .nr_sources = ARRAY_SIZE(clk_src_group4_list), | |
818 | }; | |
819 | ||
4cfd9c25 SY |
820 | static struct clksrc_clk clk_sclk_audio1 = { |
821 | .clk = { | |
822 | .name = "sclk_audio", | |
29e8eb0f | 823 | .devname = "samsung-pcm.1", |
4cfd9c25 SY |
824 | .ctrlbit = (1 << 9), |
825 | .enable = s5pc100_sclk1_ctrl, | |
826 | }, | |
827 | .sources = &clk_src_group4, | |
828 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 }, | |
829 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, | |
830 | }; | |
831 | ||
a443a637 TA |
832 | static struct clk *clk_src_group5_list[] = { |
833 | [0] = &clk_mout_epll.clk, | |
834 | [1] = &clk_div_mpll.clk, | |
835 | [2] = &clk_fin_epll, | |
836 | [3] = &clk_i2scdclk2, | |
837 | [4] = &clk_mout_hpll.clk, | |
838 | }; | |
839 | ||
ad016770 | 840 | static struct clksrc_sources clk_src_group5 = { |
a443a637 TA |
841 | .sources = clk_src_group5_list, |
842 | .nr_sources = ARRAY_SIZE(clk_src_group5_list), | |
843 | }; | |
844 | ||
4cfd9c25 SY |
845 | static struct clksrc_clk clk_sclk_audio2 = { |
846 | .clk = { | |
847 | .name = "sclk_audio", | |
29e8eb0f | 848 | .devname = "samsung-pcm.2", |
4cfd9c25 SY |
849 | .ctrlbit = (1 << 10), |
850 | .enable = s5pc100_sclk1_ctrl, | |
851 | }, | |
852 | .sources = &clk_src_group5, | |
853 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 }, | |
854 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, | |
855 | }; | |
856 | ||
a443a637 TA |
857 | static struct clk *clk_src_group6_list[] = { |
858 | [0] = &s5p_clk_27m, | |
859 | [1] = &clk_vclk54m, | |
860 | [2] = &clk_div_hdmi.clk, | |
861 | }; | |
862 | ||
ad016770 | 863 | static struct clksrc_sources clk_src_group6 = { |
a443a637 TA |
864 | .sources = clk_src_group6_list, |
865 | .nr_sources = ARRAY_SIZE(clk_src_group6_list), | |
866 | }; | |
867 | ||
868 | static struct clk *clk_src_group7_list[] = { | |
869 | [0] = &clk_mout_epll.clk, | |
870 | [1] = &clk_div_mpll.clk, | |
871 | [2] = &clk_mout_hpll.clk, | |
872 | [3] = &clk_vclk54m, | |
873 | }; | |
874 | ||
ad016770 | 875 | static struct clksrc_sources clk_src_group7 = { |
a443a637 TA |
876 | .sources = clk_src_group7_list, |
877 | .nr_sources = ARRAY_SIZE(clk_src_group7_list), | |
878 | }; | |
879 | ||
880 | static struct clk *clk_src_mmc0_list[] = { | |
881 | [0] = &clk_mout_epll.clk, | |
882 | [1] = &clk_div_mpll.clk, | |
883 | [2] = &clk_fin_epll, | |
884 | }; | |
885 | ||
ad016770 | 886 | static struct clksrc_sources clk_src_mmc0 = { |
a443a637 TA |
887 | .sources = clk_src_mmc0_list, |
888 | .nr_sources = ARRAY_SIZE(clk_src_mmc0_list), | |
889 | }; | |
890 | ||
891 | static struct clk *clk_src_mmc12_list[] = { | |
892 | [0] = &clk_mout_epll.clk, | |
893 | [1] = &clk_div_mpll.clk, | |
894 | [2] = &clk_fin_epll, | |
895 | [3] = &clk_mout_hpll.clk, | |
896 | }; | |
897 | ||
ad016770 | 898 | static struct clksrc_sources clk_src_mmc12 = { |
a443a637 TA |
899 | .sources = clk_src_mmc12_list, |
900 | .nr_sources = ARRAY_SIZE(clk_src_mmc12_list), | |
901 | }; | |
902 | ||
903 | static struct clk *clk_src_irda_usb_list[] = { | |
904 | [0] = &clk_mout_epll.clk, | |
905 | [1] = &clk_div_mpll.clk, | |
906 | [2] = &clk_fin_epll, | |
907 | [3] = &clk_mout_hpll.clk, | |
908 | }; | |
909 | ||
ad016770 | 910 | static struct clksrc_sources clk_src_irda_usb = { |
a443a637 TA |
911 | .sources = clk_src_irda_usb_list, |
912 | .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list), | |
913 | }; | |
914 | ||
915 | static struct clk *clk_src_pwi_list[] = { | |
916 | [0] = &clk_fin_epll, | |
917 | [1] = &clk_mout_epll.clk, | |
918 | [2] = &clk_div_mpll.clk, | |
919 | }; | |
920 | ||
ad016770 | 921 | static struct clksrc_sources clk_src_pwi = { |
a443a637 TA |
922 | .sources = clk_src_pwi_list, |
923 | .nr_sources = ARRAY_SIZE(clk_src_pwi_list), | |
924 | }; | |
925 | ||
04a4fd0a SY |
926 | static struct clk *clk_sclk_spdif_list[] = { |
927 | [0] = &clk_sclk_audio0.clk, | |
928 | [1] = &clk_sclk_audio1.clk, | |
929 | [2] = &clk_sclk_audio2.clk, | |
930 | }; | |
931 | ||
ad016770 | 932 | static struct clksrc_sources clk_src_sclk_spdif = { |
04a4fd0a SY |
933 | .sources = clk_sclk_spdif_list, |
934 | .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list), | |
935 | }; | |
936 | ||
04a4fd0a SY |
937 | static struct clksrc_clk clk_sclk_spdif = { |
938 | .clk = { | |
939 | .name = "sclk_spdif", | |
04a4fd0a SY |
940 | .ctrlbit = (1 << 11), |
941 | .enable = s5pc100_sclk1_ctrl, | |
65f5eaa2 | 942 | .ops = &s5p_sclk_spdif_ops, |
04a4fd0a SY |
943 | }, |
944 | .sources = &clk_src_sclk_spdif, | |
945 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 }, | |
946 | }; | |
947 | ||
a443a637 TA |
948 | static struct clksrc_clk clksrcs[] = { |
949 | { | |
a443a637 TA |
950 | .clk = { |
951 | .name = "sclk_mixer", | |
a443a637 TA |
952 | .ctrlbit = (1 << 6), |
953 | .enable = s5pc100_sclk0_ctrl, | |
954 | ||
955 | }, | |
956 | .sources = &clk_src_group6, | |
957 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 }, | |
a443a637 TA |
958 | }, { |
959 | .clk = { | |
960 | .name = "sclk_lcd", | |
a443a637 TA |
961 | .ctrlbit = (1 << 0), |
962 | .enable = s5pc100_sclk1_ctrl, | |
963 | ||
964 | }, | |
965 | .sources = &clk_src_group7, | |
966 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 }, | |
967 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, | |
968 | }, { | |
969 | .clk = { | |
970 | .name = "sclk_fimc", | |
29e8eb0f | 971 | .devname = "s5p-fimc.0", |
a443a637 TA |
972 | .ctrlbit = (1 << 1), |
973 | .enable = s5pc100_sclk1_ctrl, | |
974 | ||
975 | }, | |
976 | .sources = &clk_src_group7, | |
977 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 }, | |
978 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 }, | |
979 | }, { | |
980 | .clk = { | |
981 | .name = "sclk_fimc", | |
29e8eb0f | 982 | .devname = "s5p-fimc.1", |
a443a637 TA |
983 | .ctrlbit = (1 << 2), |
984 | .enable = s5pc100_sclk1_ctrl, | |
985 | ||
986 | }, | |
987 | .sources = &clk_src_group7, | |
988 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 }, | |
989 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, | |
990 | }, { | |
991 | .clk = { | |
992 | .name = "sclk_fimc", | |
29e8eb0f | 993 | .devname = "s5p-fimc.2", |
a443a637 TA |
994 | .ctrlbit = (1 << 3), |
995 | .enable = s5pc100_sclk1_ctrl, | |
996 | ||
997 | }, | |
998 | .sources = &clk_src_group7, | |
999 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 }, | |
1000 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, | |
a443a637 TA |
1001 | }, { |
1002 | .clk = { | |
1003 | .name = "sclk_irda", | |
a443a637 TA |
1004 | .ctrlbit = (1 << 10), |
1005 | .enable = s5pc100_sclk0_ctrl, | |
1006 | ||
1007 | }, | |
1008 | .sources = &clk_src_irda_usb, | |
1009 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, | |
1010 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, | |
1011 | }, { | |
1012 | .clk = { | |
1013 | .name = "sclk_irda", | |
a443a637 TA |
1014 | .ctrlbit = (1 << 10), |
1015 | .enable = s5pc100_sclk0_ctrl, | |
1016 | ||
1017 | }, | |
1018 | .sources = &clk_src_mmc12, | |
1019 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 }, | |
1020 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 }, | |
1021 | }, { | |
1022 | .clk = { | |
1023 | .name = "sclk_pwi", | |
a443a637 TA |
1024 | .ctrlbit = (1 << 1), |
1025 | .enable = s5pc100_sclk0_ctrl, | |
1026 | ||
1027 | }, | |
1028 | .sources = &clk_src_pwi, | |
1029 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 }, | |
1030 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 }, | |
1031 | }, { | |
1032 | .clk = { | |
1033 | .name = "sclk_uhost", | |
a443a637 TA |
1034 | .ctrlbit = (1 << 11), |
1035 | .enable = s5pc100_sclk0_ctrl, | |
1036 | ||
1037 | }, | |
1038 | .sources = &clk_src_irda_usb, | |
1039 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 }, | |
1040 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 }, | |
1041 | }, | |
1042 | }; | |
1043 | ||
0cfb26e1 TA |
1044 | static struct clksrc_clk clk_sclk_uart = { |
1045 | .clk = { | |
1046 | .name = "uclk1", | |
1047 | .ctrlbit = (1 << 3), | |
1048 | .enable = s5pc100_sclk0_ctrl, | |
1049 | }, | |
1050 | .sources = &clk_src_group2, | |
1051 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, | |
1052 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, | |
1053 | }; | |
1054 | ||
a361d10a RS |
1055 | static struct clksrc_clk clk_sclk_mmc0 = { |
1056 | .clk = { | |
1057 | .name = "sclk_mmc", | |
1058 | .devname = "s3c-sdhci.0", | |
1059 | .ctrlbit = (1 << 12), | |
1060 | .enable = s5pc100_sclk1_ctrl, | |
1061 | }, | |
1062 | .sources = &clk_src_mmc0, | |
1063 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, | |
1064 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, | |
1065 | }; | |
1066 | ||
1067 | static struct clksrc_clk clk_sclk_mmc1 = { | |
1068 | .clk = { | |
1069 | .name = "sclk_mmc", | |
1070 | .devname = "s3c-sdhci.1", | |
1071 | .ctrlbit = (1 << 13), | |
1072 | .enable = s5pc100_sclk1_ctrl, | |
1073 | }, | |
1074 | .sources = &clk_src_mmc12, | |
1075 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, | |
1076 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, | |
1077 | }; | |
1078 | ||
1079 | static struct clksrc_clk clk_sclk_mmc2 = { | |
1080 | .clk = { | |
1081 | .name = "sclk_mmc", | |
1082 | .devname = "s3c-sdhci.2", | |
1083 | .ctrlbit = (1 << 14), | |
1084 | .enable = s5pc100_sclk1_ctrl, | |
1085 | }, | |
1086 | .sources = &clk_src_mmc12, | |
1087 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, | |
1088 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, | |
1089 | }; | |
1090 | ||
02717bb9 PV |
1091 | static struct clksrc_clk clk_sclk_spi0 = { |
1092 | .clk = { | |
1093 | .name = "sclk_spi", | |
a5238e36 | 1094 | .devname = "s5pc100-spi.0", |
02717bb9 PV |
1095 | .ctrlbit = (1 << 4), |
1096 | .enable = s5pc100_sclk0_ctrl, | |
1097 | }, | |
1098 | .sources = &clk_src_group1, | |
1099 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 }, | |
1100 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, | |
1101 | }; | |
1102 | ||
1103 | static struct clksrc_clk clk_sclk_spi1 = { | |
1104 | .clk = { | |
1105 | .name = "sclk_spi", | |
a5238e36 | 1106 | .devname = "s5pc100-spi.1", |
02717bb9 PV |
1107 | .ctrlbit = (1 << 5), |
1108 | .enable = s5pc100_sclk0_ctrl, | |
1109 | }, | |
1110 | .sources = &clk_src_group1, | |
1111 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 }, | |
1112 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, | |
1113 | }; | |
1114 | ||
1115 | static struct clksrc_clk clk_sclk_spi2 = { | |
1116 | .clk = { | |
1117 | .name = "sclk_spi", | |
a5238e36 | 1118 | .devname = "s5pc100-spi.2", |
02717bb9 PV |
1119 | .ctrlbit = (1 << 6), |
1120 | .enable = s5pc100_sclk0_ctrl, | |
1121 | }, | |
1122 | .sources = &clk_src_group1, | |
1123 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 }, | |
1124 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 }, | |
1125 | }; | |
1126 | ||
a443a637 TA |
1127 | /* Clock initialisation code */ |
1128 | static struct clksrc_clk *sysclks[] = { | |
1129 | &clk_mout_apll, | |
1130 | &clk_mout_epll, | |
1131 | &clk_mout_mpll, | |
1132 | &clk_mout_hpll, | |
1133 | &clk_mout_href, | |
1134 | &clk_mout_48m, | |
1135 | &clk_div_apll, | |
1136 | &clk_div_arm, | |
1137 | &clk_div_d0_bus, | |
1138 | &clk_div_pclkd0, | |
1139 | &clk_div_secss, | |
1140 | &clk_div_apll2, | |
1141 | &clk_mout_am, | |
1142 | &clk_div_d1_bus, | |
1143 | &clk_div_mpll2, | |
1144 | &clk_div_mpll, | |
1145 | &clk_mout_onenand, | |
1146 | &clk_div_onenand, | |
1147 | &clk_div_pclkd1, | |
1148 | &clk_div_cam, | |
1149 | &clk_div_hdmi, | |
4cfd9c25 SY |
1150 | &clk_sclk_audio0, |
1151 | &clk_sclk_audio1, | |
1152 | &clk_sclk_audio2, | |
04a4fd0a | 1153 | &clk_sclk_spdif, |
a443a637 TA |
1154 | }; |
1155 | ||
a361d10a RS |
1156 | static struct clk *clk_cdev[] = { |
1157 | &clk_hsmmc0, | |
1158 | &clk_hsmmc1, | |
1159 | &clk_hsmmc2, | |
02717bb9 PV |
1160 | &clk_48m_spi0, |
1161 | &clk_48m_spi1, | |
1162 | &clk_48m_spi2, | |
eaff82ed PV |
1163 | &clk_i2s0, |
1164 | &clk_i2s1, | |
1165 | &clk_i2s2, | |
a361d10a RS |
1166 | }; |
1167 | ||
0cfb26e1 TA |
1168 | static struct clksrc_clk *clksrc_cdev[] = { |
1169 | &clk_sclk_uart, | |
a361d10a RS |
1170 | &clk_sclk_mmc0, |
1171 | &clk_sclk_mmc1, | |
1172 | &clk_sclk_mmc2, | |
02717bb9 PV |
1173 | &clk_sclk_spi0, |
1174 | &clk_sclk_spi1, | |
1175 | &clk_sclk_spi2, | |
0cfb26e1 TA |
1176 | }; |
1177 | ||
a443a637 TA |
1178 | void __init_or_cpufreq s5pc100_setup_clocks(void) |
1179 | { | |
1180 | unsigned long xtal; | |
1181 | unsigned long arm; | |
1182 | unsigned long hclkd0; | |
1183 | unsigned long hclkd1; | |
1184 | unsigned long pclkd0; | |
1185 | unsigned long pclkd1; | |
1186 | unsigned long apll; | |
1187 | unsigned long mpll; | |
1188 | unsigned long epll; | |
1189 | unsigned long hpll; | |
1190 | unsigned int ptr; | |
1191 | ||
1192 | /* Set S5PC100 functions for clk_fout_epll */ | |
d4b34c6c | 1193 | clk_fout_epll.enable = s5p_epll_enable; |
a443a637 TA |
1194 | clk_fout_epll.ops = &s5pc100_epll_ops; |
1195 | ||
1196 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | |
1197 | ||
1198 | xtal = clk_get_rate(&clk_xtal); | |
1199 | ||
1200 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | |
1201 | ||
1202 | apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON)); | |
1203 | mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON)); | |
1204 | epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON)); | |
1205 | hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON)); | |
1206 | ||
1207 | printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n", | |
1208 | print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll)); | |
1209 | ||
1210 | clk_fout_apll.rate = apll; | |
1211 | clk_fout_mpll.rate = mpll; | |
1212 | clk_fout_epll.rate = epll; | |
1213 | clk_mout_hpll.clk.rate = hpll; | |
1214 | ||
1215 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | |
1216 | s3c_set_clksrc(&clksrcs[ptr], true); | |
1217 | ||
1218 | arm = clk_get_rate(&clk_div_arm.clk); | |
1219 | hclkd0 = clk_get_rate(&clk_div_d0_bus.clk); | |
1220 | pclkd0 = clk_get_rate(&clk_div_pclkd0.clk); | |
1221 | hclkd1 = clk_get_rate(&clk_div_d1_bus.clk); | |
1222 | pclkd1 = clk_get_rate(&clk_div_pclkd1.clk); | |
1223 | ||
1224 | printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n", | |
1225 | print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1)); | |
1226 | ||
1227 | clk_f.rate = arm; | |
1228 | clk_h.rate = hclkd1; | |
1229 | clk_p.rate = pclkd1; | |
1230 | } | |
1231 | ||
1232 | /* | |
1233 | * The following clocks will be enabled during clock initialization. | |
1234 | */ | |
1235 | static struct clk init_clocks[] = { | |
1236 | { | |
1237 | .name = "tzic", | |
a443a637 TA |
1238 | .parent = &clk_div_d0_bus.clk, |
1239 | .enable = s5pc100_d0_0_ctrl, | |
1240 | .ctrlbit = (1 << 1), | |
1241 | }, { | |
1242 | .name = "intc", | |
a443a637 TA |
1243 | .parent = &clk_div_d0_bus.clk, |
1244 | .enable = s5pc100_d0_0_ctrl, | |
1245 | .ctrlbit = (1 << 0), | |
1246 | }, { | |
1247 | .name = "ebi", | |
a443a637 TA |
1248 | .parent = &clk_div_d0_bus.clk, |
1249 | .enable = s5pc100_d0_1_ctrl, | |
1250 | .ctrlbit = (1 << 5), | |
1251 | }, { | |
1252 | .name = "intmem", | |
a443a637 TA |
1253 | .parent = &clk_div_d0_bus.clk, |
1254 | .enable = s5pc100_d0_1_ctrl, | |
1255 | .ctrlbit = (1 << 4), | |
1256 | }, { | |
1257 | .name = "sromc", | |
a443a637 TA |
1258 | .parent = &clk_div_d0_bus.clk, |
1259 | .enable = s5pc100_d0_1_ctrl, | |
1260 | .ctrlbit = (1 << 1), | |
1261 | }, { | |
1262 | .name = "dmc", | |
a443a637 TA |
1263 | .parent = &clk_div_d0_bus.clk, |
1264 | .enable = s5pc100_d0_1_ctrl, | |
1265 | .ctrlbit = (1 << 0), | |
1266 | }, { | |
1267 | .name = "chipid", | |
a443a637 TA |
1268 | .parent = &clk_div_d0_bus.clk, |
1269 | .enable = s5pc100_d0_1_ctrl, | |
1270 | .ctrlbit = (1 << 0), | |
1271 | }, { | |
1272 | .name = "gpio", | |
a443a637 TA |
1273 | .parent = &clk_div_d1_bus.clk, |
1274 | .enable = s5pc100_d1_3_ctrl, | |
1275 | .ctrlbit = (1 << 1), | |
1276 | }, { | |
1277 | .name = "uart", | |
29e8eb0f | 1278 | .devname = "s3c6400-uart.0", |
a443a637 TA |
1279 | .parent = &clk_div_d1_bus.clk, |
1280 | .enable = s5pc100_d1_4_ctrl, | |
1281 | .ctrlbit = (1 << 0), | |
1282 | }, { | |
1283 | .name = "uart", | |
29e8eb0f | 1284 | .devname = "s3c6400-uart.1", |
a443a637 TA |
1285 | .parent = &clk_div_d1_bus.clk, |
1286 | .enable = s5pc100_d1_4_ctrl, | |
1287 | .ctrlbit = (1 << 1), | |
1288 | }, { | |
1289 | .name = "uart", | |
29e8eb0f | 1290 | .devname = "s3c6400-uart.2", |
a443a637 TA |
1291 | .parent = &clk_div_d1_bus.clk, |
1292 | .enable = s5pc100_d1_4_ctrl, | |
1293 | .ctrlbit = (1 << 2), | |
1294 | }, { | |
1295 | .name = "uart", | |
29e8eb0f | 1296 | .devname = "s3c6400-uart.3", |
a443a637 TA |
1297 | .parent = &clk_div_d1_bus.clk, |
1298 | .enable = s5pc100_d1_4_ctrl, | |
1299 | .ctrlbit = (1 << 3), | |
1300 | }, { | |
1301 | .name = "timers", | |
a443a637 TA |
1302 | .parent = &clk_div_d1_bus.clk, |
1303 | .enable = s5pc100_d1_3_ctrl, | |
1304 | .ctrlbit = (1 << 6), | |
1305 | }, | |
1306 | }; | |
1307 | ||
1308 | static struct clk *clks[] __initdata = { | |
1309 | &clk_ext, | |
1310 | &clk_i2scdclk0, | |
1311 | &clk_i2scdclk1, | |
1312 | &clk_i2scdclk2, | |
1313 | &clk_pcmcdclk0, | |
1314 | &clk_pcmcdclk1, | |
1315 | }; | |
1316 | ||
0cfb26e1 TA |
1317 | static struct clk_lookup s5pc100_clk_lookup[] = { |
1318 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), | |
1319 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk), | |
a361d10a RS |
1320 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), |
1321 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), | |
1322 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), | |
1323 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), | |
1324 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), | |
1325 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), | |
02717bb9 | 1326 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), |
a5238e36 TA |
1327 | CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0), |
1328 | CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), | |
1329 | CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1), | |
1330 | CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), | |
1331 | CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2), | |
1332 | CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), | |
eaff82ed PV |
1333 | CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0), |
1334 | CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1), | |
1335 | CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2), | |
0cfb26e1 TA |
1336 | }; |
1337 | ||
a443a637 TA |
1338 | void __init s5pc100_register_clocks(void) |
1339 | { | |
a443a637 TA |
1340 | int ptr; |
1341 | ||
1342 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | |
1343 | ||
1344 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | |
1345 | s3c_register_clksrc(sysclks[ptr], 1); | |
1346 | ||
1347 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | |
1348 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | |
0cfb26e1 TA |
1349 | for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) |
1350 | s3c_register_clksrc(clksrc_cdev[ptr], 1); | |
a443a637 | 1351 | |
96ee39c4 KK |
1352 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
1353 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | |
0cfb26e1 | 1354 | clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup)); |
a443a637 | 1355 | |
a361d10a RS |
1356 | s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); |
1357 | for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) | |
1358 | s3c_disable_clocks(clk_cdev[ptr], 1); | |
1359 | ||
a422bd0f | 1360 | s3c24xx_register_clock(&dummy_apb_pclk); |
a443a637 | 1361 | } |