Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / arch / arm / mach-s5pc100 / common.c
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1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
19a2c065 3 * http://www.samsung.com
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4 *
5 * Copyright 2009 Samsung Electronics Co.
6 * Byungho Min <bhmin@samsung.com>
7 *
dd4153d9 8 * Common Codes for S5PC100
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9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
dd4153d9 13 */
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14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/clk.h>
22#include <linux/io.h>
4a858cfc 23#include <linux/device.h>
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24#include <linux/serial_core.h>
25#include <linux/platform_device.h>
4341f9b3 26#include <linux/sched.h>
8acd1ade 27
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28#include <asm/irq.h>
29#include <asm/proc-fns.h>
9f97da78 30#include <asm/system_misc.h>
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31#include <asm/mach/arch.h>
32#include <asm/mach/map.h>
33#include <asm/mach/irq.h>
34
8acd1ade 35#include <mach/map.h>
dd4153d9 36#include <mach/hardware.h>
acc84707 37#include <mach/regs-clock.h>
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38
39#include <plat/cpu.h>
40#include <plat/devs.h>
41#include <plat/clock.h>
acc84707 42#include <plat/sdhci.h>
327b9030 43#include <plat/adc-core.h>
dd4153d9 44#include <plat/ata-core.h>
eb42b044 45#include <plat/fb-core.h>
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46#include <plat/iic-core.h>
47#include <plat/onenand-core.h>
308b3afb 48#include <plat/spi-core.h>
dd4153d9 49#include <plat/regs-serial.h>
5497d2e1 50#include <plat/watchdog-reset.h>
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51
52#include "common.h"
999304be 53
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54static const char name_s5pc100[] = "S5PC100";
55
56static struct cpu_table cpu_ids[] __initdata = {
57 {
58 .idcode = S5PC100_CPU_ID,
59 .idmask = S5PC100_CPU_MASK,
60 .map_io = s5pc100_map_io,
61 .init_clocks = s5pc100_init_clocks,
62 .init_uarts = s5pc100_init_uarts,
63 .init = s5pc100_init,
64 .name = name_s5pc100,
65 },
66};
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67
68/* Initial IO mappings */
69
70static struct map_desc s5pc100_iodesc[] __initdata = {
acc84707 71 {
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72 .virtual = (unsigned long)S5P_VA_CHIPID,
73 .pfn = __phys_to_pfn(S5PC100_PA_CHIPID),
74 .length = SZ_4K,
75 .type = MT_DEVICE,
76 }, {
77 .virtual = (unsigned long)S3C_VA_SYS,
78 .pfn = __phys_to_pfn(S5PC100_PA_SYSCON),
79 .length = SZ_64K,
80 .type = MT_DEVICE,
81 }, {
82 .virtual = (unsigned long)S3C_VA_TIMER,
83 .pfn = __phys_to_pfn(S5PC100_PA_TIMER),
84 .length = SZ_16K,
85 .type = MT_DEVICE,
86 }, {
87 .virtual = (unsigned long)S3C_VA_WATCHDOG,
88 .pfn = __phys_to_pfn(S5PC100_PA_WATCHDOG),
89 .length = SZ_4K,
90 .type = MT_DEVICE,
91 }, {
92 .virtual = (unsigned long)S5P_VA_SROMC,
93 .pfn = __phys_to_pfn(S5PC100_PA_SROMC),
94 .length = SZ_4K,
95 .type = MT_DEVICE,
96 }, {
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97 .virtual = (unsigned long)S5P_VA_SYSTIMER,
98 .pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER),
99 .length = SZ_16K,
100 .type = MT_DEVICE,
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101 }, {
102 .virtual = (unsigned long)S5P_VA_GPIO,
103 .pfn = __phys_to_pfn(S5PC100_PA_GPIO),
104 .length = SZ_4K,
105 .type = MT_DEVICE,
106 }, {
107 .virtual = (unsigned long)VA_VIC0,
108 .pfn = __phys_to_pfn(S5PC100_PA_VIC0),
109 .length = SZ_16K,
110 .type = MT_DEVICE,
111 }, {
112 .virtual = (unsigned long)VA_VIC1,
113 .pfn = __phys_to_pfn(S5PC100_PA_VIC1),
114 .length = SZ_16K,
115 .type = MT_DEVICE,
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116 }, {
117 .virtual = (unsigned long)VA_VIC2,
19a2c065 118 .pfn = __phys_to_pfn(S5PC100_PA_VIC2),
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119 .length = SZ_16K,
120 .type = MT_DEVICE,
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121 }, {
122 .virtual = (unsigned long)S3C_VA_UART,
123 .pfn = __phys_to_pfn(S3C_PA_UART),
124 .length = SZ_512K,
125 .type = MT_DEVICE,
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126 }, {
127 .virtual = (unsigned long)S5PC100_VA_OTHERS,
128 .pfn = __phys_to_pfn(S5PC100_PA_OTHERS),
129 .length = SZ_4K,
130 .type = MT_DEVICE,
131 }
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132};
133
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134/*
135 * s5pc100_map_io
8acd1ade 136 *
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137 * register the standard CPU IO areas
138 */
8acd1ade 139
dd4153d9 140void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
8acd1ade 141{
dd4153d9 142 /* initialize the io descriptors we need for initialization */
8acd1ade 143 iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
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144 if (mach_desc)
145 iotable_init(mach_desc, size);
146
147 /* detect cpu id and rev. */
148 s5p_init_cpu(S5P_VA_CHIPID);
149
150 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
151}
8acd1ade 152
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153void __init s5pc100_map_io(void)
154{
8acd1ade 155 /* initialise device information early */
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156 s5pc100_default_sdhci0();
157 s5pc100_default_sdhci1();
158 s5pc100_default_sdhci2();
5eda288f 159
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160 s3c_adc_setname("s3c64xx-adc");
161
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162 /* the i2c devices are directly compatible with s3c2440 */
163 s3c_i2c0_setname("s3c2440-i2c");
164 s3c_i2c1_setname("s3c2440-i2c");
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165
166 s3c_onenand_setname("s5pc100-onenand");
eb42b044 167 s3c_fb_setname("s5pc100-fb");
66194a74 168 s3c_cfcon_setname("s5pc100-pata");
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169
170 s3c64xx_spi_setname("s5pc100-spi");
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171}
172
173void __init s5pc100_init_clocks(int xtal)
174{
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175 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
176
8acd1ade 177 s3c24xx_register_baseclocks(xtal);
acc84707 178 s5p_register_clocks(xtal);
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179 s5pc100_register_clocks();
180 s5pc100_setup_clocks();
181}
182
183void __init s5pc100_init_irq(void)
184{
acc84707 185 u32 vic[] = {~0, ~0, ~0};
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186
187 /* VIC0, VIC1, and VIC2 are fully populated. */
acc84707 188 s5p_init_irq(vic, ARRAY_SIZE(vic));
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189}
190
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191static struct bus_type s5pc100_subsys = {
192 .name = "s5pc100-core",
193 .dev_name = "s5pc100-core",
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194};
195
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196static struct device s5pc100_dev = {
197 .bus = &s5pc100_subsys,
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198};
199
200static int __init s5pc100_core_init(void)
201{
4a858cfc 202 return subsys_system_register(&s5pc100_subsys, NULL);
8acd1ade 203}
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204core_initcall(s5pc100_core_init);
205
206int __init s5pc100_init(void)
207{
acc84707 208 printk(KERN_INFO "S5PC100: Initializing architecture\n");
ea04018e 209 return device_register(&s5pc100_dev);
8acd1ade 210}
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211
212/* uart registration process */
213
214void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
215{
216 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
217}
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218
219void s5pc100_restart(char mode, const char *cmd)
220{
221 if (mode != 's')
222 arch_wdt_reset();
223
224 soft_restart(0);
225}
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