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a422bd0f BK |
1 | /* linux/arch/arm/mach-s5pc100/dma.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
c5e2caca JB |
6 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. |
7 | * Jaswinder Singh <jassi.brar@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
c5e2caca | 24 | #include <linux/dma-mapping.h> |
a422bd0f BK |
25 | #include <linux/amba/bus.h> |
26 | #include <linux/amba/pl330.h> | |
c5e2caca | 27 | |
a422bd0f | 28 | #include <asm/irq.h> |
c5e2caca | 29 | #include <plat/devs.h> |
a422bd0f | 30 | #include <plat/irqs.h> |
c5e2caca JB |
31 | |
32 | #include <mach/map.h> | |
45c79433 | 33 | #include <mach/irqs.h> |
a422bd0f | 34 | #include <mach/dma.h> |
c5e2caca | 35 | |
ad016770 | 36 | static u8 pdma0_peri[] = { |
7c4cab7f TA |
37 | DMACH_UART0_RX, |
38 | DMACH_UART0_TX, | |
39 | DMACH_UART1_RX, | |
40 | DMACH_UART1_TX, | |
41 | DMACH_UART2_RX, | |
42 | DMACH_UART2_TX, | |
43 | DMACH_UART3_RX, | |
44 | DMACH_UART3_TX, | |
45 | DMACH_IRDA, | |
46 | DMACH_I2S0_RX, | |
47 | DMACH_I2S0_TX, | |
48 | DMACH_I2S0S_TX, | |
49 | DMACH_I2S1_RX, | |
50 | DMACH_I2S1_TX, | |
51 | DMACH_I2S2_RX, | |
52 | DMACH_I2S2_TX, | |
53 | DMACH_SPI0_RX, | |
54 | DMACH_SPI0_TX, | |
55 | DMACH_SPI1_RX, | |
56 | DMACH_SPI1_TX, | |
57 | DMACH_SPI2_RX, | |
58 | DMACH_SPI2_TX, | |
59 | DMACH_AC97_MICIN, | |
60 | DMACH_AC97_PCMIN, | |
61 | DMACH_AC97_PCMOUT, | |
62 | DMACH_EXTERNAL, | |
63 | DMACH_PWM, | |
64 | DMACH_SPDIF, | |
65 | DMACH_HSI_RX, | |
66 | DMACH_HSI_TX, | |
c5e2caca JB |
67 | }; |
68 | ||
ad016770 | 69 | static struct dma_pl330_platdata s5pc100_pdma0_pdata = { |
a422bd0f | 70 | .nr_valid_peri = ARRAY_SIZE(pdma0_peri), |
7c4cab7f | 71 | .peri_id = pdma0_peri, |
c5e2caca JB |
72 | }; |
73 | ||
60571f98 KK |
74 | static AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330, |
75 | S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata); | |
c5e2caca | 76 | |
ad016770 | 77 | static u8 pdma1_peri[] = { |
7c4cab7f TA |
78 | DMACH_UART0_RX, |
79 | DMACH_UART0_TX, | |
80 | DMACH_UART1_RX, | |
81 | DMACH_UART1_TX, | |
82 | DMACH_UART2_RX, | |
83 | DMACH_UART2_TX, | |
84 | DMACH_UART3_RX, | |
85 | DMACH_UART3_TX, | |
86 | DMACH_IRDA, | |
87 | DMACH_I2S0_RX, | |
88 | DMACH_I2S0_TX, | |
89 | DMACH_I2S0S_TX, | |
90 | DMACH_I2S1_RX, | |
91 | DMACH_I2S1_TX, | |
92 | DMACH_I2S2_RX, | |
93 | DMACH_I2S2_TX, | |
94 | DMACH_SPI0_RX, | |
95 | DMACH_SPI0_TX, | |
96 | DMACH_SPI1_RX, | |
97 | DMACH_SPI1_TX, | |
98 | DMACH_SPI2_RX, | |
99 | DMACH_SPI2_TX, | |
100 | DMACH_PCM0_RX, | |
101 | DMACH_PCM0_TX, | |
102 | DMACH_PCM1_RX, | |
103 | DMACH_PCM1_TX, | |
104 | DMACH_MSM_REQ0, | |
105 | DMACH_MSM_REQ1, | |
106 | DMACH_MSM_REQ2, | |
107 | DMACH_MSM_REQ3, | |
c5e2caca JB |
108 | }; |
109 | ||
ad016770 | 110 | static struct dma_pl330_platdata s5pc100_pdma1_pdata = { |
a422bd0f | 111 | .nr_valid_peri = ARRAY_SIZE(pdma1_peri), |
7c4cab7f | 112 | .peri_id = pdma1_peri, |
a422bd0f BK |
113 | }; |
114 | ||
60571f98 KK |
115 | static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330, |
116 | S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata); | |
c5e2caca JB |
117 | |
118 | static int __init s5pc100_dma_init(void) | |
119 | { | |
7c4cab7f TA |
120 | dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask); |
121 | dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask); | |
75c06963 | 122 | amba_device_register(&s5pc100_pdma0_device, &iomem_resource); |
7c4cab7f TA |
123 | |
124 | dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask); | |
125 | dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask); | |
75c06963 | 126 | amba_device_register(&s5pc100_pdma1_device, &iomem_resource); |
c5e2caca JB |
127 | |
128 | return 0; | |
129 | } | |
130 | arch_initcall(s5pc100_dma_init); |