[deliverable/linux.git] / arch / arm / mach-s5pv210 / clock.c

/* linux/arch/arm/mach-s5pv210/clock.c
 *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com/
 *
 * S5PV210 - Clock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/io.h>

#include <mach/map.h>

#include <plat/cpu-freq.h>
#include <mach/regs-clock.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/s5pv210.h>

static struct clksrc_clk clk_mout_apll = {
	.clk	= {
		.name		= "mout_apll",
		.id		= -1,
	},
	.sources	= &clk_src_apll,
	.reg_src	= { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
};

static struct clksrc_clk clk_mout_epll = {
	.clk	= {
		.name		= "mout_epll",
		.id		= -1,
	},
	.sources	= &clk_src_epll,
	.reg_src	= { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
};

static struct clksrc_clk clk_mout_mpll = {
	.clk = {
		.name		= "mout_mpll",
		.id		= -1,
	},
	.sources	= &clk_src_mpll,
	.reg_src	= { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
};

static struct clk *clkset_armclk_list[] = {
	[0] = &clk_mout_apll.clk,
	[1] = &clk_mout_mpll.clk,
};

static struct clksrc_sources clkset_armclk = {
	.sources	= clkset_armclk_list,
	.nr_sources	= ARRAY_SIZE(clkset_armclk_list),
};

static struct clksrc_clk clk_armclk = {
	.clk	= {
		.name		= "armclk",
		.id		= -1,
	},
	.sources	= &clkset_armclk,
	.reg_src	= { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
	.reg_div	= { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
};

static struct clksrc_clk clk_hclk_msys = {
	.clk	= {
		.name		= "hclk_msys",
		.id		= -1,
		.parent		= &clk_armclk.clk,
	},
	.reg_div	= { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
};

static struct clksrc_clk clk_pclk_msys = {
	.clk	= {
		.name		= "pclk_msys",
		.id		= -1,
		.parent		= &clk_hclk_msys.clk,
	},
	.reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
};

static struct clksrc_clk clk_sclk_a2m = {
	.clk	= {
		.name		= "sclk_a2m",
		.id		= -1,
		.parent		= &clk_mout_apll.clk,
	},
	.reg_div	= { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
};

static struct clk *clkset_hclk_sys_list[] = {
	[0] = &clk_mout_mpll.clk,
	[1] = &clk_sclk_a2m.clk,
};

static struct clksrc_sources clkset_hclk_sys = {
	.sources	= clkset_hclk_sys_list,
	.nr_sources	= ARRAY_SIZE(clkset_hclk_sys_list),
};

static struct clksrc_clk clk_hclk_dsys = {
	.clk	= {
		.name	= "hclk_dsys",
		.id	= -1,
	},
	.sources	= &clkset_hclk_sys,
	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
	.reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
};

static struct clksrc_clk clk_hclk_psys = {
	.clk	= {
		.name	= "hclk_psys",
		.id	= -1,
	},
	.sources	= &clkset_hclk_sys,
	.reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
	.reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
};

static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
}

static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
}

static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
}

static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
}

static struct clk clk_p83 = {
	.name		= "pclk83",
	.id		= -1,
};

static struct clk clk_p66 = {
	.name		= "pclk66",
	.id		= -1,
};

static struct clk *sys_clks[] = {
	&clk_p83,
	&clk_p66
};

static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
{
	return clk_get_rate(clk->parent) / 2;
}

static struct clk_ops clk_hclk_imem_ops = {
	.get_rate	= s5pv210_clk_imem_get_rate,
};

static struct clk init_clocks_disable[] = {
	{
		.name		= "rot",
		.id		= -1,
		.parent		= &clk_hclk_dsys.clk,
		.enable		= s5pv210_clk_ip0_ctrl,
		.ctrlbit	= (1<<29),
	}, {
		.name		= "otg",
		.id		= -1,
		.parent		= &clk_hclk_psys.clk,
		.enable		= s5pv210_clk_ip1_ctrl,
		.ctrlbit	= (1<<16),
	}, {
		.name		= "usb-host",
		.id		= -1,
		.parent		= &clk_hclk_psys.clk,
		.enable		= s5pv210_clk_ip1_ctrl,
		.ctrlbit	= (1<<17),
	}, {
		.name		= "lcd",
		.id		= -1,
		.parent		= &clk_hclk_dsys.clk,
		.enable		= s5pv210_clk_ip1_ctrl,
		.ctrlbit	= (1<<0),
	}, {
		.name		= "cfcon",
		.id		= 0,
		.parent		= &clk_hclk_psys.clk,
		.enable		= s5pv210_clk_ip1_ctrl,
		.ctrlbit	= (1<<25),
	}, {
		.name		= "hsmmc",
		.id		= 0,
		.parent		= &clk_hclk_psys.clk,
		.enable		= s5pv210_clk_ip2_ctrl,
		.ctrlbit	= (1<<16),
	}, {
		.name		= "hsmmc",
		.id		= 1,
		.parent		= &clk_hclk_psys.clk,
		.enable		= s5pv210_clk_ip2_ctrl,
		.ctrlbit	= (1<<17),
	}, {
		.name		= "hsmmc",
		.id		= 2,
		.parent		= &clk_hclk_psys.clk,
		.enable		= s5pv210_clk_ip2_ctrl,
		.ctrlbit	= (1<<18),
	}, {
		.name		= "hsmmc",
		.id		= 3,
		.parent		= &clk_hclk_psys.clk,
		.enable		= s5pv210_clk_ip2_ctrl,
		.ctrlbit	= (1<<19),
	}, {
		.name		= "systimer",
		.id		= -1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<16),
	}, {
		.name		= "watchdog",
		.id		= -1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<22),
	}, {
		.name		= "rtc",
		.id		= -1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<15),
	}, {
		.name		= "i2c",
		.id		= 0,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<7),
	}, {
		.name		= "i2c",
		.id		= 1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<8),
	}, {
		.name		= "i2c",
		.id		= 2,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<9),
	}, {
		.name		= "spi",
		.id		= 0,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<12),
	}, {
		.name		= "spi",
		.id		= 1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<13),
	}, {
		.name		= "spi",
		.id		= 2,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<14),
	}, {
		.name		= "timers",
		.id		= -1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<23),
	}, {
		.name		= "adc",
		.id		= -1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<24),
	}, {
		.name		= "keypad",
		.id		= -1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<21),
	}, {
		.name		= "i2s_v50",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<4),
	}, {
		.name		= "i2s_v32",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<4),
	}, {
		.name		= "i2s_v32",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<4),
	}
};

static struct clk init_clocks[] = {
	{
		.name		= "hclk_imem",
		.id		= -1,
		.parent		= &clk_hclk_msys.clk,
		.ctrlbit	= (1 << 5),
		.enable		= s5pv210_clk_ip0_ctrl,
		.ops		= &clk_hclk_imem_ops,
	}, {
		.name		= "uart",
		.id		= 0,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<7),
	}, {
		.name		= "uart",
		.id		= 1,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<8),
	}, {
		.name		= "uart",
		.id		= 2,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<9),
	}, {
		.name		= "uart",
		.id		= 3,
		.parent		= &clk_p66,
		.enable		= s5pv210_clk_ip3_ctrl,
		.ctrlbit	= (1<<10),
	},
};

static struct clk *clkset_uart_list[] = {
	[6] = &clk_mout_mpll.clk,
	[7] = &clk_mout_epll.clk,
};

static struct clksrc_sources clkset_uart = {
	.sources	= clkset_uart_list,
	.nr_sources	= ARRAY_SIZE(clkset_uart_list),
};

static struct clksrc_clk clksrcs[] = {
	{
		.clk	= {
			.name		= "uclk1",
			.id		= -1,
			.ctrlbit	= (1<<17),
			.enable		= s5pv210_clk_ip3_ctrl,
		},
		.sources = &clkset_uart,
		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
		.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
	}
};

/* Clock initialisation code */
static struct clksrc_clk *sysclks[] = {
	&clk_mout_apll,
	&clk_mout_epll,
	&clk_mout_mpll,
	&clk_armclk,
	&clk_hclk_msys,
	&clk_sclk_a2m,
	&clk_hclk_dsys,
	&clk_hclk_psys,
	&clk_pclk_msys,
};

#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)

void __init_or_cpufreq s5pv210_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long xtal;
	unsigned long armclk;
	unsigned long hclk_msys;
	unsigned long hclk_dsys;
	unsigned long hclk_psys;
	unsigned long pclk_msys;
	unsigned long pclk83;
	unsigned long pclk66;
	unsigned long apll;
	unsigned long mpll;
	unsigned long epll;
	unsigned int ptr;
	u32 clkdiv0, clkdiv1;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	clkdiv0 = __raw_readl(S5P_CLK_DIV0);
	clkdiv1 = __raw_readl(S5P_CLK_DIV1);

	printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
				__func__, clkdiv0, clkdiv1);

	xtal_clk = clk_get(NULL, "xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
	epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);

	clk_fout_apll.rate = apll;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;

	printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
			apll, mpll, epll);

	armclk = clk_get_rate(&clk_armclk.clk);
	hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
	hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
	hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
	pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
	pclk83 = hclk_dsys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
	pclk66 = hclk_psys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);

	printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
			 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
			armclk, hclk_msys, hclk_dsys, hclk_psys,
			pclk_msys, pclk83, pclk66);

	clk_f.rate = armclk;
	clk_h.rate = hclk_psys;
	clk_p.rate = pclk66;
	clk_p66.rate = pclk66;
	clk_p83.rate = pclk83;

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}

static struct clk *clks[] __initdata = {
};

void __init s5pv210_register_clocks(void)
{
	struct clk *clkp;
	int ret;
	int ptr;

	ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
	if (ret > 0)
		printk(KERN_ERR "Failed to register %u clocks\n", ret);

	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
		s3c_register_clksrc(sysclks[ptr], 1);

	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));

	ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
	if (ret > 0)
		printk(KERN_ERR "Failed to register system clocks\n");

	clkp = init_clocks_disable;
	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
		ret = s3c24xx_register_clock(clkp);
		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       clkp->name, ret);
		}
		(clkp->enable)(clkp, 0);
	}

	s3c_pwmclk_init();
}
Commit	Line	Data
0c1945d3 KK	1	/* linux/arch/arm/mach-s5pv210/clock.c
	2	*
	3	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com/
	5	*
	6	* S5PV210 - Clock support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/list.h>
	17	#include <linux/errno.h>
	18	#include <linux/err.h>
	19	#include <linux/clk.h>
	20	#include <linux/sysdev.h>
	21	#include <linux/io.h>
	22
	23	#include <mach/map.h>
	24
	25	#include <plat/cpu-freq.h>
	26	#include <mach/regs-clock.h>
	27	#include <plat/clock.h>
	28	#include <plat/cpu.h>
	29	#include <plat/pll.h>
	30	#include <plat/s5p-clock.h>
	31	#include <plat/clock-clksrc.h>
	32	#include <plat/s5pv210.h>
	33
59cda520 TA	34	static struct clksrc_clk clk_mout_apll = {
	35	.clk = {
	36	.name = "mout_apll",
	37	.id = -1,
	38	},
	39	.sources = &clk_src_apll,
	40	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
	41	};
	42
	43	static struct clksrc_clk clk_mout_epll = {
	44	.clk = {
	45	.name = "mout_epll",
	46	.id = -1,
	47	},
	48	.sources = &clk_src_epll,
	49	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
	50	};
	51
	52	static struct clksrc_clk clk_mout_mpll = {
	53	.clk = {
	54	.name = "mout_mpll",
	55	.id = -1,
	56	},
	57	.sources = &clk_src_mpll,
	58	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
	59	};
	60
374e0bf5 TA	61	static struct clk *clkset_armclk_list[] = {
	62	[0] = &clk_mout_apll.clk,
	63	[1] = &clk_mout_mpll.clk,
	64	};
	65
	66	static struct clksrc_sources clkset_armclk = {
	67	.sources = clkset_armclk_list,
	68	.nr_sources = ARRAY_SIZE(clkset_armclk_list),
	69	};
	70
	71	static struct clksrc_clk clk_armclk = {
	72	.clk = {
	73	.name = "armclk",
	74	.id = -1,
	75	},
	76	.sources = &clkset_armclk,
	77	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
	78	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
	79	};
	80
af76a201 TA	81	static struct clksrc_clk clk_hclk_msys = {
	82	.clk = {
	83	.name = "hclk_msys",
	84	.id = -1,
	85	.parent = &clk_armclk.clk,
	86	},
	87	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
	88	};
	89
6ed91a20 TA	90	static struct clksrc_clk clk_pclk_msys = {
	91	.clk = {
	92	.name = "pclk_msys",
	93	.id = -1,
	94	.parent = &clk_hclk_msys.clk,
	95	},
	96	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
	97	};
	98
0fe967a1 TA	99	static struct clksrc_clk clk_sclk_a2m = {
	100	.clk = {
	101	.name = "sclk_a2m",
	102	.id = -1,
	103	.parent = &clk_mout_apll.clk,
	104	},
	105	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
	106	};
	107
	108	static struct clk *clkset_hclk_sys_list[] = {
	109	[0] = &clk_mout_mpll.clk,
	110	[1] = &clk_sclk_a2m.clk,
	111	};
	112
	113	static struct clksrc_sources clkset_hclk_sys = {
	114	.sources = clkset_hclk_sys_list,
	115	.nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
	116	};
	117
	118	static struct clksrc_clk clk_hclk_dsys = {
	119	.clk = {
	120	.name = "hclk_dsys",
	121	.id = -1,
	122	},
	123	.sources = &clkset_hclk_sys,
	124	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
	125	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
	126	};
	127
acfa245f TA	128	static struct clksrc_clk clk_hclk_psys = {
	129	.clk = {
	130	.name = "hclk_psys",
	131	.id = -1,
	132	},
	133	.sources = &clkset_hclk_sys,
	134	.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
	135	.reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
	136	};
	137
0c1945d3 KK	138	static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
	139	{
	140	return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
	141	}
	142
	143	static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
	144	{
	145	return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
	146	}
	147
	148	static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
	149	{
	150	return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
	151	}
	152
	153	static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
	154	{
	155	return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
	156	}
	157
0c1945d3 KK	158	static struct clk clk_p83 = {
	159	.name = "pclk83",
	160	.id = -1,
	161	};
	162
	163	static struct clk clk_p66 = {
	164	.name = "pclk66",
	165	.id = -1,
	166	};
	167
	168	static struct clk *sys_clks[] = {
0c1945d3 KK	169	&clk_p83,
	170	&clk_p66
	171	};
	172
664f5b20 TA	173	static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
	174	{
	175	return clk_get_rate(clk->parent) / 2;
	176	}
	177
	178	static struct clk_ops clk_hclk_imem_ops = {
	179	.get_rate = s5pv210_clk_imem_get_rate,
	180	};
	181
0c1945d3 KK	182	static struct clk init_clocks_disable[] = {
	183	{
	184	.name = "rot",
	185	.id = -1,
0fe967a1	186	.parent = &clk_hclk_dsys.clk,
0c1945d3 KK	187	.enable = s5pv210_clk_ip0_ctrl,
	188	.ctrlbit = (1<<29),
	189	}, {
	190	.name = "otg",
	191	.id = -1,
acfa245f	192	.parent = &clk_hclk_psys.clk,
0c1945d3 KK	193	.enable = s5pv210_clk_ip1_ctrl,
	194	.ctrlbit = (1<<16),
	195	}, {
	196	.name = "usb-host",
	197	.id = -1,
acfa245f	198	.parent = &clk_hclk_psys.clk,
0c1945d3 KK	199	.enable = s5pv210_clk_ip1_ctrl,
	200	.ctrlbit = (1<<17),
	201	}, {
	202	.name = "lcd",
	203	.id = -1,
0fe967a1	204	.parent = &clk_hclk_dsys.clk,
0c1945d3 KK	205	.enable = s5pv210_clk_ip1_ctrl,
	206	.ctrlbit = (1<<0),
	207	}, {
	208	.name = "cfcon",
	209	.id = 0,
acfa245f	210	.parent = &clk_hclk_psys.clk,
0c1945d3 KK	211	.enable = s5pv210_clk_ip1_ctrl,
	212	.ctrlbit = (1<<25),
	213	}, {
	214	.name = "hsmmc",
	215	.id = 0,
acfa245f	216	.parent = &clk_hclk_psys.clk,
0c1945d3 KK	217	.enable = s5pv210_clk_ip2_ctrl,
	218	.ctrlbit = (1<<16),
	219	}, {
	220	.name = "hsmmc",
	221	.id = 1,
acfa245f	222	.parent = &clk_hclk_psys.clk,
0c1945d3 KK	223	.enable = s5pv210_clk_ip2_ctrl,
	224	.ctrlbit = (1<<17),
	225	}, {
	226	.name = "hsmmc",
	227	.id = 2,
acfa245f	228	.parent = &clk_hclk_psys.clk,
0c1945d3 KK	229	.enable = s5pv210_clk_ip2_ctrl,
	230	.ctrlbit = (1<<18),
	231	}, {
	232	.name = "hsmmc",
	233	.id = 3,
acfa245f	234	.parent = &clk_hclk_psys.clk,
0c1945d3 KK	235	.enable = s5pv210_clk_ip2_ctrl,
	236	.ctrlbit = (1<<19),
	237	}, {
	238	.name = "systimer",
	239	.id = -1,
	240	.parent = &clk_p66,
	241	.enable = s5pv210_clk_ip3_ctrl,
	242	.ctrlbit = (1<<16),
	243	}, {
	244	.name = "watchdog",
	245	.id = -1,
	246	.parent = &clk_p66,
	247	.enable = s5pv210_clk_ip3_ctrl,
	248	.ctrlbit = (1<<22),
	249	}, {
	250	.name = "rtc",
	251	.id = -1,
	252	.parent = &clk_p66,
	253	.enable = s5pv210_clk_ip3_ctrl,
	254	.ctrlbit = (1<<15),
	255	}, {
	256	.name = "i2c",
	257	.id = 0,
	258	.parent = &clk_p66,
	259	.enable = s5pv210_clk_ip3_ctrl,
	260	.ctrlbit = (1<<7),
	261	}, {
	262	.name = "i2c",
	263	.id = 1,
	264	.parent = &clk_p66,
	265	.enable = s5pv210_clk_ip3_ctrl,
	266	.ctrlbit = (1<<8),
	267	}, {
	268	.name = "i2c",
	269	.id = 2,
	270	.parent = &clk_p66,
	271	.enable = s5pv210_clk_ip3_ctrl,
	272	.ctrlbit = (1<<9),
	273	}, {
	274	.name = "spi",
	275	.id = 0,
	276	.parent = &clk_p66,
	277	.enable = s5pv210_clk_ip3_ctrl,
	278	.ctrlbit = (1<<12),
	279	}, {
	280	.name = "spi",
	281	.id = 1,
	282	.parent = &clk_p66,
	283	.enable = s5pv210_clk_ip3_ctrl,
	284	.ctrlbit = (1<<13),
	285	}, {
	286	.name = "spi",
	287	.id = 2,
	288	.parent = &clk_p66,
	289	.enable = s5pv210_clk_ip3_ctrl,
	290	.ctrlbit = (1<<14),
	291	}, {
	292	.name = "timers",
	293	.id = -1,
	294	.parent = &clk_p66,
	295	.enable = s5pv210_clk_ip3_ctrl,
	296	.ctrlbit = (1<<23),
	297	}, {
	298	.name = "adc",
299	.id = -1,
300	.parent = &clk_p66,
301	.enable = s5pv210_clk_ip3_ctrl,
302	.ctrlbit = (1<<24),
303	}, {
304	.name = "keypad",
305	.id = -1,
306	.parent = &clk_p66,
307	.enable = s5pv210_clk_ip3_ctrl,
308	.ctrlbit = (1<<21),
309	}, {
310	.name = "i2s_v50",
311	.id = 0,
312	.parent = &clk_p,
313	.enable = s5pv210_clk_ip3_ctrl,
314	.ctrlbit = (1<<4),
315	}, {
316	.name = "i2s_v32",
317	.id = 0,
318	.parent = &clk_p,
319	.enable = s5pv210_clk_ip3_ctrl,
320	.ctrlbit = (1<<4),
321	}, {
322	.name = "i2s_v32",
323	.id = 1,
324	.parent = &clk_p,
325	.enable = s5pv210_clk_ip3_ctrl,
326	.ctrlbit = (1<<4),
327	}
328	};
329
330	static struct clk init_clocks[] = {
331	{
664f5b20 TA	332	.name = "hclk_imem",
	333	.id = -1,
	334	.parent = &clk_hclk_msys.clk,
	335	.ctrlbit = (1 << 5),
	336	.enable = s5pv210_clk_ip0_ctrl,
	337	.ops = &clk_hclk_imem_ops,
	338	}, {
0c1945d3 KK	339	.name = "uart",
	340	.id = 0,
	341	.parent = &clk_p66,
	342	.enable = s5pv210_clk_ip3_ctrl,
	343	.ctrlbit = (1<<7),
	344	}, {
	345	.name = "uart",
	346	.id = 1,
	347	.parent = &clk_p66,
	348	.enable = s5pv210_clk_ip3_ctrl,
	349	.ctrlbit = (1<<8),
	350	}, {
	351	.name = "uart",
	352	.id = 2,
	353	.parent = &clk_p66,
	354	.enable = s5pv210_clk_ip3_ctrl,
	355	.ctrlbit = (1<<9),
	356	}, {
	357	.name = "uart",
	358	.id = 3,
	359	.parent = &clk_p66,
	360	.enable = s5pv210_clk_ip3_ctrl,
	361	.ctrlbit = (1<<10),
	362	},
	363	};
	364
0c1945d3 KK	365	static struct clk *clkset_uart_list[] = {
	366	[6] = &clk_mout_mpll.clk,
	367	[7] = &clk_mout_epll.clk,
	368	};
	369
	370	static struct clksrc_sources clkset_uart = {
	371	.sources = clkset_uart_list,
	372	.nr_sources = ARRAY_SIZE(clkset_uart_list),
	373	};
	374
	375	static struct clksrc_clk clksrcs[] = {
	376	{
	377	.clk = {
	378	.name = "uclk1",
	379	.id = -1,
	380	.ctrlbit = (1<<17),
	381	.enable = s5pv210_clk_ip3_ctrl,
	382	},
	383	.sources = &clkset_uart,
	384	.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
	385	.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
	386	}
	387	};
	388
	389	/* Clock initialisation code */
eb1ef1ed	390	static struct clksrc_clk *sysclks[] = {
0c1945d3 KK	391	&clk_mout_apll,
	392	&clk_mout_epll,
	393	&clk_mout_mpll,
374e0bf5	394	&clk_armclk,
af76a201	395	&clk_hclk_msys,
0fe967a1 TA	396	&clk_sclk_a2m,
0fe967a1 TA	397	&clk_hclk_dsys,
acfa245f	398	&clk_hclk_psys,
6ed91a20	399	&clk_pclk_msys,
0c1945d3 KK	400	};
	401
	402	#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
	403
	404	void __init_or_cpufreq s5pv210_setup_clocks(void)
	405	{
	406	struct clk *xtal_clk;
	407	unsigned long xtal;
	408	unsigned long armclk;
af76a201	409	unsigned long hclk_msys;
0fe967a1	410	unsigned long hclk_dsys;
acfa245f	411	unsigned long hclk_psys;
6ed91a20	412	unsigned long pclk_msys;
0c1945d3 KK	413	unsigned long pclk83;
	414	unsigned long pclk66;
	415	unsigned long apll;
	416	unsigned long mpll;
	417	unsigned long epll;
	418	unsigned int ptr;
	419	u32 clkdiv0, clkdiv1;
	420
	421	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
	422
	423	clkdiv0 = __raw_readl(S5P_CLK_DIV0);
	424	clkdiv1 = __raw_readl(S5P_CLK_DIV1);
	425
	426	printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
	427	__func__, clkdiv0, clkdiv1);
	428
	429	xtal_clk = clk_get(NULL, "xtal");
	430	BUG_ON(IS_ERR(xtal_clk));
	431
	432	xtal = clk_get_rate(xtal_clk);
	433	clk_put(xtal_clk);
	434
	435	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
	436
	437	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
	438	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
	439	epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
	440
c62ec6a9 TA	441	clk_fout_apll.rate = apll;
	442	clk_fout_mpll.rate = mpll;
	443	clk_fout_epll.rate = epll;
	444
0c1945d3 KK	445	printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
	446	apll, mpll, epll);
	447
374e0bf5	448	armclk = clk_get_rate(&clk_armclk.clk);
af76a201	449	hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
0fe967a1	450	hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
acfa245f	451	hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
6ed91a20	452	pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
0fe967a1	453	pclk83 = hclk_dsys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
acfa245f	454	pclk66 = hclk_psys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
0c1945d3	455
acfa245f TA	456	printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
	457	"HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
	458	armclk, hclk_msys, hclk_dsys, hclk_psys,
6ed91a20	459	pclk_msys, pclk83, pclk66);
0c1945d3	460
0c1945d3	461	clk_f.rate = armclk;
acfa245f	462	clk_h.rate = hclk_psys;
0c1945d3 KK	463	clk_p.rate = pclk66;
	464	clk_p66.rate = pclk66;
	465	clk_p83.rate = pclk83;
0c1945d3	466
0c1945d3 KK	467	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
	468	s3c_set_clksrc(&clksrcs[ptr], true);
	469	}
	470
	471	static struct clk *clks[] __initdata = {
0c1945d3 KK	472	};
	473
	474	void __init s5pv210_register_clocks(void)
	475	{
	476	struct clk *clkp;
	477	int ret;
	478	int ptr;
	479
	480	ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
	481	if (ret > 0)
	482	printk(KERN_ERR "Failed to register %u clocks\n", ret);
	483
eb1ef1ed TA	484	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
	485	s3c_register_clksrc(sysclks[ptr], 1);
	486
0c1945d3 KK	487	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
	488	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
	489
	490	ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
	491	if (ret > 0)
	492	printk(KERN_ERR "Failed to register system clocks\n");
	493
	494	clkp = init_clocks_disable;
	495	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
	496	ret = s3c24xx_register_clock(clkp);
	497	if (ret < 0) {
	498	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	499	clkp->name, ret);
	500	}
	501	(clkp->enable)(clkp, 0);
	502	}
	503
	504	s3c_pwmclk_init();
	505	}