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0c1945d3 KK |
1 | /* linux/arch/arm/mach-s5pv210/clock.c |
2 | * | |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * S5PV210 - Clock support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/sysdev.h> | |
21 | #include <linux/io.h> | |
22 | ||
23 | #include <mach/map.h> | |
24 | ||
25 | #include <plat/cpu-freq.h> | |
26 | #include <mach/regs-clock.h> | |
27 | #include <plat/clock.h> | |
28 | #include <plat/cpu.h> | |
29 | #include <plat/pll.h> | |
30 | #include <plat/s5p-clock.h> | |
31 | #include <plat/clock-clksrc.h> | |
32 | #include <plat/s5pv210.h> | |
33 | ||
88695843 JL |
34 | static unsigned long xtal; |
35 | ||
59cda520 TA |
36 | static struct clksrc_clk clk_mout_apll = { |
37 | .clk = { | |
38 | .name = "mout_apll", | |
59cda520 TA |
39 | }, |
40 | .sources = &clk_src_apll, | |
41 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | |
42 | }; | |
43 | ||
44 | static struct clksrc_clk clk_mout_epll = { | |
45 | .clk = { | |
46 | .name = "mout_epll", | |
59cda520 TA |
47 | }, |
48 | .sources = &clk_src_epll, | |
49 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, | |
50 | }; | |
51 | ||
52 | static struct clksrc_clk clk_mout_mpll = { | |
53 | .clk = { | |
54 | .name = "mout_mpll", | |
59cda520 TA |
55 | }, |
56 | .sources = &clk_src_mpll, | |
57 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, | |
58 | }; | |
59 | ||
374e0bf5 TA |
60 | static struct clk *clkset_armclk_list[] = { |
61 | [0] = &clk_mout_apll.clk, | |
62 | [1] = &clk_mout_mpll.clk, | |
63 | }; | |
64 | ||
65 | static struct clksrc_sources clkset_armclk = { | |
66 | .sources = clkset_armclk_list, | |
67 | .nr_sources = ARRAY_SIZE(clkset_armclk_list), | |
68 | }; | |
69 | ||
70 | static struct clksrc_clk clk_armclk = { | |
71 | .clk = { | |
72 | .name = "armclk", | |
374e0bf5 TA |
73 | }, |
74 | .sources = &clkset_armclk, | |
75 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, | |
76 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, | |
77 | }; | |
78 | ||
af76a201 TA |
79 | static struct clksrc_clk clk_hclk_msys = { |
80 | .clk = { | |
81 | .name = "hclk_msys", | |
af76a201 TA |
82 | .parent = &clk_armclk.clk, |
83 | }, | |
84 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, | |
85 | }; | |
86 | ||
6ed91a20 TA |
87 | static struct clksrc_clk clk_pclk_msys = { |
88 | .clk = { | |
89 | .name = "pclk_msys", | |
6ed91a20 TA |
90 | .parent = &clk_hclk_msys.clk, |
91 | }, | |
92 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, | |
93 | }; | |
94 | ||
0fe967a1 TA |
95 | static struct clksrc_clk clk_sclk_a2m = { |
96 | .clk = { | |
97 | .name = "sclk_a2m", | |
0fe967a1 TA |
98 | .parent = &clk_mout_apll.clk, |
99 | }, | |
100 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, | |
101 | }; | |
102 | ||
103 | static struct clk *clkset_hclk_sys_list[] = { | |
104 | [0] = &clk_mout_mpll.clk, | |
105 | [1] = &clk_sclk_a2m.clk, | |
106 | }; | |
107 | ||
108 | static struct clksrc_sources clkset_hclk_sys = { | |
109 | .sources = clkset_hclk_sys_list, | |
110 | .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list), | |
111 | }; | |
112 | ||
113 | static struct clksrc_clk clk_hclk_dsys = { | |
114 | .clk = { | |
115 | .name = "hclk_dsys", | |
0fe967a1 TA |
116 | }, |
117 | .sources = &clkset_hclk_sys, | |
118 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, | |
119 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, | |
120 | }; | |
121 | ||
58772cd3 TA |
122 | static struct clksrc_clk clk_pclk_dsys = { |
123 | .clk = { | |
124 | .name = "pclk_dsys", | |
58772cd3 TA |
125 | .parent = &clk_hclk_dsys.clk, |
126 | }, | |
127 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, | |
128 | }; | |
129 | ||
acfa245f TA |
130 | static struct clksrc_clk clk_hclk_psys = { |
131 | .clk = { | |
132 | .name = "hclk_psys", | |
acfa245f TA |
133 | }, |
134 | .sources = &clkset_hclk_sys, | |
135 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, | |
136 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, | |
137 | }; | |
138 | ||
f44cf78b TA |
139 | static struct clksrc_clk clk_pclk_psys = { |
140 | .clk = { | |
141 | .name = "pclk_psys", | |
f44cf78b TA |
142 | .parent = &clk_hclk_psys.clk, |
143 | }, | |
144 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, | |
145 | }; | |
146 | ||
0c1945d3 KK |
147 | static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) |
148 | { | |
149 | return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); | |
150 | } | |
151 | ||
152 | static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable) | |
153 | { | |
154 | return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable); | |
155 | } | |
156 | ||
157 | static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable) | |
158 | { | |
159 | return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable); | |
160 | } | |
161 | ||
162 | static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable) | |
163 | { | |
164 | return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); | |
165 | } | |
166 | ||
f445dbd5 TA |
167 | static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) |
168 | { | |
169 | return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); | |
170 | } | |
171 | ||
154d62e4 MH |
172 | static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) |
173 | { | |
174 | return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); | |
175 | } | |
176 | ||
fbf05563 TS |
177 | static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) |
178 | { | |
179 | return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); | |
180 | } | |
181 | ||
182 | static int exynos4_clk_dac_ctrl(struct clk *clk, int enable) | |
183 | { | |
184 | return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable); | |
185 | } | |
186 | ||
f445dbd5 TA |
187 | static struct clk clk_sclk_hdmi27m = { |
188 | .name = "sclk_hdmi27m", | |
f445dbd5 TA |
189 | .rate = 27000000, |
190 | }; | |
191 | ||
2cf4c2e6 TA |
192 | static struct clk clk_sclk_hdmiphy = { |
193 | .name = "sclk_hdmiphy", | |
2cf4c2e6 TA |
194 | }; |
195 | ||
196 | static struct clk clk_sclk_usbphy0 = { | |
197 | .name = "sclk_usbphy0", | |
2cf4c2e6 TA |
198 | }; |
199 | ||
200 | static struct clk clk_sclk_usbphy1 = { | |
201 | .name = "sclk_usbphy1", | |
2cf4c2e6 TA |
202 | }; |
203 | ||
4583487c TA |
204 | static struct clk clk_pcmcdclk0 = { |
205 | .name = "pcmcdclk", | |
4583487c TA |
206 | }; |
207 | ||
208 | static struct clk clk_pcmcdclk1 = { | |
209 | .name = "pcmcdclk", | |
4583487c TA |
210 | }; |
211 | ||
212 | static struct clk clk_pcmcdclk2 = { | |
213 | .name = "pcmcdclk", | |
4583487c TA |
214 | }; |
215 | ||
dafc9543 BK |
216 | static struct clk dummy_apb_pclk = { |
217 | .name = "apb_pclk", | |
218 | .id = -1, | |
219 | }; | |
220 | ||
f445dbd5 TA |
221 | static struct clk *clkset_vpllsrc_list[] = { |
222 | [0] = &clk_fin_vpll, | |
223 | [1] = &clk_sclk_hdmi27m, | |
224 | }; | |
225 | ||
226 | static struct clksrc_sources clkset_vpllsrc = { | |
227 | .sources = clkset_vpllsrc_list, | |
228 | .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list), | |
229 | }; | |
230 | ||
231 | static struct clksrc_clk clk_vpllsrc = { | |
232 | .clk = { | |
233 | .name = "vpll_src", | |
f445dbd5 TA |
234 | .enable = s5pv210_clk_mask0_ctrl, |
235 | .ctrlbit = (1 << 7), | |
236 | }, | |
237 | .sources = &clkset_vpllsrc, | |
238 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 }, | |
239 | }; | |
240 | ||
241 | static struct clk *clkset_sclk_vpll_list[] = { | |
242 | [0] = &clk_vpllsrc.clk, | |
243 | [1] = &clk_fout_vpll, | |
244 | }; | |
245 | ||
246 | static struct clksrc_sources clkset_sclk_vpll = { | |
247 | .sources = clkset_sclk_vpll_list, | |
248 | .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), | |
249 | }; | |
250 | ||
251 | static struct clksrc_clk clk_sclk_vpll = { | |
252 | .clk = { | |
253 | .name = "sclk_vpll", | |
f445dbd5 TA |
254 | }, |
255 | .sources = &clkset_sclk_vpll, | |
256 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, | |
257 | }; | |
258 | ||
08f49d11 JL |
259 | static struct clk *clkset_moutdmc0src_list[] = { |
260 | [0] = &clk_sclk_a2m.clk, | |
261 | [1] = &clk_mout_mpll.clk, | |
262 | [2] = NULL, | |
263 | [3] = NULL, | |
264 | }; | |
265 | ||
266 | static struct clksrc_sources clkset_moutdmc0src = { | |
267 | .sources = clkset_moutdmc0src_list, | |
268 | .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list), | |
269 | }; | |
270 | ||
271 | static struct clksrc_clk clk_mout_dmc0 = { | |
272 | .clk = { | |
273 | .name = "mout_dmc0", | |
08f49d11 JL |
274 | }, |
275 | .sources = &clkset_moutdmc0src, | |
276 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, | |
277 | }; | |
278 | ||
279 | static struct clksrc_clk clk_sclk_dmc0 = { | |
280 | .clk = { | |
281 | .name = "sclk_dmc0", | |
08f49d11 JL |
282 | .parent = &clk_mout_dmc0.clk, |
283 | }, | |
284 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, | |
285 | }; | |
286 | ||
664f5b20 TA |
287 | static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk) |
288 | { | |
289 | return clk_get_rate(clk->parent) / 2; | |
290 | } | |
291 | ||
292 | static struct clk_ops clk_hclk_imem_ops = { | |
293 | .get_rate = s5pv210_clk_imem_get_rate, | |
294 | }; | |
295 | ||
88695843 JL |
296 | static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk) |
297 | { | |
298 | return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); | |
299 | } | |
300 | ||
301 | static struct clk_ops clk_fout_apll_ops = { | |
302 | .get_rate = s5pv210_clk_fout_apll_get_rate, | |
303 | }; | |
304 | ||
3c0fa647 | 305 | static struct clk init_clocks_off[] = { |
0c1945d3 | 306 | { |
dafc9543 | 307 | .name = "dma", |
1ce3ea61 | 308 | .devname = "dma-pl330.0", |
313068fd SY |
309 | .parent = &clk_hclk_psys.clk, |
310 | .enable = s5pv210_clk_ip0_ctrl, | |
311 | .ctrlbit = (1 << 3), | |
312 | }, { | |
dafc9543 | 313 | .name = "dma", |
1ce3ea61 | 314 | .devname = "dma-pl330.1", |
313068fd SY |
315 | .parent = &clk_hclk_psys.clk, |
316 | .enable = s5pv210_clk_ip0_ctrl, | |
317 | .ctrlbit = (1 << 4), | |
318 | }, { | |
0c1945d3 | 319 | .name = "rot", |
0fe967a1 | 320 | .parent = &clk_hclk_dsys.clk, |
0c1945d3 KK |
321 | .enable = s5pv210_clk_ip0_ctrl, |
322 | .ctrlbit = (1<<29), | |
da01c2f7 MS |
323 | }, { |
324 | .name = "fimc", | |
b2a9dd46 | 325 | .devname = "s5pv210-fimc.0", |
da01c2f7 MS |
326 | .parent = &clk_hclk_dsys.clk, |
327 | .enable = s5pv210_clk_ip0_ctrl, | |
328 | .ctrlbit = (1 << 24), | |
329 | }, { | |
330 | .name = "fimc", | |
b2a9dd46 | 331 | .devname = "s5pv210-fimc.1", |
da01c2f7 MS |
332 | .parent = &clk_hclk_dsys.clk, |
333 | .enable = s5pv210_clk_ip0_ctrl, | |
334 | .ctrlbit = (1 << 25), | |
335 | }, { | |
336 | .name = "fimc", | |
b2a9dd46 | 337 | .devname = "s5pv210-fimc.2", |
da01c2f7 MS |
338 | .parent = &clk_hclk_dsys.clk, |
339 | .enable = s5pv210_clk_ip0_ctrl, | |
340 | .ctrlbit = (1 << 26), | |
0f75a96b KD |
341 | }, { |
342 | .name = "mfc", | |
343 | .devname = "s5p-mfc", | |
344 | .parent = &clk_pclk_psys.clk, | |
345 | .enable = s5pv210_clk_ip0_ctrl, | |
346 | .ctrlbit = (1 << 16), | |
fbf05563 TS |
347 | }, { |
348 | .name = "dac", | |
349 | .devname = "s5p-sdo", | |
350 | .parent = &clk_hclk_dsys.clk, | |
351 | .enable = s5pv210_clk_ip1_ctrl, | |
352 | .ctrlbit = (1 << 10), | |
353 | }, { | |
354 | .name = "mixer", | |
355 | .devname = "s5p-mixer", | |
356 | .parent = &clk_hclk_dsys.clk, | |
357 | .enable = s5pv210_clk_ip1_ctrl, | |
358 | .ctrlbit = (1 << 9), | |
359 | }, { | |
360 | .name = "vp", | |
361 | .devname = "s5p-mixer", | |
362 | .parent = &clk_hclk_dsys.clk, | |
363 | .enable = s5pv210_clk_ip1_ctrl, | |
364 | .ctrlbit = (1 << 8), | |
365 | }, { | |
366 | .name = "hdmi", | |
367 | .devname = "s5pv210-hdmi", | |
368 | .parent = &clk_hclk_dsys.clk, | |
369 | .enable = s5pv210_clk_ip1_ctrl, | |
370 | .ctrlbit = (1 << 11), | |
371 | }, { | |
372 | .name = "hdmiphy", | |
373 | .devname = "s5pv210-hdmi", | |
374 | .enable = exynos4_clk_hdmiphy_ctrl, | |
375 | .ctrlbit = (1 << 0), | |
376 | }, { | |
377 | .name = "dacphy", | |
378 | .devname = "s5p-sdo", | |
379 | .enable = exynos4_clk_dac_ctrl, | |
380 | .ctrlbit = (1 << 0), | |
0c1945d3 KK |
381 | }, { |
382 | .name = "otg", | |
acfa245f | 383 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
384 | .enable = s5pv210_clk_ip1_ctrl, |
385 | .ctrlbit = (1<<16), | |
386 | }, { | |
387 | .name = "usb-host", | |
acfa245f | 388 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
389 | .enable = s5pv210_clk_ip1_ctrl, |
390 | .ctrlbit = (1<<17), | |
391 | }, { | |
392 | .name = "lcd", | |
0fe967a1 | 393 | .parent = &clk_hclk_dsys.clk, |
0c1945d3 KK |
394 | .enable = s5pv210_clk_ip1_ctrl, |
395 | .ctrlbit = (1<<0), | |
396 | }, { | |
397 | .name = "cfcon", | |
acfa245f | 398 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
399 | .enable = s5pv210_clk_ip1_ctrl, |
400 | .ctrlbit = (1<<25), | |
401 | }, { | |
402 | .name = "hsmmc", | |
b2a9dd46 | 403 | .devname = "s3c-sdhci.0", |
acfa245f | 404 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
405 | .enable = s5pv210_clk_ip2_ctrl, |
406 | .ctrlbit = (1<<16), | |
407 | }, { | |
408 | .name = "hsmmc", | |
b2a9dd46 | 409 | .devname = "s3c-sdhci.1", |
acfa245f | 410 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
411 | .enable = s5pv210_clk_ip2_ctrl, |
412 | .ctrlbit = (1<<17), | |
413 | }, { | |
414 | .name = "hsmmc", | |
b2a9dd46 | 415 | .devname = "s3c-sdhci.2", |
acfa245f | 416 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
417 | .enable = s5pv210_clk_ip2_ctrl, |
418 | .ctrlbit = (1<<18), | |
419 | }, { | |
420 | .name = "hsmmc", | |
b2a9dd46 | 421 | .devname = "s3c-sdhci.3", |
acfa245f | 422 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
423 | .enable = s5pv210_clk_ip2_ctrl, |
424 | .ctrlbit = (1<<19), | |
425 | }, { | |
426 | .name = "systimer", | |
f44cf78b | 427 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
428 | .enable = s5pv210_clk_ip3_ctrl, |
429 | .ctrlbit = (1<<16), | |
430 | }, { | |
431 | .name = "watchdog", | |
f44cf78b | 432 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
433 | .enable = s5pv210_clk_ip3_ctrl, |
434 | .ctrlbit = (1<<22), | |
435 | }, { | |
436 | .name = "rtc", | |
f44cf78b | 437 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
438 | .enable = s5pv210_clk_ip3_ctrl, |
439 | .ctrlbit = (1<<15), | |
440 | }, { | |
441 | .name = "i2c", | |
b2a9dd46 | 442 | .devname = "s3c2440-i2c.0", |
f44cf78b | 443 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
444 | .enable = s5pv210_clk_ip3_ctrl, |
445 | .ctrlbit = (1<<7), | |
446 | }, { | |
447 | .name = "i2c", | |
b2a9dd46 | 448 | .devname = "s3c2440-i2c.1", |
f44cf78b | 449 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 450 | .enable = s5pv210_clk_ip3_ctrl, |
f1c894de | 451 | .ctrlbit = (1 << 10), |
0c1945d3 KK |
452 | }, { |
453 | .name = "i2c", | |
b2a9dd46 | 454 | .devname = "s3c2440-i2c.2", |
f44cf78b | 455 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
456 | .enable = s5pv210_clk_ip3_ctrl, |
457 | .ctrlbit = (1<<9), | |
c40e7e0d TS |
458 | }, { |
459 | .name = "i2c", | |
460 | .devname = "s3c2440-hdmiphy-i2c", | |
461 | .parent = &clk_pclk_psys.clk, | |
462 | .enable = s5pv210_clk_ip3_ctrl, | |
463 | .ctrlbit = (1 << 11), | |
0c1945d3 KK |
464 | }, { |
465 | .name = "spi", | |
b2a9dd46 | 466 | .devname = "s3c64xx-spi.0", |
f44cf78b | 467 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
468 | .enable = s5pv210_clk_ip3_ctrl, |
469 | .ctrlbit = (1<<12), | |
470 | }, { | |
471 | .name = "spi", | |
b2a9dd46 | 472 | .devname = "s3c64xx-spi.1", |
f44cf78b | 473 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
474 | .enable = s5pv210_clk_ip3_ctrl, |
475 | .ctrlbit = (1<<13), | |
476 | }, { | |
477 | .name = "spi", | |
b2a9dd46 | 478 | .devname = "s3c64xx-spi.2", |
f44cf78b | 479 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
480 | .enable = s5pv210_clk_ip3_ctrl, |
481 | .ctrlbit = (1<<14), | |
482 | }, { | |
483 | .name = "timers", | |
f44cf78b | 484 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
485 | .enable = s5pv210_clk_ip3_ctrl, |
486 | .ctrlbit = (1<<23), | |
487 | }, { | |
488 | .name = "adc", | |
f44cf78b | 489 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
490 | .enable = s5pv210_clk_ip3_ctrl, |
491 | .ctrlbit = (1<<24), | |
492 | }, { | |
493 | .name = "keypad", | |
f44cf78b | 494 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
495 | .enable = s5pv210_clk_ip3_ctrl, |
496 | .ctrlbit = (1<<21), | |
497 | }, { | |
9aa2570e | 498 | .name = "iis", |
b2a9dd46 | 499 | .devname = "samsung-i2s.0", |
0c1945d3 KK |
500 | .parent = &clk_p, |
501 | .enable = s5pv210_clk_ip3_ctrl, | |
502 | .ctrlbit = (1<<4), | |
503 | }, { | |
9aa2570e | 504 | .name = "iis", |
b2a9dd46 | 505 | .devname = "samsung-i2s.1", |
0c1945d3 KK |
506 | .parent = &clk_p, |
507 | .enable = s5pv210_clk_ip3_ctrl, | |
154d62e4 | 508 | .ctrlbit = (1 << 5), |
0c1945d3 | 509 | }, { |
9aa2570e | 510 | .name = "iis", |
b2a9dd46 | 511 | .devname = "samsung-i2s.2", |
0c1945d3 KK |
512 | .parent = &clk_p, |
513 | .enable = s5pv210_clk_ip3_ctrl, | |
154d62e4 | 514 | .ctrlbit = (1 << 6), |
aa21ae3d SY |
515 | }, { |
516 | .name = "spdif", | |
aa21ae3d SY |
517 | .parent = &clk_p, |
518 | .enable = s5pv210_clk_ip3_ctrl, | |
519 | .ctrlbit = (1 << 0), | |
154d62e4 | 520 | }, |
0c1945d3 KK |
521 | }; |
522 | ||
523 | static struct clk init_clocks[] = { | |
524 | { | |
664f5b20 | 525 | .name = "hclk_imem", |
664f5b20 TA |
526 | .parent = &clk_hclk_msys.clk, |
527 | .ctrlbit = (1 << 5), | |
528 | .enable = s5pv210_clk_ip0_ctrl, | |
529 | .ops = &clk_hclk_imem_ops, | |
530 | }, { | |
0c1945d3 | 531 | .name = "uart", |
b2a9dd46 | 532 | .devname = "s5pv210-uart.0", |
f44cf78b | 533 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 534 | .enable = s5pv210_clk_ip3_ctrl, |
154d62e4 | 535 | .ctrlbit = (1 << 17), |
0c1945d3 KK |
536 | }, { |
537 | .name = "uart", | |
b2a9dd46 | 538 | .devname = "s5pv210-uart.1", |
f44cf78b | 539 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 540 | .enable = s5pv210_clk_ip3_ctrl, |
154d62e4 | 541 | .ctrlbit = (1 << 18), |
0c1945d3 KK |
542 | }, { |
543 | .name = "uart", | |
b2a9dd46 | 544 | .devname = "s5pv210-uart.2", |
f44cf78b | 545 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 546 | .enable = s5pv210_clk_ip3_ctrl, |
154d62e4 | 547 | .ctrlbit = (1 << 19), |
0c1945d3 KK |
548 | }, { |
549 | .name = "uart", | |
b2a9dd46 | 550 | .devname = "s5pv210-uart.3", |
f44cf78b | 551 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 552 | .enable = s5pv210_clk_ip3_ctrl, |
154d62e4 | 553 | .ctrlbit = (1 << 20), |
81f9becd TA |
554 | }, { |
555 | .name = "sromc", | |
81f9becd TA |
556 | .parent = &clk_hclk_psys.clk, |
557 | .enable = s5pv210_clk_ip1_ctrl, | |
558 | .ctrlbit = (1 << 26), | |
0c1945d3 KK |
559 | }, |
560 | }; | |
561 | ||
0c1945d3 KK |
562 | static struct clk *clkset_uart_list[] = { |
563 | [6] = &clk_mout_mpll.clk, | |
564 | [7] = &clk_mout_epll.clk, | |
565 | }; | |
566 | ||
567 | static struct clksrc_sources clkset_uart = { | |
568 | .sources = clkset_uart_list, | |
569 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | |
570 | }; | |
571 | ||
2cf4c2e6 TA |
572 | static struct clk *clkset_group1_list[] = { |
573 | [0] = &clk_sclk_a2m.clk, | |
574 | [1] = &clk_mout_mpll.clk, | |
575 | [2] = &clk_mout_epll.clk, | |
576 | [3] = &clk_sclk_vpll.clk, | |
577 | }; | |
578 | ||
579 | static struct clksrc_sources clkset_group1 = { | |
580 | .sources = clkset_group1_list, | |
581 | .nr_sources = ARRAY_SIZE(clkset_group1_list), | |
582 | }; | |
583 | ||
584 | static struct clk *clkset_sclk_onenand_list[] = { | |
585 | [0] = &clk_hclk_psys.clk, | |
586 | [1] = &clk_hclk_dsys.clk, | |
587 | }; | |
588 | ||
589 | static struct clksrc_sources clkset_sclk_onenand = { | |
590 | .sources = clkset_sclk_onenand_list, | |
591 | .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list), | |
592 | }; | |
593 | ||
9e20614b TA |
594 | static struct clk *clkset_sclk_dac_list[] = { |
595 | [0] = &clk_sclk_vpll.clk, | |
596 | [1] = &clk_sclk_hdmiphy, | |
597 | }; | |
598 | ||
599 | static struct clksrc_sources clkset_sclk_dac = { | |
600 | .sources = clkset_sclk_dac_list, | |
601 | .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list), | |
602 | }; | |
603 | ||
604 | static struct clksrc_clk clk_sclk_dac = { | |
605 | .clk = { | |
606 | .name = "sclk_dac", | |
154d62e4 MH |
607 | .enable = s5pv210_clk_mask0_ctrl, |
608 | .ctrlbit = (1 << 2), | |
9e20614b TA |
609 | }, |
610 | .sources = &clkset_sclk_dac, | |
611 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 }, | |
612 | }; | |
613 | ||
614 | static struct clksrc_clk clk_sclk_pixel = { | |
615 | .clk = { | |
616 | .name = "sclk_pixel", | |
9e20614b TA |
617 | .parent = &clk_sclk_vpll.clk, |
618 | }, | |
619 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, | |
620 | }; | |
621 | ||
622 | static struct clk *clkset_sclk_hdmi_list[] = { | |
623 | [0] = &clk_sclk_pixel.clk, | |
624 | [1] = &clk_sclk_hdmiphy, | |
625 | }; | |
626 | ||
627 | static struct clksrc_sources clkset_sclk_hdmi = { | |
628 | .sources = clkset_sclk_hdmi_list, | |
629 | .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list), | |
630 | }; | |
631 | ||
632 | static struct clksrc_clk clk_sclk_hdmi = { | |
633 | .clk = { | |
634 | .name = "sclk_hdmi", | |
154d62e4 MH |
635 | .enable = s5pv210_clk_mask0_ctrl, |
636 | .ctrlbit = (1 << 0), | |
9e20614b TA |
637 | }, |
638 | .sources = &clkset_sclk_hdmi, | |
639 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, | |
640 | }; | |
641 | ||
642 | static struct clk *clkset_sclk_mixer_list[] = { | |
643 | [0] = &clk_sclk_dac.clk, | |
644 | [1] = &clk_sclk_hdmi.clk, | |
645 | }; | |
646 | ||
647 | static struct clksrc_sources clkset_sclk_mixer = { | |
648 | .sources = clkset_sclk_mixer_list, | |
649 | .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), | |
650 | }; | |
651 | ||
fbf05563 TS |
652 | static struct clksrc_clk clk_sclk_mixer = { |
653 | .clk = { | |
654 | .name = "sclk_mixer", | |
655 | .enable = s5pv210_clk_mask0_ctrl, | |
656 | .ctrlbit = (1 << 1), | |
657 | }, | |
658 | .sources = &clkset_sclk_mixer, | |
659 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, | |
660 | }; | |
661 | ||
662 | static struct clksrc_clk *sclk_tv[] = { | |
663 | &clk_sclk_dac, | |
664 | &clk_sclk_pixel, | |
665 | &clk_sclk_hdmi, | |
666 | &clk_sclk_mixer, | |
667 | }; | |
668 | ||
4583487c TA |
669 | static struct clk *clkset_sclk_audio0_list[] = { |
670 | [0] = &clk_ext_xtal_mux, | |
671 | [1] = &clk_pcmcdclk0, | |
672 | [2] = &clk_sclk_hdmi27m, | |
673 | [3] = &clk_sclk_usbphy0, | |
674 | [4] = &clk_sclk_usbphy1, | |
675 | [5] = &clk_sclk_hdmiphy, | |
676 | [6] = &clk_mout_mpll.clk, | |
677 | [7] = &clk_mout_epll.clk, | |
678 | [8] = &clk_sclk_vpll.clk, | |
679 | }; | |
680 | ||
681 | static struct clksrc_sources clkset_sclk_audio0 = { | |
682 | .sources = clkset_sclk_audio0_list, | |
683 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list), | |
684 | }; | |
685 | ||
686 | static struct clksrc_clk clk_sclk_audio0 = { | |
687 | .clk = { | |
688 | .name = "sclk_audio", | |
b2a9dd46 | 689 | .devname = "soc-audio.0", |
154d62e4 MH |
690 | .enable = s5pv210_clk_mask0_ctrl, |
691 | .ctrlbit = (1 << 24), | |
4583487c TA |
692 | }, |
693 | .sources = &clkset_sclk_audio0, | |
694 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 }, | |
695 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 }, | |
696 | }; | |
697 | ||
698 | static struct clk *clkset_sclk_audio1_list[] = { | |
699 | [0] = &clk_ext_xtal_mux, | |
700 | [1] = &clk_pcmcdclk1, | |
701 | [2] = &clk_sclk_hdmi27m, | |
702 | [3] = &clk_sclk_usbphy0, | |
703 | [4] = &clk_sclk_usbphy1, | |
704 | [5] = &clk_sclk_hdmiphy, | |
705 | [6] = &clk_mout_mpll.clk, | |
706 | [7] = &clk_mout_epll.clk, | |
707 | [8] = &clk_sclk_vpll.clk, | |
708 | }; | |
709 | ||
710 | static struct clksrc_sources clkset_sclk_audio1 = { | |
711 | .sources = clkset_sclk_audio1_list, | |
712 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list), | |
713 | }; | |
714 | ||
715 | static struct clksrc_clk clk_sclk_audio1 = { | |
716 | .clk = { | |
717 | .name = "sclk_audio", | |
b2a9dd46 | 718 | .devname = "soc-audio.1", |
154d62e4 MH |
719 | .enable = s5pv210_clk_mask0_ctrl, |
720 | .ctrlbit = (1 << 25), | |
4583487c TA |
721 | }, |
722 | .sources = &clkset_sclk_audio1, | |
723 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 }, | |
724 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 }, | |
725 | }; | |
726 | ||
727 | static struct clk *clkset_sclk_audio2_list[] = { | |
728 | [0] = &clk_ext_xtal_mux, | |
729 | [1] = &clk_pcmcdclk0, | |
730 | [2] = &clk_sclk_hdmi27m, | |
731 | [3] = &clk_sclk_usbphy0, | |
732 | [4] = &clk_sclk_usbphy1, | |
733 | [5] = &clk_sclk_hdmiphy, | |
734 | [6] = &clk_mout_mpll.clk, | |
735 | [7] = &clk_mout_epll.clk, | |
736 | [8] = &clk_sclk_vpll.clk, | |
737 | }; | |
738 | ||
739 | static struct clksrc_sources clkset_sclk_audio2 = { | |
740 | .sources = clkset_sclk_audio2_list, | |
741 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list), | |
742 | }; | |
743 | ||
744 | static struct clksrc_clk clk_sclk_audio2 = { | |
745 | .clk = { | |
746 | .name = "sclk_audio", | |
b2a9dd46 | 747 | .devname = "soc-audio.2", |
154d62e4 MH |
748 | .enable = s5pv210_clk_mask0_ctrl, |
749 | .ctrlbit = (1 << 26), | |
4583487c TA |
750 | }, |
751 | .sources = &clkset_sclk_audio2, | |
752 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 }, | |
753 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 }, | |
754 | }; | |
755 | ||
756 | static struct clk *clkset_sclk_spdif_list[] = { | |
757 | [0] = &clk_sclk_audio0.clk, | |
758 | [1] = &clk_sclk_audio1.clk, | |
759 | [2] = &clk_sclk_audio2.clk, | |
760 | }; | |
761 | ||
762 | static struct clksrc_sources clkset_sclk_spdif = { | |
763 | .sources = clkset_sclk_spdif_list, | |
764 | .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), | |
765 | }; | |
766 | ||
aa21ae3d SY |
767 | static struct clksrc_clk clk_sclk_spdif = { |
768 | .clk = { | |
769 | .name = "sclk_spdif", | |
aa21ae3d SY |
770 | .enable = s5pv210_clk_mask0_ctrl, |
771 | .ctrlbit = (1 << 27), | |
65f5eaa2 | 772 | .ops = &s5p_sclk_spdif_ops, |
aa21ae3d SY |
773 | }, |
774 | .sources = &clkset_sclk_spdif, | |
775 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, | |
776 | }; | |
777 | ||
f64cacc3 TA |
778 | static struct clk *clkset_group2_list[] = { |
779 | [0] = &clk_ext_xtal_mux, | |
780 | [1] = &clk_xusbxti, | |
781 | [2] = &clk_sclk_hdmi27m, | |
782 | [3] = &clk_sclk_usbphy0, | |
783 | [4] = &clk_sclk_usbphy1, | |
784 | [5] = &clk_sclk_hdmiphy, | |
785 | [6] = &clk_mout_mpll.clk, | |
786 | [7] = &clk_mout_epll.clk, | |
787 | [8] = &clk_sclk_vpll.clk, | |
788 | }; | |
789 | ||
790 | static struct clksrc_sources clkset_group2 = { | |
791 | .sources = clkset_group2_list, | |
792 | .nr_sources = ARRAY_SIZE(clkset_group2_list), | |
793 | }; | |
794 | ||
0c1945d3 KK |
795 | static struct clksrc_clk clksrcs[] = { |
796 | { | |
2cf4c2e6 TA |
797 | .clk = { |
798 | .name = "sclk_dmc", | |
2cf4c2e6 TA |
799 | }, |
800 | .sources = &clkset_group1, | |
801 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, | |
802 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, | |
803 | }, { | |
804 | .clk = { | |
805 | .name = "sclk_onenand", | |
2cf4c2e6 TA |
806 | }, |
807 | .sources = &clkset_sclk_onenand, | |
808 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, | |
809 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, | |
f64cacc3 TA |
810 | }, { |
811 | .clk = { | |
812 | .name = "sclk_fimc", | |
b2a9dd46 | 813 | .devname = "s5pv210-fimc.0", |
154d62e4 MH |
814 | .enable = s5pv210_clk_mask1_ctrl, |
815 | .ctrlbit = (1 << 2), | |
f64cacc3 TA |
816 | }, |
817 | .sources = &clkset_group2, | |
818 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 }, | |
819 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, | |
820 | }, { | |
821 | .clk = { | |
822 | .name = "sclk_fimc", | |
b2a9dd46 | 823 | .devname = "s5pv210-fimc.1", |
154d62e4 MH |
824 | .enable = s5pv210_clk_mask1_ctrl, |
825 | .ctrlbit = (1 << 3), | |
f64cacc3 TA |
826 | }, |
827 | .sources = &clkset_group2, | |
828 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 }, | |
829 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 }, | |
830 | }, { | |
831 | .clk = { | |
832 | .name = "sclk_fimc", | |
b2a9dd46 | 833 | .devname = "s5pv210-fimc.2", |
154d62e4 MH |
834 | .enable = s5pv210_clk_mask1_ctrl, |
835 | .ctrlbit = (1 << 4), | |
f64cacc3 TA |
836 | }, |
837 | .sources = &clkset_group2, | |
838 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 }, | |
839 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, | |
840 | }, { | |
841 | .clk = { | |
83427c23 | 842 | .name = "sclk_cam0", |
154d62e4 MH |
843 | .enable = s5pv210_clk_mask0_ctrl, |
844 | .ctrlbit = (1 << 3), | |
f64cacc3 TA |
845 | }, |
846 | .sources = &clkset_group2, | |
847 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 }, | |
848 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, | |
849 | }, { | |
850 | .clk = { | |
83427c23 | 851 | .name = "sclk_cam1", |
154d62e4 MH |
852 | .enable = s5pv210_clk_mask0_ctrl, |
853 | .ctrlbit = (1 << 4), | |
f64cacc3 TA |
854 | }, |
855 | .sources = &clkset_group2, | |
856 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 }, | |
857 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 }, | |
858 | }, { | |
859 | .clk = { | |
860 | .name = "sclk_fimd", | |
154d62e4 MH |
861 | .enable = s5pv210_clk_mask0_ctrl, |
862 | .ctrlbit = (1 << 5), | |
f64cacc3 TA |
863 | }, |
864 | .sources = &clkset_group2, | |
865 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 }, | |
866 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, | |
867 | }, { | |
868 | .clk = { | |
869 | .name = "sclk_mmc", | |
b2a9dd46 | 870 | .devname = "s3c-sdhci.0", |
154d62e4 MH |
871 | .enable = s5pv210_clk_mask0_ctrl, |
872 | .ctrlbit = (1 << 8), | |
f64cacc3 TA |
873 | }, |
874 | .sources = &clkset_group2, | |
875 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, | |
876 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, | |
877 | }, { | |
878 | .clk = { | |
879 | .name = "sclk_mmc", | |
b2a9dd46 | 880 | .devname = "s3c-sdhci.1", |
154d62e4 MH |
881 | .enable = s5pv210_clk_mask0_ctrl, |
882 | .ctrlbit = (1 << 9), | |
f64cacc3 TA |
883 | }, |
884 | .sources = &clkset_group2, | |
885 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, | |
886 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, | |
887 | }, { | |
888 | .clk = { | |
889 | .name = "sclk_mmc", | |
b2a9dd46 | 890 | .devname = "s3c-sdhci.2", |
154d62e4 MH |
891 | .enable = s5pv210_clk_mask0_ctrl, |
892 | .ctrlbit = (1 << 10), | |
f64cacc3 TA |
893 | }, |
894 | .sources = &clkset_group2, | |
895 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, | |
896 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, | |
897 | }, { | |
898 | .clk = { | |
899 | .name = "sclk_mmc", | |
b2a9dd46 | 900 | .devname = "s3c-sdhci.3", |
154d62e4 MH |
901 | .enable = s5pv210_clk_mask0_ctrl, |
902 | .ctrlbit = (1 << 11), | |
f64cacc3 TA |
903 | }, |
904 | .sources = &clkset_group2, | |
905 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, | |
906 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, | |
907 | }, { | |
908 | .clk = { | |
909 | .name = "sclk_mfc", | |
0f75a96b | 910 | .devname = "s5p-mfc", |
f64cacc3 TA |
911 | .enable = s5pv210_clk_ip0_ctrl, |
912 | .ctrlbit = (1 << 16), | |
913 | }, | |
914 | .sources = &clkset_group1, | |
915 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, | |
916 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, | |
917 | }, { | |
918 | .clk = { | |
919 | .name = "sclk_g2d", | |
f64cacc3 TA |
920 | .enable = s5pv210_clk_ip0_ctrl, |
921 | .ctrlbit = (1 << 12), | |
922 | }, | |
923 | .sources = &clkset_group1, | |
924 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, | |
925 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, | |
926 | }, { | |
927 | .clk = { | |
928 | .name = "sclk_g3d", | |
f64cacc3 TA |
929 | .enable = s5pv210_clk_ip0_ctrl, |
930 | .ctrlbit = (1 << 8), | |
931 | }, | |
932 | .sources = &clkset_group1, | |
933 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, | |
934 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, | |
935 | }, { | |
936 | .clk = { | |
937 | .name = "sclk_csis", | |
154d62e4 MH |
938 | .enable = s5pv210_clk_mask0_ctrl, |
939 | .ctrlbit = (1 << 6), | |
f64cacc3 TA |
940 | }, |
941 | .sources = &clkset_group2, | |
942 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, | |
943 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, | |
944 | }, { | |
945 | .clk = { | |
946 | .name = "sclk_spi", | |
b2a9dd46 | 947 | .devname = "s3c64xx-spi.0", |
154d62e4 MH |
948 | .enable = s5pv210_clk_mask0_ctrl, |
949 | .ctrlbit = (1 << 16), | |
f64cacc3 TA |
950 | }, |
951 | .sources = &clkset_group2, | |
952 | .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, | |
953 | .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 }, | |
954 | }, { | |
955 | .clk = { | |
956 | .name = "sclk_spi", | |
b2a9dd46 | 957 | .devname = "s3c64xx-spi.1", |
154d62e4 MH |
958 | .enable = s5pv210_clk_mask0_ctrl, |
959 | .ctrlbit = (1 << 17), | |
f64cacc3 TA |
960 | }, |
961 | .sources = &clkset_group2, | |
962 | .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, | |
963 | .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 }, | |
964 | }, { | |
965 | .clk = { | |
966 | .name = "sclk_pwi", | |
154d62e4 MH |
967 | .enable = s5pv210_clk_mask0_ctrl, |
968 | .ctrlbit = (1 << 29), | |
f64cacc3 TA |
969 | }, |
970 | .sources = &clkset_group2, | |
971 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 }, | |
972 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 }, | |
973 | }, { | |
974 | .clk = { | |
975 | .name = "sclk_pwm", | |
154d62e4 MH |
976 | .enable = s5pv210_clk_mask0_ctrl, |
977 | .ctrlbit = (1 << 19), | |
f64cacc3 TA |
978 | }, |
979 | .sources = &clkset_group2, | |
980 | .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 }, | |
981 | .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 }, | |
9e20614b | 982 | }, |
0c1945d3 KK |
983 | }; |
984 | ||
0cfb26e1 TA |
985 | static struct clksrc_clk clk_sclk_uart0 = { |
986 | .clk = { | |
987 | .name = "uclk1", | |
988 | .devname = "s5pv210-uart.0", | |
989 | .enable = s5pv210_clk_mask0_ctrl, | |
990 | .ctrlbit = (1 << 12), | |
991 | }, | |
992 | .sources = &clkset_uart, | |
993 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, | |
994 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, | |
995 | }; | |
996 | ||
997 | static struct clksrc_clk clk_sclk_uart1 = { | |
998 | .clk = { | |
999 | .name = "uclk1", | |
1000 | .devname = "s5pv210-uart.1", | |
1001 | .enable = s5pv210_clk_mask0_ctrl, | |
1002 | .ctrlbit = (1 << 13), | |
1003 | }, | |
1004 | .sources = &clkset_uart, | |
1005 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, | |
1006 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, | |
1007 | }; | |
1008 | ||
1009 | static struct clksrc_clk clk_sclk_uart2 = { | |
1010 | .clk = { | |
1011 | .name = "uclk1", | |
1012 | .devname = "s5pv210-uart.2", | |
1013 | .enable = s5pv210_clk_mask0_ctrl, | |
1014 | .ctrlbit = (1 << 14), | |
1015 | }, | |
1016 | .sources = &clkset_uart, | |
1017 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, | |
1018 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 }, | |
1019 | }; | |
1020 | ||
1021 | static struct clksrc_clk clk_sclk_uart3 = { | |
1022 | .clk = { | |
1023 | .name = "uclk1", | |
1024 | .devname = "s5pv210-uart.3", | |
1025 | .enable = s5pv210_clk_mask0_ctrl, | |
1026 | .ctrlbit = (1 << 15), | |
1027 | }, | |
1028 | .sources = &clkset_uart, | |
1029 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, | |
1030 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, | |
1031 | }; | |
1032 | ||
1033 | static struct clksrc_clk *clksrc_cdev[] = { | |
1034 | &clk_sclk_uart0, | |
1035 | &clk_sclk_uart1, | |
1036 | &clk_sclk_uart2, | |
1037 | &clk_sclk_uart3, | |
1038 | }; | |
1039 | ||
0c1945d3 | 1040 | /* Clock initialisation code */ |
eb1ef1ed | 1041 | static struct clksrc_clk *sysclks[] = { |
0c1945d3 KK |
1042 | &clk_mout_apll, |
1043 | &clk_mout_epll, | |
1044 | &clk_mout_mpll, | |
374e0bf5 | 1045 | &clk_armclk, |
af76a201 | 1046 | &clk_hclk_msys, |
0fe967a1 TA |
1047 | &clk_sclk_a2m, |
1048 | &clk_hclk_dsys, | |
acfa245f | 1049 | &clk_hclk_psys, |
6ed91a20 | 1050 | &clk_pclk_msys, |
58772cd3 | 1051 | &clk_pclk_dsys, |
f44cf78b | 1052 | &clk_pclk_psys, |
f445dbd5 TA |
1053 | &clk_vpllsrc, |
1054 | &clk_sclk_vpll, | |
08f49d11 JL |
1055 | &clk_mout_dmc0, |
1056 | &clk_sclk_dmc0, | |
900fa019 SY |
1057 | &clk_sclk_audio0, |
1058 | &clk_sclk_audio1, | |
1059 | &clk_sclk_audio2, | |
1060 | &clk_sclk_spdif, | |
0c1945d3 KK |
1061 | }; |
1062 | ||
c9fa7a08 SY |
1063 | static u32 epll_div[][6] = { |
1064 | { 48000000, 0, 48, 3, 3, 0 }, | |
1065 | { 96000000, 0, 48, 3, 2, 0 }, | |
1066 | { 144000000, 1, 72, 3, 2, 0 }, | |
1067 | { 192000000, 0, 48, 3, 1, 0 }, | |
1068 | { 288000000, 1, 72, 3, 1, 0 }, | |
1069 | { 32750000, 1, 65, 3, 4, 35127 }, | |
1070 | { 32768000, 1, 65, 3, 4, 35127 }, | |
1071 | { 45158400, 0, 45, 3, 3, 10355 }, | |
1072 | { 45000000, 0, 45, 3, 3, 10355 }, | |
1073 | { 45158000, 0, 45, 3, 3, 10355 }, | |
1074 | { 49125000, 0, 49, 3, 3, 9961 }, | |
1075 | { 49152000, 0, 49, 3, 3, 9961 }, | |
1076 | { 67737600, 1, 67, 3, 3, 48366 }, | |
1077 | { 67738000, 1, 67, 3, 3, 48366 }, | |
1078 | { 73800000, 1, 73, 3, 3, 47710 }, | |
1079 | { 73728000, 1, 73, 3, 3, 47710 }, | |
1080 | { 36000000, 1, 32, 3, 4, 0 }, | |
1081 | { 60000000, 1, 60, 3, 3, 0 }, | |
1082 | { 72000000, 1, 72, 3, 3, 0 }, | |
1083 | { 80000000, 1, 80, 3, 3, 0 }, | |
1084 | { 84000000, 0, 42, 3, 2, 0 }, | |
1085 | { 50000000, 0, 50, 3, 3, 0 }, | |
1086 | }; | |
1087 | ||
1088 | static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate) | |
1089 | { | |
1090 | unsigned int epll_con, epll_con_k; | |
1091 | unsigned int i; | |
1092 | ||
1093 | /* Return if nothing changed */ | |
1094 | if (clk->rate == rate) | |
1095 | return 0; | |
1096 | ||
1097 | epll_con = __raw_readl(S5P_EPLL_CON); | |
1098 | epll_con_k = __raw_readl(S5P_EPLL_CON1); | |
1099 | ||
1100 | epll_con_k &= ~PLL46XX_KDIV_MASK; | |
1101 | epll_con &= ~(1 << 27 | | |
1102 | PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | | |
1103 | PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | | |
1104 | PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); | |
1105 | ||
1106 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { | |
1107 | if (epll_div[i][0] == rate) { | |
1108 | epll_con_k |= epll_div[i][5] << 0; | |
1109 | epll_con |= (epll_div[i][1] << 27 | | |
1110 | epll_div[i][2] << PLL46XX_MDIV_SHIFT | | |
1111 | epll_div[i][3] << PLL46XX_PDIV_SHIFT | | |
1112 | epll_div[i][4] << PLL46XX_SDIV_SHIFT); | |
1113 | break; | |
1114 | } | |
1115 | } | |
1116 | ||
1117 | if (i == ARRAY_SIZE(epll_div)) { | |
1118 | printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", | |
1119 | __func__); | |
1120 | return -EINVAL; | |
1121 | } | |
1122 | ||
1123 | __raw_writel(epll_con, S5P_EPLL_CON); | |
1124 | __raw_writel(epll_con_k, S5P_EPLL_CON1); | |
1125 | ||
9616674a SY |
1126 | printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", |
1127 | clk->rate, rate); | |
1128 | ||
c9fa7a08 SY |
1129 | clk->rate = rate; |
1130 | ||
1131 | return 0; | |
1132 | } | |
1133 | ||
1134 | static struct clk_ops s5pv210_epll_ops = { | |
1135 | .set_rate = s5pv210_epll_set_rate, | |
1136 | .get_rate = s5p_epll_get_rate, | |
1137 | }; | |
1138 | ||
fbf05563 TS |
1139 | static u32 vpll_div[][5] = { |
1140 | { 54000000, 3, 53, 3, 0 }, | |
1141 | { 108000000, 3, 53, 2, 0 }, | |
1142 | }; | |
1143 | ||
1144 | static unsigned long s5pv210_vpll_get_rate(struct clk *clk) | |
1145 | { | |
1146 | return clk->rate; | |
1147 | } | |
1148 | ||
1149 | static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate) | |
1150 | { | |
1151 | unsigned int vpll_con; | |
1152 | unsigned int i; | |
1153 | ||
1154 | /* Return if nothing changed */ | |
1155 | if (clk->rate == rate) | |
1156 | return 0; | |
1157 | ||
1158 | vpll_con = __raw_readl(S5P_VPLL_CON); | |
1159 | vpll_con &= ~(0x1 << 27 | \ | |
1160 | PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT | \ | |
1161 | PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT | \ | |
1162 | PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT); | |
1163 | ||
1164 | for (i = 0; i < ARRAY_SIZE(vpll_div); i++) { | |
1165 | if (vpll_div[i][0] == rate) { | |
1166 | vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT; | |
1167 | vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT; | |
1168 | vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT; | |
1169 | vpll_con |= vpll_div[i][4] << 27; | |
1170 | break; | |
1171 | } | |
1172 | } | |
1173 | ||
1174 | if (i == ARRAY_SIZE(vpll_div)) { | |
1175 | printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", | |
1176 | __func__); | |
1177 | return -EINVAL; | |
1178 | } | |
1179 | ||
1180 | __raw_writel(vpll_con, S5P_VPLL_CON); | |
1181 | ||
1182 | /* Wait for VPLL lock */ | |
1183 | while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT))) | |
1184 | continue; | |
1185 | ||
1186 | clk->rate = rate; | |
1187 | return 0; | |
1188 | } | |
1189 | static struct clk_ops s5pv210_vpll_ops = { | |
1190 | .get_rate = s5pv210_vpll_get_rate, | |
1191 | .set_rate = s5pv210_vpll_set_rate, | |
1192 | }; | |
1193 | ||
0c1945d3 KK |
1194 | void __init_or_cpufreq s5pv210_setup_clocks(void) |
1195 | { | |
1196 | struct clk *xtal_clk; | |
f445dbd5 | 1197 | unsigned long vpllsrc; |
0c1945d3 | 1198 | unsigned long armclk; |
af76a201 | 1199 | unsigned long hclk_msys; |
0fe967a1 | 1200 | unsigned long hclk_dsys; |
acfa245f | 1201 | unsigned long hclk_psys; |
6ed91a20 | 1202 | unsigned long pclk_msys; |
58772cd3 | 1203 | unsigned long pclk_dsys; |
f44cf78b | 1204 | unsigned long pclk_psys; |
0c1945d3 KK |
1205 | unsigned long apll; |
1206 | unsigned long mpll; | |
1207 | unsigned long epll; | |
f445dbd5 | 1208 | unsigned long vpll; |
0c1945d3 KK |
1209 | unsigned int ptr; |
1210 | u32 clkdiv0, clkdiv1; | |
1211 | ||
c9fa7a08 SY |
1212 | /* Set functions for clk_fout_epll */ |
1213 | clk_fout_epll.enable = s5p_epll_enable; | |
1214 | clk_fout_epll.ops = &s5pv210_epll_ops; | |
1215 | ||
0c1945d3 KK |
1216 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); |
1217 | ||
1218 | clkdiv0 = __raw_readl(S5P_CLK_DIV0); | |
1219 | clkdiv1 = __raw_readl(S5P_CLK_DIV1); | |
1220 | ||
1221 | printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", | |
1222 | __func__, clkdiv0, clkdiv1); | |
1223 | ||
1224 | xtal_clk = clk_get(NULL, "xtal"); | |
1225 | BUG_ON(IS_ERR(xtal_clk)); | |
1226 | ||
1227 | xtal = clk_get_rate(xtal_clk); | |
1228 | clk_put(xtal_clk); | |
1229 | ||
1230 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | |
1231 | ||
1232 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); | |
1233 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); | |
42a6e20e SY |
1234 | epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON), |
1235 | __raw_readl(S5P_EPLL_CON1), pll_4600); | |
f445dbd5 TA |
1236 | vpllsrc = clk_get_rate(&clk_vpllsrc.clk); |
1237 | vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); | |
0c1945d3 | 1238 | |
88695843 | 1239 | clk_fout_apll.ops = &clk_fout_apll_ops; |
c62ec6a9 TA |
1240 | clk_fout_mpll.rate = mpll; |
1241 | clk_fout_epll.rate = epll; | |
fbf05563 | 1242 | clk_fout_vpll.ops = &s5pv210_vpll_ops; |
f445dbd5 | 1243 | clk_fout_vpll.rate = vpll; |
c62ec6a9 | 1244 | |
f445dbd5 TA |
1245 | printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", |
1246 | apll, mpll, epll, vpll); | |
0c1945d3 | 1247 | |
374e0bf5 | 1248 | armclk = clk_get_rate(&clk_armclk.clk); |
af76a201 | 1249 | hclk_msys = clk_get_rate(&clk_hclk_msys.clk); |
0fe967a1 | 1250 | hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk); |
acfa245f | 1251 | hclk_psys = clk_get_rate(&clk_hclk_psys.clk); |
6ed91a20 | 1252 | pclk_msys = clk_get_rate(&clk_pclk_msys.clk); |
58772cd3 | 1253 | pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk); |
f44cf78b | 1254 | pclk_psys = clk_get_rate(&clk_pclk_psys.clk); |
0c1945d3 | 1255 | |
acfa245f TA |
1256 | printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n" |
1257 | "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", | |
1258 | armclk, hclk_msys, hclk_dsys, hclk_psys, | |
f44cf78b | 1259 | pclk_msys, pclk_dsys, pclk_psys); |
0c1945d3 | 1260 | |
0c1945d3 | 1261 | clk_f.rate = armclk; |
acfa245f | 1262 | clk_h.rate = hclk_psys; |
f44cf78b | 1263 | clk_p.rate = pclk_psys; |
0c1945d3 | 1264 | |
0c1945d3 KK |
1265 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) |
1266 | s3c_set_clksrc(&clksrcs[ptr], true); | |
1267 | } | |
1268 | ||
1269 | static struct clk *clks[] __initdata = { | |
f445dbd5 | 1270 | &clk_sclk_hdmi27m, |
2cf4c2e6 TA |
1271 | &clk_sclk_hdmiphy, |
1272 | &clk_sclk_usbphy0, | |
1273 | &clk_sclk_usbphy1, | |
4583487c TA |
1274 | &clk_pcmcdclk0, |
1275 | &clk_pcmcdclk1, | |
1276 | &clk_pcmcdclk2, | |
0c1945d3 KK |
1277 | }; |
1278 | ||
0cfb26e1 TA |
1279 | static struct clk_lookup s5pv210_clk_lookup[] = { |
1280 | CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p), | |
1281 | CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk), | |
1282 | CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk), | |
1283 | CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk), | |
1284 | CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk), | |
1285 | }; | |
1286 | ||
0c1945d3 KK |
1287 | void __init s5pv210_register_clocks(void) |
1288 | { | |
0c1945d3 KK |
1289 | int ptr; |
1290 | ||
3c0fa647 | 1291 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
0c1945d3 | 1292 | |
eb1ef1ed TA |
1293 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) |
1294 | s3c_register_clksrc(sysclks[ptr], 1); | |
1295 | ||
fbf05563 TS |
1296 | for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) |
1297 | s3c_register_clksrc(sclk_tv[ptr], 1); | |
1298 | ||
0cfb26e1 TA |
1299 | for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) |
1300 | s3c_register_clksrc(clksrc_cdev[ptr], 1); | |
1301 | ||
0c1945d3 KK |
1302 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); |
1303 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | |
1304 | ||
3c0fa647 KK |
1305 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
1306 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | |
0cfb26e1 | 1307 | clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup)); |
0c1945d3 | 1308 | |
dafc9543 | 1309 | s3c24xx_register_clock(&dummy_apb_pclk); |
0c1945d3 KK |
1310 | s3c_pwmclk_init(); |
1311 | } |