Commit | Line | Data |
---|---|---|
0c1945d3 KK |
1 | /* linux/arch/arm/mach-s5pv210/clock.c |
2 | * | |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * S5PV210 - Clock support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/sysdev.h> | |
21 | #include <linux/io.h> | |
22 | ||
23 | #include <mach/map.h> | |
24 | ||
25 | #include <plat/cpu-freq.h> | |
26 | #include <mach/regs-clock.h> | |
27 | #include <plat/clock.h> | |
28 | #include <plat/cpu.h> | |
29 | #include <plat/pll.h> | |
30 | #include <plat/s5p-clock.h> | |
31 | #include <plat/clock-clksrc.h> | |
32 | #include <plat/s5pv210.h> | |
33 | ||
88695843 JL |
34 | static unsigned long xtal; |
35 | ||
59cda520 TA |
36 | static struct clksrc_clk clk_mout_apll = { |
37 | .clk = { | |
38 | .name = "mout_apll", | |
59cda520 TA |
39 | }, |
40 | .sources = &clk_src_apll, | |
41 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | |
42 | }; | |
43 | ||
44 | static struct clksrc_clk clk_mout_epll = { | |
45 | .clk = { | |
46 | .name = "mout_epll", | |
59cda520 TA |
47 | }, |
48 | .sources = &clk_src_epll, | |
49 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, | |
50 | }; | |
51 | ||
52 | static struct clksrc_clk clk_mout_mpll = { | |
53 | .clk = { | |
54 | .name = "mout_mpll", | |
59cda520 TA |
55 | }, |
56 | .sources = &clk_src_mpll, | |
57 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, | |
58 | }; | |
59 | ||
374e0bf5 TA |
60 | static struct clk *clkset_armclk_list[] = { |
61 | [0] = &clk_mout_apll.clk, | |
62 | [1] = &clk_mout_mpll.clk, | |
63 | }; | |
64 | ||
65 | static struct clksrc_sources clkset_armclk = { | |
66 | .sources = clkset_armclk_list, | |
67 | .nr_sources = ARRAY_SIZE(clkset_armclk_list), | |
68 | }; | |
69 | ||
70 | static struct clksrc_clk clk_armclk = { | |
71 | .clk = { | |
72 | .name = "armclk", | |
374e0bf5 TA |
73 | }, |
74 | .sources = &clkset_armclk, | |
75 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, | |
76 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, | |
77 | }; | |
78 | ||
af76a201 TA |
79 | static struct clksrc_clk clk_hclk_msys = { |
80 | .clk = { | |
81 | .name = "hclk_msys", | |
af76a201 TA |
82 | .parent = &clk_armclk.clk, |
83 | }, | |
84 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, | |
85 | }; | |
86 | ||
6ed91a20 TA |
87 | static struct clksrc_clk clk_pclk_msys = { |
88 | .clk = { | |
89 | .name = "pclk_msys", | |
6ed91a20 TA |
90 | .parent = &clk_hclk_msys.clk, |
91 | }, | |
92 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, | |
93 | }; | |
94 | ||
0fe967a1 TA |
95 | static struct clksrc_clk clk_sclk_a2m = { |
96 | .clk = { | |
97 | .name = "sclk_a2m", | |
0fe967a1 TA |
98 | .parent = &clk_mout_apll.clk, |
99 | }, | |
100 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, | |
101 | }; | |
102 | ||
103 | static struct clk *clkset_hclk_sys_list[] = { | |
104 | [0] = &clk_mout_mpll.clk, | |
105 | [1] = &clk_sclk_a2m.clk, | |
106 | }; | |
107 | ||
108 | static struct clksrc_sources clkset_hclk_sys = { | |
109 | .sources = clkset_hclk_sys_list, | |
110 | .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list), | |
111 | }; | |
112 | ||
113 | static struct clksrc_clk clk_hclk_dsys = { | |
114 | .clk = { | |
115 | .name = "hclk_dsys", | |
0fe967a1 TA |
116 | }, |
117 | .sources = &clkset_hclk_sys, | |
118 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, | |
119 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, | |
120 | }; | |
121 | ||
58772cd3 TA |
122 | static struct clksrc_clk clk_pclk_dsys = { |
123 | .clk = { | |
124 | .name = "pclk_dsys", | |
58772cd3 TA |
125 | .parent = &clk_hclk_dsys.clk, |
126 | }, | |
127 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, | |
128 | }; | |
129 | ||
acfa245f TA |
130 | static struct clksrc_clk clk_hclk_psys = { |
131 | .clk = { | |
132 | .name = "hclk_psys", | |
acfa245f TA |
133 | }, |
134 | .sources = &clkset_hclk_sys, | |
135 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, | |
136 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, | |
137 | }; | |
138 | ||
f44cf78b TA |
139 | static struct clksrc_clk clk_pclk_psys = { |
140 | .clk = { | |
141 | .name = "pclk_psys", | |
f44cf78b TA |
142 | .parent = &clk_hclk_psys.clk, |
143 | }, | |
144 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, | |
145 | }; | |
146 | ||
0c1945d3 KK |
147 | static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) |
148 | { | |
149 | return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); | |
150 | } | |
151 | ||
152 | static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable) | |
153 | { | |
154 | return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable); | |
155 | } | |
156 | ||
157 | static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable) | |
158 | { | |
159 | return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable); | |
160 | } | |
161 | ||
162 | static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable) | |
163 | { | |
164 | return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); | |
165 | } | |
166 | ||
f445dbd5 TA |
167 | static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) |
168 | { | |
169 | return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); | |
170 | } | |
171 | ||
154d62e4 MH |
172 | static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) |
173 | { | |
174 | return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); | |
175 | } | |
176 | ||
fbf05563 TS |
177 | static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) |
178 | { | |
179 | return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); | |
180 | } | |
181 | ||
182 | static int exynos4_clk_dac_ctrl(struct clk *clk, int enable) | |
183 | { | |
184 | return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable); | |
185 | } | |
186 | ||
f445dbd5 TA |
187 | static struct clk clk_sclk_hdmi27m = { |
188 | .name = "sclk_hdmi27m", | |
f445dbd5 TA |
189 | .rate = 27000000, |
190 | }; | |
191 | ||
2cf4c2e6 TA |
192 | static struct clk clk_sclk_hdmiphy = { |
193 | .name = "sclk_hdmiphy", | |
2cf4c2e6 TA |
194 | }; |
195 | ||
196 | static struct clk clk_sclk_usbphy0 = { | |
197 | .name = "sclk_usbphy0", | |
2cf4c2e6 TA |
198 | }; |
199 | ||
200 | static struct clk clk_sclk_usbphy1 = { | |
201 | .name = "sclk_usbphy1", | |
2cf4c2e6 TA |
202 | }; |
203 | ||
4583487c TA |
204 | static struct clk clk_pcmcdclk0 = { |
205 | .name = "pcmcdclk", | |
4583487c TA |
206 | }; |
207 | ||
208 | static struct clk clk_pcmcdclk1 = { | |
209 | .name = "pcmcdclk", | |
4583487c TA |
210 | }; |
211 | ||
212 | static struct clk clk_pcmcdclk2 = { | |
213 | .name = "pcmcdclk", | |
4583487c TA |
214 | }; |
215 | ||
dafc9543 BK |
216 | static struct clk dummy_apb_pclk = { |
217 | .name = "apb_pclk", | |
218 | .id = -1, | |
219 | }; | |
220 | ||
f445dbd5 TA |
221 | static struct clk *clkset_vpllsrc_list[] = { |
222 | [0] = &clk_fin_vpll, | |
223 | [1] = &clk_sclk_hdmi27m, | |
224 | }; | |
225 | ||
226 | static struct clksrc_sources clkset_vpllsrc = { | |
227 | .sources = clkset_vpllsrc_list, | |
228 | .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list), | |
229 | }; | |
230 | ||
231 | static struct clksrc_clk clk_vpllsrc = { | |
232 | .clk = { | |
233 | .name = "vpll_src", | |
f445dbd5 TA |
234 | .enable = s5pv210_clk_mask0_ctrl, |
235 | .ctrlbit = (1 << 7), | |
236 | }, | |
237 | .sources = &clkset_vpllsrc, | |
238 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 }, | |
239 | }; | |
240 | ||
241 | static struct clk *clkset_sclk_vpll_list[] = { | |
242 | [0] = &clk_vpllsrc.clk, | |
243 | [1] = &clk_fout_vpll, | |
244 | }; | |
245 | ||
246 | static struct clksrc_sources clkset_sclk_vpll = { | |
247 | .sources = clkset_sclk_vpll_list, | |
248 | .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), | |
249 | }; | |
250 | ||
251 | static struct clksrc_clk clk_sclk_vpll = { | |
252 | .clk = { | |
253 | .name = "sclk_vpll", | |
f445dbd5 TA |
254 | }, |
255 | .sources = &clkset_sclk_vpll, | |
256 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, | |
257 | }; | |
258 | ||
08f49d11 JL |
259 | static struct clk *clkset_moutdmc0src_list[] = { |
260 | [0] = &clk_sclk_a2m.clk, | |
261 | [1] = &clk_mout_mpll.clk, | |
262 | [2] = NULL, | |
263 | [3] = NULL, | |
264 | }; | |
265 | ||
266 | static struct clksrc_sources clkset_moutdmc0src = { | |
267 | .sources = clkset_moutdmc0src_list, | |
268 | .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list), | |
269 | }; | |
270 | ||
271 | static struct clksrc_clk clk_mout_dmc0 = { | |
272 | .clk = { | |
273 | .name = "mout_dmc0", | |
08f49d11 JL |
274 | }, |
275 | .sources = &clkset_moutdmc0src, | |
276 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, | |
277 | }; | |
278 | ||
279 | static struct clksrc_clk clk_sclk_dmc0 = { | |
280 | .clk = { | |
281 | .name = "sclk_dmc0", | |
08f49d11 JL |
282 | .parent = &clk_mout_dmc0.clk, |
283 | }, | |
284 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, | |
285 | }; | |
286 | ||
664f5b20 TA |
287 | static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk) |
288 | { | |
289 | return clk_get_rate(clk->parent) / 2; | |
290 | } | |
291 | ||
292 | static struct clk_ops clk_hclk_imem_ops = { | |
293 | .get_rate = s5pv210_clk_imem_get_rate, | |
294 | }; | |
295 | ||
88695843 JL |
296 | static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk) |
297 | { | |
298 | return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); | |
299 | } | |
300 | ||
301 | static struct clk_ops clk_fout_apll_ops = { | |
302 | .get_rate = s5pv210_clk_fout_apll_get_rate, | |
303 | }; | |
304 | ||
3c0fa647 | 305 | static struct clk init_clocks_off[] = { |
0c1945d3 | 306 | { |
dafc9543 | 307 | .name = "dma", |
1ce3ea61 | 308 | .devname = "dma-pl330.0", |
313068fd SY |
309 | .parent = &clk_hclk_psys.clk, |
310 | .enable = s5pv210_clk_ip0_ctrl, | |
311 | .ctrlbit = (1 << 3), | |
312 | }, { | |
dafc9543 | 313 | .name = "dma", |
1ce3ea61 | 314 | .devname = "dma-pl330.1", |
313068fd SY |
315 | .parent = &clk_hclk_psys.clk, |
316 | .enable = s5pv210_clk_ip0_ctrl, | |
317 | .ctrlbit = (1 << 4), | |
318 | }, { | |
0c1945d3 | 319 | .name = "rot", |
0fe967a1 | 320 | .parent = &clk_hclk_dsys.clk, |
0c1945d3 KK |
321 | .enable = s5pv210_clk_ip0_ctrl, |
322 | .ctrlbit = (1<<29), | |
da01c2f7 MS |
323 | }, { |
324 | .name = "fimc", | |
b2a9dd46 | 325 | .devname = "s5pv210-fimc.0", |
da01c2f7 MS |
326 | .parent = &clk_hclk_dsys.clk, |
327 | .enable = s5pv210_clk_ip0_ctrl, | |
328 | .ctrlbit = (1 << 24), | |
329 | }, { | |
330 | .name = "fimc", | |
b2a9dd46 | 331 | .devname = "s5pv210-fimc.1", |
da01c2f7 MS |
332 | .parent = &clk_hclk_dsys.clk, |
333 | .enable = s5pv210_clk_ip0_ctrl, | |
334 | .ctrlbit = (1 << 25), | |
335 | }, { | |
336 | .name = "fimc", | |
b2a9dd46 | 337 | .devname = "s5pv210-fimc.2", |
da01c2f7 MS |
338 | .parent = &clk_hclk_dsys.clk, |
339 | .enable = s5pv210_clk_ip0_ctrl, | |
340 | .ctrlbit = (1 << 26), | |
0f75a96b KD |
341 | }, { |
342 | .name = "mfc", | |
343 | .devname = "s5p-mfc", | |
344 | .parent = &clk_pclk_psys.clk, | |
345 | .enable = s5pv210_clk_ip0_ctrl, | |
346 | .ctrlbit = (1 << 16), | |
fbf05563 TS |
347 | }, { |
348 | .name = "dac", | |
349 | .devname = "s5p-sdo", | |
350 | .parent = &clk_hclk_dsys.clk, | |
351 | .enable = s5pv210_clk_ip1_ctrl, | |
352 | .ctrlbit = (1 << 10), | |
353 | }, { | |
354 | .name = "mixer", | |
355 | .devname = "s5p-mixer", | |
356 | .parent = &clk_hclk_dsys.clk, | |
357 | .enable = s5pv210_clk_ip1_ctrl, | |
358 | .ctrlbit = (1 << 9), | |
359 | }, { | |
360 | .name = "vp", | |
361 | .devname = "s5p-mixer", | |
362 | .parent = &clk_hclk_dsys.clk, | |
363 | .enable = s5pv210_clk_ip1_ctrl, | |
364 | .ctrlbit = (1 << 8), | |
365 | }, { | |
366 | .name = "hdmi", | |
367 | .devname = "s5pv210-hdmi", | |
368 | .parent = &clk_hclk_dsys.clk, | |
369 | .enable = s5pv210_clk_ip1_ctrl, | |
370 | .ctrlbit = (1 << 11), | |
371 | }, { | |
372 | .name = "hdmiphy", | |
373 | .devname = "s5pv210-hdmi", | |
374 | .enable = exynos4_clk_hdmiphy_ctrl, | |
375 | .ctrlbit = (1 << 0), | |
376 | }, { | |
377 | .name = "dacphy", | |
378 | .devname = "s5p-sdo", | |
379 | .enable = exynos4_clk_dac_ctrl, | |
380 | .ctrlbit = (1 << 0), | |
0c1945d3 KK |
381 | }, { |
382 | .name = "otg", | |
acfa245f | 383 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
384 | .enable = s5pv210_clk_ip1_ctrl, |
385 | .ctrlbit = (1<<16), | |
386 | }, { | |
387 | .name = "usb-host", | |
acfa245f | 388 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
389 | .enable = s5pv210_clk_ip1_ctrl, |
390 | .ctrlbit = (1<<17), | |
391 | }, { | |
392 | .name = "lcd", | |
0fe967a1 | 393 | .parent = &clk_hclk_dsys.clk, |
0c1945d3 KK |
394 | .enable = s5pv210_clk_ip1_ctrl, |
395 | .ctrlbit = (1<<0), | |
396 | }, { | |
397 | .name = "cfcon", | |
acfa245f | 398 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
399 | .enable = s5pv210_clk_ip1_ctrl, |
400 | .ctrlbit = (1<<25), | |
0c1945d3 KK |
401 | }, { |
402 | .name = "systimer", | |
f44cf78b | 403 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
404 | .enable = s5pv210_clk_ip3_ctrl, |
405 | .ctrlbit = (1<<16), | |
406 | }, { | |
407 | .name = "watchdog", | |
f44cf78b | 408 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
409 | .enable = s5pv210_clk_ip3_ctrl, |
410 | .ctrlbit = (1<<22), | |
411 | }, { | |
412 | .name = "rtc", | |
f44cf78b | 413 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
414 | .enable = s5pv210_clk_ip3_ctrl, |
415 | .ctrlbit = (1<<15), | |
416 | }, { | |
417 | .name = "i2c", | |
b2a9dd46 | 418 | .devname = "s3c2440-i2c.0", |
f44cf78b | 419 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
420 | .enable = s5pv210_clk_ip3_ctrl, |
421 | .ctrlbit = (1<<7), | |
422 | }, { | |
423 | .name = "i2c", | |
b2a9dd46 | 424 | .devname = "s3c2440-i2c.1", |
f44cf78b | 425 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 426 | .enable = s5pv210_clk_ip3_ctrl, |
f1c894de | 427 | .ctrlbit = (1 << 10), |
0c1945d3 KK |
428 | }, { |
429 | .name = "i2c", | |
b2a9dd46 | 430 | .devname = "s3c2440-i2c.2", |
f44cf78b | 431 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
432 | .enable = s5pv210_clk_ip3_ctrl, |
433 | .ctrlbit = (1<<9), | |
c40e7e0d TS |
434 | }, { |
435 | .name = "i2c", | |
436 | .devname = "s3c2440-hdmiphy-i2c", | |
437 | .parent = &clk_pclk_psys.clk, | |
438 | .enable = s5pv210_clk_ip3_ctrl, | |
439 | .ctrlbit = (1 << 11), | |
0c1945d3 KK |
440 | }, { |
441 | .name = "spi", | |
b2a9dd46 | 442 | .devname = "s3c64xx-spi.0", |
f44cf78b | 443 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
444 | .enable = s5pv210_clk_ip3_ctrl, |
445 | .ctrlbit = (1<<12), | |
446 | }, { | |
447 | .name = "spi", | |
b2a9dd46 | 448 | .devname = "s3c64xx-spi.1", |
f44cf78b | 449 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
450 | .enable = s5pv210_clk_ip3_ctrl, |
451 | .ctrlbit = (1<<13), | |
452 | }, { | |
453 | .name = "spi", | |
b2a9dd46 | 454 | .devname = "s3c64xx-spi.2", |
f44cf78b | 455 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
456 | .enable = s5pv210_clk_ip3_ctrl, |
457 | .ctrlbit = (1<<14), | |
458 | }, { | |
459 | .name = "timers", | |
f44cf78b | 460 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
461 | .enable = s5pv210_clk_ip3_ctrl, |
462 | .ctrlbit = (1<<23), | |
463 | }, { | |
464 | .name = "adc", | |
f44cf78b | 465 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
466 | .enable = s5pv210_clk_ip3_ctrl, |
467 | .ctrlbit = (1<<24), | |
468 | }, { | |
469 | .name = "keypad", | |
f44cf78b | 470 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
471 | .enable = s5pv210_clk_ip3_ctrl, |
472 | .ctrlbit = (1<<21), | |
473 | }, { | |
9aa2570e | 474 | .name = "iis", |
b2a9dd46 | 475 | .devname = "samsung-i2s.0", |
0c1945d3 KK |
476 | .parent = &clk_p, |
477 | .enable = s5pv210_clk_ip3_ctrl, | |
478 | .ctrlbit = (1<<4), | |
479 | }, { | |
9aa2570e | 480 | .name = "iis", |
b2a9dd46 | 481 | .devname = "samsung-i2s.1", |
0c1945d3 KK |
482 | .parent = &clk_p, |
483 | .enable = s5pv210_clk_ip3_ctrl, | |
154d62e4 | 484 | .ctrlbit = (1 << 5), |
0c1945d3 | 485 | }, { |
9aa2570e | 486 | .name = "iis", |
b2a9dd46 | 487 | .devname = "samsung-i2s.2", |
0c1945d3 KK |
488 | .parent = &clk_p, |
489 | .enable = s5pv210_clk_ip3_ctrl, | |
154d62e4 | 490 | .ctrlbit = (1 << 6), |
aa21ae3d SY |
491 | }, { |
492 | .name = "spdif", | |
aa21ae3d SY |
493 | .parent = &clk_p, |
494 | .enable = s5pv210_clk_ip3_ctrl, | |
495 | .ctrlbit = (1 << 0), | |
154d62e4 | 496 | }, |
0c1945d3 KK |
497 | }; |
498 | ||
499 | static struct clk init_clocks[] = { | |
500 | { | |
664f5b20 | 501 | .name = "hclk_imem", |
664f5b20 TA |
502 | .parent = &clk_hclk_msys.clk, |
503 | .ctrlbit = (1 << 5), | |
504 | .enable = s5pv210_clk_ip0_ctrl, | |
505 | .ops = &clk_hclk_imem_ops, | |
506 | }, { | |
0c1945d3 | 507 | .name = "uart", |
b2a9dd46 | 508 | .devname = "s5pv210-uart.0", |
f44cf78b | 509 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 510 | .enable = s5pv210_clk_ip3_ctrl, |
154d62e4 | 511 | .ctrlbit = (1 << 17), |
0c1945d3 KK |
512 | }, { |
513 | .name = "uart", | |
b2a9dd46 | 514 | .devname = "s5pv210-uart.1", |
f44cf78b | 515 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 516 | .enable = s5pv210_clk_ip3_ctrl, |
154d62e4 | 517 | .ctrlbit = (1 << 18), |
0c1945d3 KK |
518 | }, { |
519 | .name = "uart", | |
b2a9dd46 | 520 | .devname = "s5pv210-uart.2", |
f44cf78b | 521 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 522 | .enable = s5pv210_clk_ip3_ctrl, |
154d62e4 | 523 | .ctrlbit = (1 << 19), |
0c1945d3 KK |
524 | }, { |
525 | .name = "uart", | |
b2a9dd46 | 526 | .devname = "s5pv210-uart.3", |
f44cf78b | 527 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 528 | .enable = s5pv210_clk_ip3_ctrl, |
154d62e4 | 529 | .ctrlbit = (1 << 20), |
81f9becd TA |
530 | }, { |
531 | .name = "sromc", | |
81f9becd TA |
532 | .parent = &clk_hclk_psys.clk, |
533 | .enable = s5pv210_clk_ip1_ctrl, | |
534 | .ctrlbit = (1 << 26), | |
0c1945d3 KK |
535 | }, |
536 | }; | |
537 | ||
a361d10a RS |
538 | static struct clk clk_hsmmc0 = { |
539 | .name = "hsmmc", | |
540 | .devname = "s3c-sdhci.0", | |
541 | .parent = &clk_hclk_psys.clk, | |
542 | .enable = s5pv210_clk_ip2_ctrl, | |
543 | .ctrlbit = (1<<16), | |
544 | }; | |
545 | ||
546 | static struct clk clk_hsmmc1 = { | |
547 | .name = "hsmmc", | |
548 | .devname = "s3c-sdhci.1", | |
549 | .parent = &clk_hclk_psys.clk, | |
550 | .enable = s5pv210_clk_ip2_ctrl, | |
551 | .ctrlbit = (1<<17), | |
552 | }; | |
553 | ||
554 | static struct clk clk_hsmmc2 = { | |
555 | .name = "hsmmc", | |
556 | .devname = "s3c-sdhci.2", | |
557 | .parent = &clk_hclk_psys.clk, | |
558 | .enable = s5pv210_clk_ip2_ctrl, | |
559 | .ctrlbit = (1<<18), | |
560 | }; | |
561 | ||
562 | static struct clk clk_hsmmc3 = { | |
563 | .name = "hsmmc", | |
564 | .devname = "s3c-sdhci.3", | |
565 | .parent = &clk_hclk_psys.clk, | |
566 | .enable = s5pv210_clk_ip2_ctrl, | |
567 | .ctrlbit = (1<<19), | |
568 | }; | |
569 | ||
0c1945d3 KK |
570 | static struct clk *clkset_uart_list[] = { |
571 | [6] = &clk_mout_mpll.clk, | |
572 | [7] = &clk_mout_epll.clk, | |
573 | }; | |
574 | ||
575 | static struct clksrc_sources clkset_uart = { | |
576 | .sources = clkset_uart_list, | |
577 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | |
578 | }; | |
579 | ||
2cf4c2e6 TA |
580 | static struct clk *clkset_group1_list[] = { |
581 | [0] = &clk_sclk_a2m.clk, | |
582 | [1] = &clk_mout_mpll.clk, | |
583 | [2] = &clk_mout_epll.clk, | |
584 | [3] = &clk_sclk_vpll.clk, | |
585 | }; | |
586 | ||
587 | static struct clksrc_sources clkset_group1 = { | |
588 | .sources = clkset_group1_list, | |
589 | .nr_sources = ARRAY_SIZE(clkset_group1_list), | |
590 | }; | |
591 | ||
592 | static struct clk *clkset_sclk_onenand_list[] = { | |
593 | [0] = &clk_hclk_psys.clk, | |
594 | [1] = &clk_hclk_dsys.clk, | |
595 | }; | |
596 | ||
597 | static struct clksrc_sources clkset_sclk_onenand = { | |
598 | .sources = clkset_sclk_onenand_list, | |
599 | .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list), | |
600 | }; | |
601 | ||
9e20614b TA |
602 | static struct clk *clkset_sclk_dac_list[] = { |
603 | [0] = &clk_sclk_vpll.clk, | |
604 | [1] = &clk_sclk_hdmiphy, | |
605 | }; | |
606 | ||
607 | static struct clksrc_sources clkset_sclk_dac = { | |
608 | .sources = clkset_sclk_dac_list, | |
609 | .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list), | |
610 | }; | |
611 | ||
612 | static struct clksrc_clk clk_sclk_dac = { | |
613 | .clk = { | |
614 | .name = "sclk_dac", | |
154d62e4 MH |
615 | .enable = s5pv210_clk_mask0_ctrl, |
616 | .ctrlbit = (1 << 2), | |
9e20614b TA |
617 | }, |
618 | .sources = &clkset_sclk_dac, | |
619 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 }, | |
620 | }; | |
621 | ||
622 | static struct clksrc_clk clk_sclk_pixel = { | |
623 | .clk = { | |
624 | .name = "sclk_pixel", | |
9e20614b TA |
625 | .parent = &clk_sclk_vpll.clk, |
626 | }, | |
627 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, | |
628 | }; | |
629 | ||
630 | static struct clk *clkset_sclk_hdmi_list[] = { | |
631 | [0] = &clk_sclk_pixel.clk, | |
632 | [1] = &clk_sclk_hdmiphy, | |
633 | }; | |
634 | ||
635 | static struct clksrc_sources clkset_sclk_hdmi = { | |
636 | .sources = clkset_sclk_hdmi_list, | |
637 | .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list), | |
638 | }; | |
639 | ||
640 | static struct clksrc_clk clk_sclk_hdmi = { | |
641 | .clk = { | |
642 | .name = "sclk_hdmi", | |
154d62e4 MH |
643 | .enable = s5pv210_clk_mask0_ctrl, |
644 | .ctrlbit = (1 << 0), | |
9e20614b TA |
645 | }, |
646 | .sources = &clkset_sclk_hdmi, | |
647 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, | |
648 | }; | |
649 | ||
650 | static struct clk *clkset_sclk_mixer_list[] = { | |
651 | [0] = &clk_sclk_dac.clk, | |
652 | [1] = &clk_sclk_hdmi.clk, | |
653 | }; | |
654 | ||
655 | static struct clksrc_sources clkset_sclk_mixer = { | |
656 | .sources = clkset_sclk_mixer_list, | |
657 | .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), | |
658 | }; | |
659 | ||
fbf05563 TS |
660 | static struct clksrc_clk clk_sclk_mixer = { |
661 | .clk = { | |
662 | .name = "sclk_mixer", | |
663 | .enable = s5pv210_clk_mask0_ctrl, | |
664 | .ctrlbit = (1 << 1), | |
665 | }, | |
666 | .sources = &clkset_sclk_mixer, | |
667 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, | |
668 | }; | |
669 | ||
670 | static struct clksrc_clk *sclk_tv[] = { | |
671 | &clk_sclk_dac, | |
672 | &clk_sclk_pixel, | |
673 | &clk_sclk_hdmi, | |
674 | &clk_sclk_mixer, | |
675 | }; | |
676 | ||
4583487c TA |
677 | static struct clk *clkset_sclk_audio0_list[] = { |
678 | [0] = &clk_ext_xtal_mux, | |
679 | [1] = &clk_pcmcdclk0, | |
680 | [2] = &clk_sclk_hdmi27m, | |
681 | [3] = &clk_sclk_usbphy0, | |
682 | [4] = &clk_sclk_usbphy1, | |
683 | [5] = &clk_sclk_hdmiphy, | |
684 | [6] = &clk_mout_mpll.clk, | |
685 | [7] = &clk_mout_epll.clk, | |
686 | [8] = &clk_sclk_vpll.clk, | |
687 | }; | |
688 | ||
689 | static struct clksrc_sources clkset_sclk_audio0 = { | |
690 | .sources = clkset_sclk_audio0_list, | |
691 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list), | |
692 | }; | |
693 | ||
694 | static struct clksrc_clk clk_sclk_audio0 = { | |
695 | .clk = { | |
696 | .name = "sclk_audio", | |
b2a9dd46 | 697 | .devname = "soc-audio.0", |
154d62e4 MH |
698 | .enable = s5pv210_clk_mask0_ctrl, |
699 | .ctrlbit = (1 << 24), | |
4583487c TA |
700 | }, |
701 | .sources = &clkset_sclk_audio0, | |
702 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 }, | |
703 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 }, | |
704 | }; | |
705 | ||
706 | static struct clk *clkset_sclk_audio1_list[] = { | |
707 | [0] = &clk_ext_xtal_mux, | |
708 | [1] = &clk_pcmcdclk1, | |
709 | [2] = &clk_sclk_hdmi27m, | |
710 | [3] = &clk_sclk_usbphy0, | |
711 | [4] = &clk_sclk_usbphy1, | |
712 | [5] = &clk_sclk_hdmiphy, | |
713 | [6] = &clk_mout_mpll.clk, | |
714 | [7] = &clk_mout_epll.clk, | |
715 | [8] = &clk_sclk_vpll.clk, | |
716 | }; | |
717 | ||
718 | static struct clksrc_sources clkset_sclk_audio1 = { | |
719 | .sources = clkset_sclk_audio1_list, | |
720 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list), | |
721 | }; | |
722 | ||
723 | static struct clksrc_clk clk_sclk_audio1 = { | |
724 | .clk = { | |
725 | .name = "sclk_audio", | |
b2a9dd46 | 726 | .devname = "soc-audio.1", |
154d62e4 MH |
727 | .enable = s5pv210_clk_mask0_ctrl, |
728 | .ctrlbit = (1 << 25), | |
4583487c TA |
729 | }, |
730 | .sources = &clkset_sclk_audio1, | |
731 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 }, | |
732 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 }, | |
733 | }; | |
734 | ||
735 | static struct clk *clkset_sclk_audio2_list[] = { | |
736 | [0] = &clk_ext_xtal_mux, | |
737 | [1] = &clk_pcmcdclk0, | |
738 | [2] = &clk_sclk_hdmi27m, | |
739 | [3] = &clk_sclk_usbphy0, | |
740 | [4] = &clk_sclk_usbphy1, | |
741 | [5] = &clk_sclk_hdmiphy, | |
742 | [6] = &clk_mout_mpll.clk, | |
743 | [7] = &clk_mout_epll.clk, | |
744 | [8] = &clk_sclk_vpll.clk, | |
745 | }; | |
746 | ||
747 | static struct clksrc_sources clkset_sclk_audio2 = { | |
748 | .sources = clkset_sclk_audio2_list, | |
749 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list), | |
750 | }; | |
751 | ||
752 | static struct clksrc_clk clk_sclk_audio2 = { | |
753 | .clk = { | |
754 | .name = "sclk_audio", | |
b2a9dd46 | 755 | .devname = "soc-audio.2", |
154d62e4 MH |
756 | .enable = s5pv210_clk_mask0_ctrl, |
757 | .ctrlbit = (1 << 26), | |
4583487c TA |
758 | }, |
759 | .sources = &clkset_sclk_audio2, | |
760 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 }, | |
761 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 }, | |
762 | }; | |
763 | ||
764 | static struct clk *clkset_sclk_spdif_list[] = { | |
765 | [0] = &clk_sclk_audio0.clk, | |
766 | [1] = &clk_sclk_audio1.clk, | |
767 | [2] = &clk_sclk_audio2.clk, | |
768 | }; | |
769 | ||
770 | static struct clksrc_sources clkset_sclk_spdif = { | |
771 | .sources = clkset_sclk_spdif_list, | |
772 | .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), | |
773 | }; | |
774 | ||
aa21ae3d SY |
775 | static struct clksrc_clk clk_sclk_spdif = { |
776 | .clk = { | |
777 | .name = "sclk_spdif", | |
aa21ae3d SY |
778 | .enable = s5pv210_clk_mask0_ctrl, |
779 | .ctrlbit = (1 << 27), | |
65f5eaa2 | 780 | .ops = &s5p_sclk_spdif_ops, |
aa21ae3d SY |
781 | }, |
782 | .sources = &clkset_sclk_spdif, | |
783 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, | |
784 | }; | |
785 | ||
f64cacc3 TA |
786 | static struct clk *clkset_group2_list[] = { |
787 | [0] = &clk_ext_xtal_mux, | |
788 | [1] = &clk_xusbxti, | |
789 | [2] = &clk_sclk_hdmi27m, | |
790 | [3] = &clk_sclk_usbphy0, | |
791 | [4] = &clk_sclk_usbphy1, | |
792 | [5] = &clk_sclk_hdmiphy, | |
793 | [6] = &clk_mout_mpll.clk, | |
794 | [7] = &clk_mout_epll.clk, | |
795 | [8] = &clk_sclk_vpll.clk, | |
796 | }; | |
797 | ||
798 | static struct clksrc_sources clkset_group2 = { | |
799 | .sources = clkset_group2_list, | |
800 | .nr_sources = ARRAY_SIZE(clkset_group2_list), | |
801 | }; | |
802 | ||
0c1945d3 KK |
803 | static struct clksrc_clk clksrcs[] = { |
804 | { | |
2cf4c2e6 TA |
805 | .clk = { |
806 | .name = "sclk_dmc", | |
2cf4c2e6 TA |
807 | }, |
808 | .sources = &clkset_group1, | |
809 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, | |
810 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, | |
811 | }, { | |
812 | .clk = { | |
813 | .name = "sclk_onenand", | |
2cf4c2e6 TA |
814 | }, |
815 | .sources = &clkset_sclk_onenand, | |
816 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, | |
817 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, | |
f64cacc3 TA |
818 | }, { |
819 | .clk = { | |
820 | .name = "sclk_fimc", | |
b2a9dd46 | 821 | .devname = "s5pv210-fimc.0", |
154d62e4 MH |
822 | .enable = s5pv210_clk_mask1_ctrl, |
823 | .ctrlbit = (1 << 2), | |
f64cacc3 TA |
824 | }, |
825 | .sources = &clkset_group2, | |
826 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 }, | |
827 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, | |
828 | }, { | |
829 | .clk = { | |
830 | .name = "sclk_fimc", | |
b2a9dd46 | 831 | .devname = "s5pv210-fimc.1", |
154d62e4 MH |
832 | .enable = s5pv210_clk_mask1_ctrl, |
833 | .ctrlbit = (1 << 3), | |
f64cacc3 TA |
834 | }, |
835 | .sources = &clkset_group2, | |
836 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 }, | |
837 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 }, | |
838 | }, { | |
839 | .clk = { | |
840 | .name = "sclk_fimc", | |
b2a9dd46 | 841 | .devname = "s5pv210-fimc.2", |
154d62e4 MH |
842 | .enable = s5pv210_clk_mask1_ctrl, |
843 | .ctrlbit = (1 << 4), | |
f64cacc3 TA |
844 | }, |
845 | .sources = &clkset_group2, | |
846 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 }, | |
847 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, | |
848 | }, { | |
849 | .clk = { | |
83427c23 | 850 | .name = "sclk_cam0", |
154d62e4 MH |
851 | .enable = s5pv210_clk_mask0_ctrl, |
852 | .ctrlbit = (1 << 3), | |
f64cacc3 TA |
853 | }, |
854 | .sources = &clkset_group2, | |
855 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 }, | |
856 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, | |
857 | }, { | |
858 | .clk = { | |
83427c23 | 859 | .name = "sclk_cam1", |
154d62e4 MH |
860 | .enable = s5pv210_clk_mask0_ctrl, |
861 | .ctrlbit = (1 << 4), | |
f64cacc3 TA |
862 | }, |
863 | .sources = &clkset_group2, | |
864 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 }, | |
865 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 }, | |
866 | }, { | |
867 | .clk = { | |
868 | .name = "sclk_fimd", | |
154d62e4 MH |
869 | .enable = s5pv210_clk_mask0_ctrl, |
870 | .ctrlbit = (1 << 5), | |
f64cacc3 TA |
871 | }, |
872 | .sources = &clkset_group2, | |
873 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 }, | |
874 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, | |
f64cacc3 TA |
875 | }, { |
876 | .clk = { | |
877 | .name = "sclk_mfc", | |
0f75a96b | 878 | .devname = "s5p-mfc", |
f64cacc3 TA |
879 | .enable = s5pv210_clk_ip0_ctrl, |
880 | .ctrlbit = (1 << 16), | |
881 | }, | |
882 | .sources = &clkset_group1, | |
883 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, | |
884 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, | |
885 | }, { | |
886 | .clk = { | |
887 | .name = "sclk_g2d", | |
f64cacc3 TA |
888 | .enable = s5pv210_clk_ip0_ctrl, |
889 | .ctrlbit = (1 << 12), | |
890 | }, | |
891 | .sources = &clkset_group1, | |
892 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, | |
893 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, | |
894 | }, { | |
895 | .clk = { | |
896 | .name = "sclk_g3d", | |
f64cacc3 TA |
897 | .enable = s5pv210_clk_ip0_ctrl, |
898 | .ctrlbit = (1 << 8), | |
899 | }, | |
900 | .sources = &clkset_group1, | |
901 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, | |
902 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, | |
903 | }, { | |
904 | .clk = { | |
905 | .name = "sclk_csis", | |
154d62e4 MH |
906 | .enable = s5pv210_clk_mask0_ctrl, |
907 | .ctrlbit = (1 << 6), | |
f64cacc3 TA |
908 | }, |
909 | .sources = &clkset_group2, | |
910 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, | |
911 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, | |
912 | }, { | |
913 | .clk = { | |
914 | .name = "sclk_spi", | |
b2a9dd46 | 915 | .devname = "s3c64xx-spi.0", |
154d62e4 MH |
916 | .enable = s5pv210_clk_mask0_ctrl, |
917 | .ctrlbit = (1 << 16), | |
f64cacc3 TA |
918 | }, |
919 | .sources = &clkset_group2, | |
920 | .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, | |
921 | .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 }, | |
922 | }, { | |
923 | .clk = { | |
924 | .name = "sclk_spi", | |
b2a9dd46 | 925 | .devname = "s3c64xx-spi.1", |
154d62e4 MH |
926 | .enable = s5pv210_clk_mask0_ctrl, |
927 | .ctrlbit = (1 << 17), | |
f64cacc3 TA |
928 | }, |
929 | .sources = &clkset_group2, | |
930 | .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, | |
931 | .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 }, | |
932 | }, { | |
933 | .clk = { | |
934 | .name = "sclk_pwi", | |
154d62e4 MH |
935 | .enable = s5pv210_clk_mask0_ctrl, |
936 | .ctrlbit = (1 << 29), | |
f64cacc3 TA |
937 | }, |
938 | .sources = &clkset_group2, | |
939 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 }, | |
940 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 }, | |
941 | }, { | |
942 | .clk = { | |
943 | .name = "sclk_pwm", | |
154d62e4 MH |
944 | .enable = s5pv210_clk_mask0_ctrl, |
945 | .ctrlbit = (1 << 19), | |
f64cacc3 TA |
946 | }, |
947 | .sources = &clkset_group2, | |
948 | .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 }, | |
949 | .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 }, | |
9e20614b | 950 | }, |
0c1945d3 KK |
951 | }; |
952 | ||
0cfb26e1 TA |
953 | static struct clksrc_clk clk_sclk_uart0 = { |
954 | .clk = { | |
955 | .name = "uclk1", | |
956 | .devname = "s5pv210-uart.0", | |
957 | .enable = s5pv210_clk_mask0_ctrl, | |
958 | .ctrlbit = (1 << 12), | |
959 | }, | |
960 | .sources = &clkset_uart, | |
961 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, | |
962 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, | |
963 | }; | |
964 | ||
965 | static struct clksrc_clk clk_sclk_uart1 = { | |
966 | .clk = { | |
967 | .name = "uclk1", | |
968 | .devname = "s5pv210-uart.1", | |
969 | .enable = s5pv210_clk_mask0_ctrl, | |
970 | .ctrlbit = (1 << 13), | |
971 | }, | |
972 | .sources = &clkset_uart, | |
973 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, | |
974 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, | |
975 | }; | |
976 | ||
977 | static struct clksrc_clk clk_sclk_uart2 = { | |
978 | .clk = { | |
979 | .name = "uclk1", | |
980 | .devname = "s5pv210-uart.2", | |
981 | .enable = s5pv210_clk_mask0_ctrl, | |
982 | .ctrlbit = (1 << 14), | |
983 | }, | |
984 | .sources = &clkset_uart, | |
985 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, | |
986 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 }, | |
987 | }; | |
988 | ||
989 | static struct clksrc_clk clk_sclk_uart3 = { | |
990 | .clk = { | |
991 | .name = "uclk1", | |
992 | .devname = "s5pv210-uart.3", | |
993 | .enable = s5pv210_clk_mask0_ctrl, | |
994 | .ctrlbit = (1 << 15), | |
995 | }, | |
996 | .sources = &clkset_uart, | |
997 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, | |
998 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, | |
999 | }; | |
1000 | ||
a361d10a RS |
1001 | static struct clksrc_clk clk_sclk_mmc0 = { |
1002 | .clk = { | |
1003 | .name = "sclk_mmc", | |
1004 | .devname = "s3c-sdhci.0", | |
1005 | .enable = s5pv210_clk_mask0_ctrl, | |
1006 | .ctrlbit = (1 << 8), | |
1007 | }, | |
1008 | .sources = &clkset_group2, | |
1009 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, | |
1010 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, | |
1011 | }; | |
1012 | ||
1013 | static struct clksrc_clk clk_sclk_mmc1 = { | |
1014 | .clk = { | |
1015 | .name = "sclk_mmc", | |
1016 | .devname = "s3c-sdhci.1", | |
1017 | .enable = s5pv210_clk_mask0_ctrl, | |
1018 | .ctrlbit = (1 << 9), | |
1019 | }, | |
1020 | .sources = &clkset_group2, | |
1021 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, | |
1022 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, | |
1023 | }; | |
1024 | ||
1025 | static struct clksrc_clk clk_sclk_mmc2 = { | |
1026 | .clk = { | |
1027 | .name = "sclk_mmc", | |
1028 | .devname = "s3c-sdhci.2", | |
1029 | .enable = s5pv210_clk_mask0_ctrl, | |
1030 | .ctrlbit = (1 << 10), | |
1031 | }, | |
1032 | .sources = &clkset_group2, | |
1033 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, | |
1034 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, | |
1035 | }; | |
1036 | ||
1037 | static struct clksrc_clk clk_sclk_mmc3 = { | |
1038 | .clk = { | |
1039 | .name = "sclk_mmc", | |
1040 | .devname = "s3c-sdhci.3", | |
1041 | .enable = s5pv210_clk_mask0_ctrl, | |
1042 | .ctrlbit = (1 << 11), | |
1043 | }, | |
1044 | .sources = &clkset_group2, | |
1045 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, | |
1046 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, | |
1047 | }; | |
1048 | ||
0cfb26e1 TA |
1049 | static struct clksrc_clk *clksrc_cdev[] = { |
1050 | &clk_sclk_uart0, | |
1051 | &clk_sclk_uart1, | |
1052 | &clk_sclk_uart2, | |
1053 | &clk_sclk_uart3, | |
a361d10a RS |
1054 | &clk_sclk_mmc0, |
1055 | &clk_sclk_mmc1, | |
1056 | &clk_sclk_mmc2, | |
1057 | &clk_sclk_mmc3, | |
1058 | }; | |
1059 | ||
1060 | static struct clk *clk_cdev[] = { | |
1061 | &clk_hsmmc0, | |
1062 | &clk_hsmmc1, | |
1063 | &clk_hsmmc2, | |
1064 | &clk_hsmmc3, | |
0cfb26e1 TA |
1065 | }; |
1066 | ||
0c1945d3 | 1067 | /* Clock initialisation code */ |
eb1ef1ed | 1068 | static struct clksrc_clk *sysclks[] = { |
0c1945d3 KK |
1069 | &clk_mout_apll, |
1070 | &clk_mout_epll, | |
1071 | &clk_mout_mpll, | |
374e0bf5 | 1072 | &clk_armclk, |
af76a201 | 1073 | &clk_hclk_msys, |
0fe967a1 TA |
1074 | &clk_sclk_a2m, |
1075 | &clk_hclk_dsys, | |
acfa245f | 1076 | &clk_hclk_psys, |
6ed91a20 | 1077 | &clk_pclk_msys, |
58772cd3 | 1078 | &clk_pclk_dsys, |
f44cf78b | 1079 | &clk_pclk_psys, |
f445dbd5 TA |
1080 | &clk_vpllsrc, |
1081 | &clk_sclk_vpll, | |
08f49d11 JL |
1082 | &clk_mout_dmc0, |
1083 | &clk_sclk_dmc0, | |
900fa019 SY |
1084 | &clk_sclk_audio0, |
1085 | &clk_sclk_audio1, | |
1086 | &clk_sclk_audio2, | |
1087 | &clk_sclk_spdif, | |
0c1945d3 KK |
1088 | }; |
1089 | ||
c9fa7a08 SY |
1090 | static u32 epll_div[][6] = { |
1091 | { 48000000, 0, 48, 3, 3, 0 }, | |
1092 | { 96000000, 0, 48, 3, 2, 0 }, | |
1093 | { 144000000, 1, 72, 3, 2, 0 }, | |
1094 | { 192000000, 0, 48, 3, 1, 0 }, | |
1095 | { 288000000, 1, 72, 3, 1, 0 }, | |
1096 | { 32750000, 1, 65, 3, 4, 35127 }, | |
1097 | { 32768000, 1, 65, 3, 4, 35127 }, | |
1098 | { 45158400, 0, 45, 3, 3, 10355 }, | |
1099 | { 45000000, 0, 45, 3, 3, 10355 }, | |
1100 | { 45158000, 0, 45, 3, 3, 10355 }, | |
1101 | { 49125000, 0, 49, 3, 3, 9961 }, | |
1102 | { 49152000, 0, 49, 3, 3, 9961 }, | |
1103 | { 67737600, 1, 67, 3, 3, 48366 }, | |
1104 | { 67738000, 1, 67, 3, 3, 48366 }, | |
1105 | { 73800000, 1, 73, 3, 3, 47710 }, | |
1106 | { 73728000, 1, 73, 3, 3, 47710 }, | |
1107 | { 36000000, 1, 32, 3, 4, 0 }, | |
1108 | { 60000000, 1, 60, 3, 3, 0 }, | |
1109 | { 72000000, 1, 72, 3, 3, 0 }, | |
1110 | { 80000000, 1, 80, 3, 3, 0 }, | |
1111 | { 84000000, 0, 42, 3, 2, 0 }, | |
1112 | { 50000000, 0, 50, 3, 3, 0 }, | |
1113 | }; | |
1114 | ||
1115 | static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate) | |
1116 | { | |
1117 | unsigned int epll_con, epll_con_k; | |
1118 | unsigned int i; | |
1119 | ||
1120 | /* Return if nothing changed */ | |
1121 | if (clk->rate == rate) | |
1122 | return 0; | |
1123 | ||
1124 | epll_con = __raw_readl(S5P_EPLL_CON); | |
1125 | epll_con_k = __raw_readl(S5P_EPLL_CON1); | |
1126 | ||
1127 | epll_con_k &= ~PLL46XX_KDIV_MASK; | |
1128 | epll_con &= ~(1 << 27 | | |
1129 | PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | | |
1130 | PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | | |
1131 | PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); | |
1132 | ||
1133 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { | |
1134 | if (epll_div[i][0] == rate) { | |
1135 | epll_con_k |= epll_div[i][5] << 0; | |
1136 | epll_con |= (epll_div[i][1] << 27 | | |
1137 | epll_div[i][2] << PLL46XX_MDIV_SHIFT | | |
1138 | epll_div[i][3] << PLL46XX_PDIV_SHIFT | | |
1139 | epll_div[i][4] << PLL46XX_SDIV_SHIFT); | |
1140 | break; | |
1141 | } | |
1142 | } | |
1143 | ||
1144 | if (i == ARRAY_SIZE(epll_div)) { | |
1145 | printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", | |
1146 | __func__); | |
1147 | return -EINVAL; | |
1148 | } | |
1149 | ||
1150 | __raw_writel(epll_con, S5P_EPLL_CON); | |
1151 | __raw_writel(epll_con_k, S5P_EPLL_CON1); | |
1152 | ||
9616674a SY |
1153 | printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", |
1154 | clk->rate, rate); | |
1155 | ||
c9fa7a08 SY |
1156 | clk->rate = rate; |
1157 | ||
1158 | return 0; | |
1159 | } | |
1160 | ||
1161 | static struct clk_ops s5pv210_epll_ops = { | |
1162 | .set_rate = s5pv210_epll_set_rate, | |
1163 | .get_rate = s5p_epll_get_rate, | |
1164 | }; | |
1165 | ||
fbf05563 TS |
1166 | static u32 vpll_div[][5] = { |
1167 | { 54000000, 3, 53, 3, 0 }, | |
1168 | { 108000000, 3, 53, 2, 0 }, | |
1169 | }; | |
1170 | ||
1171 | static unsigned long s5pv210_vpll_get_rate(struct clk *clk) | |
1172 | { | |
1173 | return clk->rate; | |
1174 | } | |
1175 | ||
1176 | static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate) | |
1177 | { | |
1178 | unsigned int vpll_con; | |
1179 | unsigned int i; | |
1180 | ||
1181 | /* Return if nothing changed */ | |
1182 | if (clk->rate == rate) | |
1183 | return 0; | |
1184 | ||
1185 | vpll_con = __raw_readl(S5P_VPLL_CON); | |
1186 | vpll_con &= ~(0x1 << 27 | \ | |
1187 | PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT | \ | |
1188 | PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT | \ | |
1189 | PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT); | |
1190 | ||
1191 | for (i = 0; i < ARRAY_SIZE(vpll_div); i++) { | |
1192 | if (vpll_div[i][0] == rate) { | |
1193 | vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT; | |
1194 | vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT; | |
1195 | vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT; | |
1196 | vpll_con |= vpll_div[i][4] << 27; | |
1197 | break; | |
1198 | } | |
1199 | } | |
1200 | ||
1201 | if (i == ARRAY_SIZE(vpll_div)) { | |
1202 | printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", | |
1203 | __func__); | |
1204 | return -EINVAL; | |
1205 | } | |
1206 | ||
1207 | __raw_writel(vpll_con, S5P_VPLL_CON); | |
1208 | ||
1209 | /* Wait for VPLL lock */ | |
1210 | while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT))) | |
1211 | continue; | |
1212 | ||
1213 | clk->rate = rate; | |
1214 | return 0; | |
1215 | } | |
1216 | static struct clk_ops s5pv210_vpll_ops = { | |
1217 | .get_rate = s5pv210_vpll_get_rate, | |
1218 | .set_rate = s5pv210_vpll_set_rate, | |
1219 | }; | |
1220 | ||
0c1945d3 KK |
1221 | void __init_or_cpufreq s5pv210_setup_clocks(void) |
1222 | { | |
1223 | struct clk *xtal_clk; | |
f445dbd5 | 1224 | unsigned long vpllsrc; |
0c1945d3 | 1225 | unsigned long armclk; |
af76a201 | 1226 | unsigned long hclk_msys; |
0fe967a1 | 1227 | unsigned long hclk_dsys; |
acfa245f | 1228 | unsigned long hclk_psys; |
6ed91a20 | 1229 | unsigned long pclk_msys; |
58772cd3 | 1230 | unsigned long pclk_dsys; |
f44cf78b | 1231 | unsigned long pclk_psys; |
0c1945d3 KK |
1232 | unsigned long apll; |
1233 | unsigned long mpll; | |
1234 | unsigned long epll; | |
f445dbd5 | 1235 | unsigned long vpll; |
0c1945d3 KK |
1236 | unsigned int ptr; |
1237 | u32 clkdiv0, clkdiv1; | |
1238 | ||
c9fa7a08 SY |
1239 | /* Set functions for clk_fout_epll */ |
1240 | clk_fout_epll.enable = s5p_epll_enable; | |
1241 | clk_fout_epll.ops = &s5pv210_epll_ops; | |
1242 | ||
0c1945d3 KK |
1243 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); |
1244 | ||
1245 | clkdiv0 = __raw_readl(S5P_CLK_DIV0); | |
1246 | clkdiv1 = __raw_readl(S5P_CLK_DIV1); | |
1247 | ||
1248 | printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", | |
1249 | __func__, clkdiv0, clkdiv1); | |
1250 | ||
1251 | xtal_clk = clk_get(NULL, "xtal"); | |
1252 | BUG_ON(IS_ERR(xtal_clk)); | |
1253 | ||
1254 | xtal = clk_get_rate(xtal_clk); | |
1255 | clk_put(xtal_clk); | |
1256 | ||
1257 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | |
1258 | ||
1259 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); | |
1260 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); | |
42a6e20e SY |
1261 | epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON), |
1262 | __raw_readl(S5P_EPLL_CON1), pll_4600); | |
f445dbd5 TA |
1263 | vpllsrc = clk_get_rate(&clk_vpllsrc.clk); |
1264 | vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); | |
0c1945d3 | 1265 | |
88695843 | 1266 | clk_fout_apll.ops = &clk_fout_apll_ops; |
c62ec6a9 TA |
1267 | clk_fout_mpll.rate = mpll; |
1268 | clk_fout_epll.rate = epll; | |
fbf05563 | 1269 | clk_fout_vpll.ops = &s5pv210_vpll_ops; |
f445dbd5 | 1270 | clk_fout_vpll.rate = vpll; |
c62ec6a9 | 1271 | |
f445dbd5 TA |
1272 | printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", |
1273 | apll, mpll, epll, vpll); | |
0c1945d3 | 1274 | |
374e0bf5 | 1275 | armclk = clk_get_rate(&clk_armclk.clk); |
af76a201 | 1276 | hclk_msys = clk_get_rate(&clk_hclk_msys.clk); |
0fe967a1 | 1277 | hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk); |
acfa245f | 1278 | hclk_psys = clk_get_rate(&clk_hclk_psys.clk); |
6ed91a20 | 1279 | pclk_msys = clk_get_rate(&clk_pclk_msys.clk); |
58772cd3 | 1280 | pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk); |
f44cf78b | 1281 | pclk_psys = clk_get_rate(&clk_pclk_psys.clk); |
0c1945d3 | 1282 | |
acfa245f TA |
1283 | printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n" |
1284 | "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", | |
1285 | armclk, hclk_msys, hclk_dsys, hclk_psys, | |
f44cf78b | 1286 | pclk_msys, pclk_dsys, pclk_psys); |
0c1945d3 | 1287 | |
0c1945d3 | 1288 | clk_f.rate = armclk; |
acfa245f | 1289 | clk_h.rate = hclk_psys; |
f44cf78b | 1290 | clk_p.rate = pclk_psys; |
0c1945d3 | 1291 | |
0c1945d3 KK |
1292 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) |
1293 | s3c_set_clksrc(&clksrcs[ptr], true); | |
1294 | } | |
1295 | ||
1296 | static struct clk *clks[] __initdata = { | |
f445dbd5 | 1297 | &clk_sclk_hdmi27m, |
2cf4c2e6 TA |
1298 | &clk_sclk_hdmiphy, |
1299 | &clk_sclk_usbphy0, | |
1300 | &clk_sclk_usbphy1, | |
4583487c TA |
1301 | &clk_pcmcdclk0, |
1302 | &clk_pcmcdclk1, | |
1303 | &clk_pcmcdclk2, | |
0c1945d3 KK |
1304 | }; |
1305 | ||
0cfb26e1 TA |
1306 | static struct clk_lookup s5pv210_clk_lookup[] = { |
1307 | CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p), | |
1308 | CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk), | |
1309 | CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk), | |
1310 | CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk), | |
1311 | CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk), | |
a361d10a RS |
1312 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), |
1313 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), | |
1314 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), | |
1315 | CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3), | |
1316 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), | |
1317 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), | |
1318 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), | |
1319 | CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), | |
0cfb26e1 TA |
1320 | }; |
1321 | ||
0c1945d3 KK |
1322 | void __init s5pv210_register_clocks(void) |
1323 | { | |
0c1945d3 KK |
1324 | int ptr; |
1325 | ||
3c0fa647 | 1326 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
0c1945d3 | 1327 | |
eb1ef1ed TA |
1328 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) |
1329 | s3c_register_clksrc(sysclks[ptr], 1); | |
1330 | ||
fbf05563 TS |
1331 | for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) |
1332 | s3c_register_clksrc(sclk_tv[ptr], 1); | |
1333 | ||
0cfb26e1 TA |
1334 | for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) |
1335 | s3c_register_clksrc(clksrc_cdev[ptr], 1); | |
1336 | ||
0c1945d3 KK |
1337 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); |
1338 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | |
1339 | ||
3c0fa647 KK |
1340 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
1341 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | |
0cfb26e1 | 1342 | clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup)); |
0c1945d3 | 1343 | |
a361d10a RS |
1344 | s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); |
1345 | for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) | |
1346 | s3c_disable_clocks(clk_cdev[ptr], 1); | |
1347 | ||
dafc9543 | 1348 | s3c24xx_register_clock(&dummy_apb_pclk); |
0c1945d3 KK |
1349 | s3c_pwmclk_init(); |
1350 | } |