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dafc9543 BK |
1 | /* linux/arch/arm/mach-s5pv210/dma.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
7d1a2077 JB |
6 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. |
7 | * Jaswinder Singh <jassi.brar@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
7d1a2077 | 24 | #include <linux/dma-mapping.h> |
dafc9543 BK |
25 | #include <linux/amba/bus.h> |
26 | #include <linux/amba/pl330.h> | |
7d1a2077 | 27 | |
dafc9543 | 28 | #include <asm/irq.h> |
7d1a2077 JB |
29 | #include <plat/devs.h> |
30 | #include <plat/irqs.h> | |
31 | ||
32 | #include <mach/map.h> | |
33 | #include <mach/irqs.h> | |
dafc9543 | 34 | #include <mach/dma.h> |
7d1a2077 JB |
35 | |
36 | static u64 dma_dmamask = DMA_BIT_MASK(32); | |
37 | ||
8742e044 TA |
38 | u8 pdma0_peri[] = { |
39 | DMACH_UART0_RX, | |
40 | DMACH_UART0_TX, | |
41 | DMACH_UART1_RX, | |
42 | DMACH_UART1_TX, | |
43 | DMACH_UART2_RX, | |
44 | DMACH_UART2_TX, | |
45 | DMACH_UART3_RX, | |
46 | DMACH_UART3_TX, | |
47 | DMACH_MAX, | |
48 | DMACH_I2S0_RX, | |
49 | DMACH_I2S0_TX, | |
50 | DMACH_I2S0S_TX, | |
51 | DMACH_I2S1_RX, | |
52 | DMACH_I2S1_TX, | |
53 | DMACH_MAX, | |
54 | DMACH_MAX, | |
55 | DMACH_SPI0_RX, | |
56 | DMACH_SPI0_TX, | |
57 | DMACH_SPI1_RX, | |
58 | DMACH_SPI1_TX, | |
59 | DMACH_MAX, | |
60 | DMACH_MAX, | |
61 | DMACH_AC97_MICIN, | |
62 | DMACH_AC97_PCMIN, | |
63 | DMACH_AC97_PCMOUT, | |
64 | DMACH_MAX, | |
65 | DMACH_PWM, | |
66 | DMACH_SPDIF, | |
7d1a2077 JB |
67 | }; |
68 | ||
dafc9543 BK |
69 | struct dma_pl330_platdata s5pv210_pdma0_pdata = { |
70 | .nr_valid_peri = ARRAY_SIZE(pdma0_peri), | |
8742e044 | 71 | .peri_id = pdma0_peri, |
7d1a2077 JB |
72 | }; |
73 | ||
dafc9543 BK |
74 | struct amba_device s5pv210_device_pdma0 = { |
75 | .dev = { | |
76 | .init_name = "dma-pl330.0", | |
7d1a2077 JB |
77 | .dma_mask = &dma_dmamask, |
78 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
79 | .platform_data = &s5pv210_pdma0_pdata, | |
80 | }, | |
dafc9543 BK |
81 | .res = { |
82 | .start = S5PV210_PA_PDMA0, | |
83 | .end = S5PV210_PA_PDMA0 + SZ_4K, | |
7d1a2077 JB |
84 | .flags = IORESOURCE_MEM, |
85 | }, | |
dafc9543 BK |
86 | .irq = {IRQ_PDMA0, NO_IRQ}, |
87 | .periphid = 0x00041330, | |
7d1a2077 JB |
88 | }; |
89 | ||
8742e044 TA |
90 | u8 pdma1_peri[] = { |
91 | DMACH_UART0_RX, | |
92 | DMACH_UART0_TX, | |
93 | DMACH_UART1_RX, | |
94 | DMACH_UART1_TX, | |
95 | DMACH_UART2_RX, | |
96 | DMACH_UART2_TX, | |
97 | DMACH_UART3_RX, | |
98 | DMACH_UART3_TX, | |
99 | DMACH_MAX, | |
100 | DMACH_I2S0_RX, | |
101 | DMACH_I2S0_TX, | |
102 | DMACH_I2S0S_TX, | |
103 | DMACH_I2S1_RX, | |
104 | DMACH_I2S1_TX, | |
105 | DMACH_I2S2_RX, | |
106 | DMACH_I2S2_TX, | |
107 | DMACH_SPI0_RX, | |
108 | DMACH_SPI0_TX, | |
109 | DMACH_SPI1_RX, | |
110 | DMACH_SPI1_TX, | |
111 | DMACH_MAX, | |
112 | DMACH_MAX, | |
113 | DMACH_PCM0_RX, | |
114 | DMACH_PCM0_TX, | |
115 | DMACH_PCM1_RX, | |
116 | DMACH_PCM1_TX, | |
117 | DMACH_MSM_REQ0, | |
118 | DMACH_MSM_REQ1, | |
119 | DMACH_MSM_REQ2, | |
120 | DMACH_MSM_REQ3, | |
121 | DMACH_PCM2_RX, | |
122 | DMACH_PCM2_TX, | |
7d1a2077 JB |
123 | }; |
124 | ||
dafc9543 BK |
125 | struct dma_pl330_platdata s5pv210_pdma1_pdata = { |
126 | .nr_valid_peri = ARRAY_SIZE(pdma1_peri), | |
8742e044 | 127 | .peri_id = pdma1_peri, |
dafc9543 BK |
128 | }; |
129 | ||
130 | struct amba_device s5pv210_device_pdma1 = { | |
131 | .dev = { | |
132 | .init_name = "dma-pl330.1", | |
7d1a2077 JB |
133 | .dma_mask = &dma_dmamask, |
134 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
135 | .platform_data = &s5pv210_pdma1_pdata, | |
136 | }, | |
dafc9543 BK |
137 | .res = { |
138 | .start = S5PV210_PA_PDMA1, | |
139 | .end = S5PV210_PA_PDMA1 + SZ_4K, | |
140 | .flags = IORESOURCE_MEM, | |
141 | }, | |
142 | .irq = {IRQ_PDMA1, NO_IRQ}, | |
143 | .periphid = 0x00041330, | |
7d1a2077 JB |
144 | }; |
145 | ||
146 | static int __init s5pv210_dma_init(void) | |
147 | { | |
8742e044 TA |
148 | dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask); |
149 | dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask); | |
dafc9543 | 150 | amba_device_register(&s5pv210_device_pdma0, &iomem_resource); |
8742e044 TA |
151 | |
152 | dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask); | |
153 | dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask); | |
f86147cc | 154 | amba_device_register(&s5pv210_device_pdma1, &iomem_resource); |
7d1a2077 JB |
155 | |
156 | return 0; | |
157 | } | |
158 | arch_initcall(s5pv210_dma_init); |