ARM: S5P: irq_data conversion
[deliverable/linux.git] / arch / arm / mach-s5pv310 / irq-combiner.c
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1/* linux/arch/arm/mach-s5pv310/irq-combiner.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/common/gic.c
7 *
8 * IRQ COMBINER support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/io.h>
16
17#include <asm/mach/irq.h>
18
19#define COMBINER_ENABLE_SET 0x0
20#define COMBINER_ENABLE_CLEAR 0x4
21#define COMBINER_INT_STATUS 0xC
22
23static DEFINE_SPINLOCK(irq_controller_lock);
24
25struct combiner_chip_data {
26 unsigned int irq_offset;
27 void __iomem *base;
28};
29
30static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
31
bb0b2374 32static inline void __iomem *combiner_base(struct irq_data *data)
84bbc16c 33{
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34 struct combiner_chip_data *combiner_data =
35 irq_data_get_irq_chip_data(data);
36
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37 return combiner_data->base;
38}
39
bb0b2374 40static void combiner_mask_irq(struct irq_data *data)
84bbc16c 41{
bb0b2374 42 u32 mask = 1 << (data->irq % 32);
84bbc16c 43
bb0b2374 44 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
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45}
46
bb0b2374 47static void combiner_unmask_irq(struct irq_data *data)
84bbc16c 48{
bb0b2374 49 u32 mask = 1 << (data->irq % 32);
84bbc16c 50
bb0b2374 51 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
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52}
53
54static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
55{
56 struct combiner_chip_data *chip_data = get_irq_data(irq);
57 struct irq_chip *chip = get_irq_chip(irq);
58 unsigned int cascade_irq, combiner_irq;
59 unsigned long status;
60
61 /* primary controller ack'ing */
bb0b2374 62 chip->irq_ack(&desc->irq_data);
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63
64 spin_lock(&irq_controller_lock);
65 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
66 spin_unlock(&irq_controller_lock);
67
68 if (status == 0)
69 goto out;
70
0c0f9096 71 combiner_irq = __ffs(status);
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72
73 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
74 if (unlikely(cascade_irq >= NR_IRQS))
75 do_bad_IRQ(cascade_irq, desc);
76 else
77 generic_handle_irq(cascade_irq);
78
79 out:
80 /* primary controller unmasking */
bb0b2374 81 chip->irq_unmask(&desc->irq_data);
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82}
83
84static struct irq_chip combiner_chip = {
85 .name = "COMBINER",
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86 .irq_mask = combiner_mask_irq,
87 .irq_unmask = combiner_unmask_irq,
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88};
89
90void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
91{
92 if (combiner_nr >= MAX_COMBINER_NR)
93 BUG();
94 if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0)
95 BUG();
96 set_irq_chained_handler(irq, combiner_handle_cascade_irq);
97}
98
99void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
100 unsigned int irq_start)
101{
102 unsigned int i;
103
104 if (combiner_nr >= MAX_COMBINER_NR)
105 BUG();
106
107 combiner_data[combiner_nr].base = base;
108 combiner_data[combiner_nr].irq_offset = irq_start;
109
110 /* Disable all interrupts */
111
112 __raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR);
113
114 /* Setup the Linux IRQ subsystem */
115
116 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
117 + MAX_IRQ_IN_COMBINER; i++) {
118 set_irq_chip(i, &combiner_chip);
119 set_irq_chip_data(i, &combiner_data[combiner_nr]);
120 set_irq_handler(i, handle_level_irq);
121 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
122 }
123}
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