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2b12b5c4 CY |
1 | /* linux/arch/arm/mach-s5pv310/platsmp.c |
2 | * | |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * Cloned from linux/arch/arm/mach-vexpress/platsmp.c | |
7 | * | |
8 | * Copyright (C) 2002 ARM Ltd. | |
9 | * All Rights Reserved | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/jiffies.h> | |
21 | #include <linux/smp.h> | |
22 | #include <linux/io.h> | |
23 | ||
24 | #include <asm/cacheflush.h> | |
2b12b5c4 CY |
25 | #include <asm/smp_scu.h> |
26 | #include <asm/unified.h> | |
27 | ||
28 | #include <mach/hardware.h> | |
29 | #include <mach/regs-clock.h> | |
30 | ||
31 | extern void s5pv310_secondary_startup(void); | |
32 | ||
33 | /* | |
34 | * control for which core is the next to come out of the secondary | |
35 | * boot "holding pen" | |
36 | */ | |
37 | ||
38 | volatile int __cpuinitdata pen_release = -1; | |
39 | ||
3705ff6d RK |
40 | /* |
41 | * Write pen_release in a way that is guaranteed to be visible to all | |
42 | * observers, irrespective of whether they're taking part in coherency | |
43 | * or not. This is necessary for the hotplug code to work reliably. | |
44 | */ | |
45 | static void write_pen_release(int val) | |
46 | { | |
47 | pen_release = val; | |
48 | smp_wmb(); | |
49 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | |
50 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | |
51 | } | |
52 | ||
2b12b5c4 CY |
53 | static void __iomem *scu_base_addr(void) |
54 | { | |
55 | return (void __iomem *)(S5P_VA_SCU); | |
56 | } | |
57 | ||
58 | static DEFINE_SPINLOCK(boot_lock); | |
59 | ||
60 | void __cpuinit platform_secondary_init(unsigned int cpu) | |
61 | { | |
2b12b5c4 CY |
62 | /* |
63 | * if any interrupts are already enabled for the primary | |
64 | * core (e.g. timer irq), then they will not have been enabled | |
65 | * for us: do so | |
66 | */ | |
67 | gic_cpu_init(0, gic_cpu_base_addr); | |
68 | ||
69 | /* | |
70 | * let the primary processor know we're out of the | |
71 | * pen, then head off into the C entry point | |
72 | */ | |
3705ff6d | 73 | write_pen_release(-1); |
2b12b5c4 CY |
74 | |
75 | /* | |
76 | * Synchronise with the boot thread. | |
77 | */ | |
78 | spin_lock(&boot_lock); | |
79 | spin_unlock(&boot_lock); | |
80 | } | |
81 | ||
82 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
83 | { | |
84 | unsigned long timeout; | |
85 | ||
86 | /* | |
87 | * Set synchronisation state between this boot processor | |
88 | * and the secondary one | |
89 | */ | |
90 | spin_lock(&boot_lock); | |
91 | ||
92 | /* | |
93 | * The secondary processor is waiting to be released from | |
94 | * the holding pen - release it, then wait for it to flag | |
95 | * that it has been released by resetting pen_release. | |
96 | * | |
97 | * Note that "pen_release" is the hardware CPU ID, whereas | |
98 | * "cpu" is Linux's internal ID. | |
99 | */ | |
3705ff6d | 100 | write_pen_release(cpu); |
2b12b5c4 CY |
101 | |
102 | /* | |
103 | * Send the secondary CPU a soft interrupt, thereby causing | |
104 | * the boot monitor to read the system wide flags register, | |
105 | * and branch to the address found there. | |
106 | */ | |
ad3b6993 | 107 | smp_cross_call(cpumask_of(cpu), 1); |
2b12b5c4 CY |
108 | |
109 | timeout = jiffies + (1 * HZ); | |
110 | while (time_before(jiffies, timeout)) { | |
111 | smp_rmb(); | |
112 | if (pen_release == -1) | |
113 | break; | |
114 | ||
115 | udelay(10); | |
116 | } | |
117 | ||
118 | /* | |
119 | * now the secondary core is starting up let it run its | |
120 | * calibrations, then wait for it to finish | |
121 | */ | |
122 | spin_unlock(&boot_lock); | |
123 | ||
124 | return pen_release != -1 ? -ENOSYS : 0; | |
125 | } | |
126 | ||
127 | /* | |
128 | * Initialise the CPU possible map early - this describes the CPUs | |
129 | * which may be present or become present in the system. | |
130 | */ | |
131 | ||
132 | void __init smp_init_cpus(void) | |
133 | { | |
134 | void __iomem *scu_base = scu_base_addr(); | |
135 | unsigned int i, ncores; | |
136 | ||
137 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; | |
138 | ||
139 | /* sanity check */ | |
2b12b5c4 CY |
140 | if (ncores > NR_CPUS) { |
141 | printk(KERN_WARNING | |
142 | "S5PV310: no. of cores (%d) greater than configured " | |
143 | "maximum of %d - clipping\n", | |
144 | ncores, NR_CPUS); | |
145 | ncores = NR_CPUS; | |
146 | } | |
147 | ||
148 | for (i = 0; i < ncores; i++) | |
149 | set_cpu_possible(i, true); | |
150 | } | |
151 | ||
05c74a6c | 152 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
2b12b5c4 | 153 | { |
2b12b5c4 CY |
154 | int i; |
155 | ||
2b12b5c4 CY |
156 | /* |
157 | * Initialise the present map, which describes the set of CPUs | |
158 | * actually populated at the present time. | |
159 | */ | |
160 | for (i = 0; i < max_cpus; i++) | |
161 | set_cpu_present(i, true); | |
162 | ||
05c74a6c RK |
163 | scu_enable(scu_base_addr()); |
164 | ||
2b12b5c4 | 165 | /* |
05c74a6c RK |
166 | * Write the address of secondary startup into the |
167 | * system-wide flags register. The boot monitor waits | |
168 | * until it receives a soft interrupt, and then the | |
169 | * secondary CPU branches to this address. | |
2b12b5c4 | 170 | */ |
766211e7 | 171 | __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM); |
2b12b5c4 | 172 | } |