[deliverable/linux.git] / arch / arm / mach-sa1100 / assabet.c

/*
 * linux/arch/arm/mach-sa1100/assabet.c
 *
 * Author: Nicolas Pitre
 *
 * This file contains all Assabet-specific tweaks.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/mfd/ucb1x00.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/delay.h>
#include <linux/mm.h>

#include <video/sa1100fb.h>

#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irda.h>
#include <asm/mach/map.h>
#include <asm/mach/serial_sa1100.h>
#include <mach/assabet.h>
#include <mach/mcp.h>
#include <mach/irqs.h>

#include "generic.h"

#define ASSABET_BCR_DB1110 \
	(ASSABET_BCR_SPK_OFF    | \
	 ASSABET_BCR_LED_GREEN  | ASSABET_BCR_LED_RED   | \
	 ASSABET_BCR_RS232EN    | ASSABET_BCR_LCD_12RGB | \
	 ASSABET_BCR_IRDA_MD0)

#define ASSABET_BCR_DB1111 \
	(ASSABET_BCR_SPK_OFF    | \
	 ASSABET_BCR_LED_GREEN  | ASSABET_BCR_LED_RED   | \
	 ASSABET_BCR_RS232EN    | ASSABET_BCR_LCD_12RGB | \
	 ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \
	 ASSABET_BCR_IRDA_MD0   | ASSABET_BCR_CF_RST)

unsigned long SCR_value = ASSABET_SCR_INIT;
EXPORT_SYMBOL(SCR_value);

static unsigned long BCR_value = ASSABET_BCR_DB1110;

void ASSABET_BCR_frob(unsigned int mask, unsigned int val)
{
	unsigned long flags;

	local_irq_save(flags);
	BCR_value = (BCR_value & ~mask) | val;
	ASSABET_BCR = BCR_value;
	local_irq_restore(flags);
}

EXPORT_SYMBOL(ASSABET_BCR_frob);

static void assabet_ucb1x00_reset(enum ucb1x00_reset state)
{
	if (state == UCB_RST_PROBE)
		ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
}


/*
 * Assabet flash support code.
 */

#ifdef ASSABET_REV_4
/*
 * Phase 4 Assabet has two 28F160B3 flash parts in bank 0:
 */
static struct mtd_partition assabet_partitions[] = {
	{
		.name		= "bootloader",
		.size		= 0x00020000,
		.offset		= 0,
		.mask_flags	= MTD_WRITEABLE,
	}, {
		.name		= "bootloader params",
		.size		= 0x00020000,
		.offset		= MTDPART_OFS_APPEND,
		.mask_flags	= MTD_WRITEABLE,
	}, {
		.name		= "jffs",
		.size		= MTDPART_SIZ_FULL,
		.offset		= MTDPART_OFS_APPEND,
	}
};
#else
/*
 * Phase 5 Assabet has two 28F128J3A flash parts in bank 0:
 */
static struct mtd_partition assabet_partitions[] = {
	{
		.name		= "bootloader",
		.size		= 0x00040000,
		.offset		= 0,
		.mask_flags	= MTD_WRITEABLE,
	}, {
		.name		= "bootloader params",
		.size		= 0x00040000,
		.offset		= MTDPART_OFS_APPEND,
		.mask_flags	= MTD_WRITEABLE,
	}, {
		.name		= "jffs",
		.size		= MTDPART_SIZ_FULL,
		.offset		= MTDPART_OFS_APPEND,
	}
};
#endif

static struct flash_platform_data assabet_flash_data = {
	.map_name	= "cfi_probe",
	.parts		= assabet_partitions,
	.nr_parts	= ARRAY_SIZE(assabet_partitions),
};

static struct resource assabet_flash_resources[] = {
	DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
	DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
};


/*
 * Assabet IrDA support code.
 */

static int assabet_irda_set_power(struct device *dev, unsigned int state)
{
	static unsigned int bcr_state[4] = {
		ASSABET_BCR_IRDA_MD0,
		ASSABET_BCR_IRDA_MD1|ASSABET_BCR_IRDA_MD0,
		ASSABET_BCR_IRDA_MD1,
		0
	};

	if (state < 4) {
		state = bcr_state[state];
		ASSABET_BCR_clear(state ^ (ASSABET_BCR_IRDA_MD1|
					   ASSABET_BCR_IRDA_MD0));
		ASSABET_BCR_set(state);
	}
	return 0;
}

static void assabet_irda_set_speed(struct device *dev, unsigned int speed)
{
	if (speed < 4000000)
		ASSABET_BCR_clear(ASSABET_BCR_IRDA_FSEL);
	else
		ASSABET_BCR_set(ASSABET_BCR_IRDA_FSEL);
}

static struct irda_platform_data assabet_irda_data = {
	.set_power	= assabet_irda_set_power,
	.set_speed	= assabet_irda_set_speed,
};

static struct ucb1x00_plat_data assabet_ucb1x00_data = {
	.reset		= assabet_ucb1x00_reset,
	.gpio_base	= -1,
};

static struct mcp_plat_data assabet_mcp_data = {
	.mccr0		= MCCR0_ADM,
	.sclk_rate	= 11981000,
	.codec_pdata	= &assabet_ucb1x00_data,
};

static void assabet_lcd_set_visual(u32 visual)
{
	u_int is_true_color = visual == FB_VISUAL_TRUECOLOR;

	if (machine_is_assabet()) {
#if 1		// phase 4 or newer Assabet's
		if (is_true_color)
			ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
		else
			ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
#else
		// older Assabet's
		if (is_true_color)
			ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
		else
			ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
#endif
	}
}

#ifndef ASSABET_PAL_VIDEO
static void assabet_lcd_backlight_power(int on)
{
	if (on)
		ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
	else
		ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
}

/*
 * Turn on/off the backlight.  When turning the backlight on, we wait
 * 500us after turning it on so we don't cause the supplies to droop
 * when we enable the LCD controller (and cause a hard reset.)
 */
static void assabet_lcd_power(int on)
{
	if (on) {
		ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
		udelay(500);
	} else
		ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
}

/*
 * The assabet uses a sharp LQ039Q2DS54 LCD module.  It is actually
 * takes an RGB666 signal, but we provide it with an RGB565 signal
 * instead (def_rgb_16).
 */
static struct sa1100fb_mach_info lq039q2ds54_info = {
	.pixclock	= 171521,	.bpp		= 16,
	.xres		= 320,		.yres		= 240,

	.hsync_len	= 5,		.vsync_len	= 1,
	.left_margin	= 61,		.upper_margin	= 3,
	.right_margin	= 9,		.lower_margin	= 0,

	.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

	.lccr0		= LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
	.lccr3		= LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),

	.backlight_power = assabet_lcd_backlight_power,
	.lcd_power = assabet_lcd_power,
	.set_visual = assabet_lcd_set_visual,
};
#else
static void assabet_pal_backlight_power(int on)
{
	ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
}

static void assabet_pal_power(int on)
{
	ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
}

static struct sa1100fb_mach_info pal_info = {
	.pixclock	= 67797,	.bpp		= 16,
	.xres		= 640,		.yres		= 512,

	.hsync_len	= 64,		.vsync_len	= 6,
	.left_margin	= 125,		.upper_margin	= 70,
	.right_margin	= 115,		.lower_margin	= 36,

	.lccr0		= LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
	.lccr3		= LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),

	.backlight_power = assabet_pal_backlight_power,
	.lcd_power = assabet_pal_power,
	.set_visual = assabet_lcd_set_visual,
};
#endif

#ifdef CONFIG_ASSABET_NEPONSET
static struct resource neponset_resources[] = {
	DEFINE_RES_MEM(0x10000000, 0x08000000),
	DEFINE_RES_MEM(0x18000000, 0x04000000),
	DEFINE_RES_MEM(0x40000000, SZ_8K),
	DEFINE_RES_IRQ(IRQ_GPIO25),
};
#endif

static void __init assabet_init(void)
{
	/*
	 * Ensure that the power supply is in "high power" mode.
	 */
	GPSR = GPIO_GPIO16;
	GPDR |= GPIO_GPIO16;

	/*
	 * Ensure that these pins are set as outputs and are driving
	 * logic 0.  This ensures that we won't inadvertently toggle
	 * the WS latch in the CPLD, and we don't float causing
	 * excessive power drain.  --rmk
	 */
	GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
	GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;

	/*
	 * Also set GPIO27 as an output; this is used to clock UART3
	 * via the FPGA and as otherwise has no pullups or pulldowns,
	 * so stop it floating.
	 */
	GPCR = GPIO_GPIO27;
	GPDR |= GPIO_GPIO27;

	/*
	 * Set up registers for sleep mode.
	 */
	PWER = PWER_GPIO0;
	PGSR = 0;
	PCFR = 0;
	PSDR = 0;
	PPDR |= PPC_TXD3 | PPC_TXD1;
	PPSR |= PPC_TXD3 | PPC_TXD1;

	sa11x0_ppc_configure_mcp();

	if (machine_has_neponset()) {
		/*
		 * Angel sets this, but other bootloaders may not.
		 *
		 * This must precede any driver calls to BCR_set()
		 * or BCR_clear().
		 */
		ASSABET_BCR = BCR_value = ASSABET_BCR_DB1111;

#ifndef CONFIG_ASSABET_NEPONSET
		printk( "Warning: Neponset detected but full support "
			"hasn't been configured in the kernel\n" );
#else
		platform_device_register_simple("neponset", 0,
			neponset_resources, ARRAY_SIZE(neponset_resources));
#endif
	}

#ifndef ASSABET_PAL_VIDEO
	sa11x0_register_lcd(&lq039q2ds54_info);
#else
	sa11x0_register_lcd(&pal_video);
#endif
	sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
			    ARRAY_SIZE(assabet_flash_resources));
	sa11x0_register_irda(&assabet_irda_data);
	sa11x0_register_mcp(&assabet_mcp_data);
}

/*
 * On Assabet, we must probe for the Neponset board _before_
 * paging_init() has occurred to actually determine the amount
 * of RAM available.  To do so, we map the appropriate IO section
 * in the page table here in order to access GPIO registers.
 */
static void __init map_sa1100_gpio_regs( void )
{
	unsigned long phys = __PREG(GPLR) & PMD_MASK;
	unsigned long virt = (unsigned long)io_p2v(phys);
	int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
	pmd_t *pmd;

	pmd = pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt);
	*pmd = __pmd(phys | prot);
	flush_pmd_entry(pmd);
}

/*
 * Read System Configuration "Register"
 * (taken from "Intel StrongARM SA-1110 Microprocessor Development Board
 * User's Guide", section 4.4.1)
 *
 * This same scan is performed in arch/arm/boot/compressed/head-sa1100.S
 * to set up the serial port for decompression status messages. We
 * repeat it here because the kernel may not be loaded as a zImage, and
 * also because it's a hassle to communicate the SCR value to the kernel
 * from the decompressor.
 *
 * Note that IRQs are guaranteed to be disabled.
 */
static void __init get_assabet_scr(void)
{
	unsigned long scr, i;

	GPDR |= 0x3fc;			/* Configure GPIO 9:2 as outputs */
	GPSR = 0x3fc;			/* Write 0xFF to GPIO 9:2 */
	GPDR &= ~(0x3fc);		/* Configure GPIO 9:2 as inputs */
	for(i = 100; i--; )		/* Read GPIO 9:2 */
		scr = GPLR;
	GPDR |= 0x3fc;			/*  restore correct pin direction */
	scr &= 0x3fc;			/* save as system configuration byte. */
	SCR_value = scr;
}

static void __init
fixup_assabet(struct tag *tags, char **cmdline, struct meminfo *mi)
{
	/* This must be done before any call to machine_has_neponset() */
	map_sa1100_gpio_regs();
	get_assabet_scr();

	if (machine_has_neponset())
		printk("Neponset expansion board detected\n");
}


static void assabet_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
{
	if (port->mapbase == _Ser1UTCR0) {
		if (state)
			ASSABET_BCR_clear(ASSABET_BCR_RS232EN |
					  ASSABET_BCR_COM_RTS |
					  ASSABET_BCR_COM_DTR);
		else
			ASSABET_BCR_set(ASSABET_BCR_RS232EN |
					ASSABET_BCR_COM_RTS |
					ASSABET_BCR_COM_DTR);
	}
}

/*
 * Assabet uses COM_RTS and COM_DTR for both UART1 (com port)
 * and UART3 (radio module).  We only handle them for UART1 here.
 */
static void assabet_set_mctrl(struct uart_port *port, u_int mctrl)
{
	if (port->mapbase == _Ser1UTCR0) {
		u_int set = 0, clear = 0;

		if (mctrl & TIOCM_RTS)
			clear |= ASSABET_BCR_COM_RTS;
		else
			set |= ASSABET_BCR_COM_RTS;

		if (mctrl & TIOCM_DTR)
			clear |= ASSABET_BCR_COM_DTR;
		else
			set |= ASSABET_BCR_COM_DTR;

		ASSABET_BCR_clear(clear);
		ASSABET_BCR_set(set);
	}
}

static u_int assabet_get_mctrl(struct uart_port *port)
{
	u_int ret = 0;
	u_int bsr = ASSABET_BSR;

	/* need 2 reads to read current value */
	bsr = ASSABET_BSR;

	if (port->mapbase == _Ser1UTCR0) {
		if (bsr & ASSABET_BSR_COM_DCD)
			ret |= TIOCM_CD;
		if (bsr & ASSABET_BSR_COM_CTS)
			ret |= TIOCM_CTS;
		if (bsr & ASSABET_BSR_COM_DSR)
			ret |= TIOCM_DSR;
	} else if (port->mapbase == _Ser3UTCR0) {
		if (bsr & ASSABET_BSR_RAD_DCD)
			ret |= TIOCM_CD;
		if (bsr & ASSABET_BSR_RAD_CTS)
			ret |= TIOCM_CTS;
		if (bsr & ASSABET_BSR_RAD_DSR)
			ret |= TIOCM_DSR;
		if (bsr & ASSABET_BSR_RAD_RI)
			ret |= TIOCM_RI;
	} else {
		ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
	}

	return ret;
}

static struct sa1100_port_fns assabet_port_fns __initdata = {
	.set_mctrl	= assabet_set_mctrl,
	.get_mctrl	= assabet_get_mctrl,
	.pm		= assabet_uart_pm,
};

static struct map_desc assabet_io_desc[] __initdata = {
  	{	/* Board Control Register */
		.virtual	=  0xf1000000,
		.pfn		= __phys_to_pfn(0x12000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* MQ200 */
		.virtual	=  0xf2800000,
		.pfn		= __phys_to_pfn(0x4b800000),
		.length		= 0x00800000,
		.type		= MT_DEVICE
	}
};

static void __init assabet_map_io(void)
{
	sa1100_map_io();
	iotable_init(assabet_io_desc, ARRAY_SIZE(assabet_io_desc));

	/*
	 * Set SUS bit in SDCR0 so serial port 1 functions.
	 * Its called GPCLKR0 in my SA1110 manual.
	 */
	Ser1SDCR0 |= SDCR0_SUS;

	if (!machine_has_neponset())
		sa1100_register_uart_fns(&assabet_port_fns);

	/*
	 * When Neponset is attached, the first UART should be
	 * UART3.  That's what Angel is doing and many documents
	 * are stating this.
	 *
	 * We do the Neponset mapping even if Neponset support
	 * isn't compiled in so the user will still get something on
	 * the expected physical serial port.
	 *
	 * We no longer do this; not all boot loaders support it,
	 * and UART3 appears to be somewhat unreliable with blob.
	 */
	sa1100_register_uart(0, 1);
	sa1100_register_uart(2, 3);
}


MACHINE_START(ASSABET, "Intel-Assabet")
	.atag_offset	= 0x100,
	.fixup		= fixup_assabet,
	.map_io		= assabet_map_io,
	.nr_irqs	= SA1100_NR_IRQS,
	.init_irq	= sa1100_init_irq,
	.timer		= &sa1100_timer,
	.init_machine	= assabet_init,
	.init_late	= sa11x0_init_late,
#ifdef CONFIG_SA1111
	.dma_zone_size	= SZ_1M,
#endif
	.restart	= sa11x0_restart,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-sa1100/assabet.c
	3	*
	4	* Author: Nicolas Pitre
	5	*
	6	* This file contains all Assabet-specific tweaks.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
1da177e4 LT	12	#include <linux/init.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/errno.h>
	16	#include <linux/ioport.h>
	17	#include <linux/serial_core.h>
69dde86a	18	#include <linux/mfd/ucb1x00.h>
1da177e4 LT	19	#include <linux/mtd/mtd.h>
	20	#include <linux/mtd/partitions.h>
	21	#include <linux/delay.h>
	22	#include <linux/mm.h>
	23
e1b7a72a RK	24	#include <video/sa1100fb.h>
e1b7a72a RK	25
a09e64fb	26	#include <mach/hardware.h>
1da177e4	27	#include <asm/mach-types.h>
1da177e4 LT	28	#include <asm/setup.h>
1da177e4 LT	29	#include <asm/page.h>
74945c86	30	#include <asm/pgtable-hwdef.h>
1da177e4 LT	31	#include <asm/pgtable.h>
	32	#include <asm/tlbflush.h>
	33
	34	#include <asm/mach/arch.h>
	35	#include <asm/mach/flash.h>
	36	#include <asm/mach/irda.h>
	37	#include <asm/mach/map.h>
	38	#include <asm/mach/serial_sa1100.h>
a09e64fb RK	39	#include <mach/assabet.h>
a09e64fb RK	40	#include <mach/mcp.h>
f314f33b	41	#include <mach/irqs.h>
1da177e4 LT	42
	43	#include "generic.h"
	44
	45	#define ASSABET_BCR_DB1110 \
7186fb9f	46	(ASSABET_BCR_SPK_OFF \| \
1da177e4 LT	47	ASSABET_BCR_LED_GREEN \| ASSABET_BCR_LED_RED \| \
	48	ASSABET_BCR_RS232EN \| ASSABET_BCR_LCD_12RGB \| \
	49	ASSABET_BCR_IRDA_MD0)
	50
	51	#define ASSABET_BCR_DB1111 \
7186fb9f	52	(ASSABET_BCR_SPK_OFF \| \
1da177e4 LT	53	ASSABET_BCR_LED_GREEN \| ASSABET_BCR_LED_RED \| \
	54	ASSABET_BCR_RS232EN \| ASSABET_BCR_LCD_12RGB \| \
	55	ASSABET_BCR_CF_BUS_OFF \| ASSABET_BCR_STEREO_LB \| \
	56	ASSABET_BCR_IRDA_MD0 \| ASSABET_BCR_CF_RST)
	57
	58	unsigned long SCR_value = ASSABET_SCR_INIT;
	59	EXPORT_SYMBOL(SCR_value);
	60
	61	static unsigned long BCR_value = ASSABET_BCR_DB1110;
	62
	63	void ASSABET_BCR_frob(unsigned int mask, unsigned int val)
	64	{
	65	unsigned long flags;
	66
	67	local_irq_save(flags);
	68	BCR_value = (BCR_value & ~mask) \| val;
	69	ASSABET_BCR = BCR_value;
	70	local_irq_restore(flags);
	71	}
	72
	73	EXPORT_SYMBOL(ASSABET_BCR_frob);
	74
6ed3e2ac RK	75	static void assabet_ucb1x00_reset(enum ucb1x00_reset state)
	76	{
	77	if (state == UCB_RST_PROBE)
	78	ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
	79	}
	80
1da177e4 LT	81
	82	/*
	83	* Assabet flash support code.
	84	*/
	85
	86	#ifdef ASSABET_REV_4
	87	/*
	88	* Phase 4 Assabet has two 28F160B3 flash parts in bank 0:
	89	*/
	90	static struct mtd_partition assabet_partitions[] = {
	91	{
	92	.name = "bootloader",
	93	.size = 0x00020000,
	94	.offset = 0,
	95	.mask_flags = MTD_WRITEABLE,
	96	}, {
	97	.name = "bootloader params",
	98	.size = 0x00020000,
	99	.offset = MTDPART_OFS_APPEND,
	100	.mask_flags = MTD_WRITEABLE,
	101	}, {
	102	.name = "jffs",
	103	.size = MTDPART_SIZ_FULL,
	104	.offset = MTDPART_OFS_APPEND,
	105	}
	106	};
	107	#else
	108	/*
	109	* Phase 5 Assabet has two 28F128J3A flash parts in bank 0:
	110	*/
	111	static struct mtd_partition assabet_partitions[] = {
	112	{
	113	.name = "bootloader",
	114	.size = 0x00040000,
	115	.offset = 0,
	116	.mask_flags = MTD_WRITEABLE,
	117	}, {
	118	.name = "bootloader params",
	119	.size = 0x00040000,
	120	.offset = MTDPART_OFS_APPEND,
	121	.mask_flags = MTD_WRITEABLE,
	122	}, {
	123	.name = "jffs",
	124	.size = MTDPART_SIZ_FULL,
	125	.offset = MTDPART_OFS_APPEND,
	126	}
	127	};
	128	#endif
	129
	130	static struct flash_platform_data assabet_flash_data = {
	131	.map_name = "cfi_probe",
	132	.parts = assabet_partitions,
	133	.nr_parts = ARRAY_SIZE(assabet_partitions),
	134	};
	135
	136	static struct resource assabet_flash_resources[] = {
a181099e RK	137	DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
a181099e RK	138	DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
1da177e4 LT	139	};
	140
	141
	142	/*
	143	* Assabet IrDA support code.
	144	*/
	145
	146	static int assabet_irda_set_power(struct device *dev, unsigned int state)
	147	{
	148	static unsigned int bcr_state[4] = {
	149	ASSABET_BCR_IRDA_MD0,
	150	ASSABET_BCR_IRDA_MD1\|ASSABET_BCR_IRDA_MD0,
	151	ASSABET_BCR_IRDA_MD1,
	152	0
	153	};
	154
	155	if (state < 4) {
	156	state = bcr_state[state];
	157	ASSABET_BCR_clear(state ^ (ASSABET_BCR_IRDA_MD1\|
	158	ASSABET_BCR_IRDA_MD0));
	159	ASSABET_BCR_set(state);
	160	}
	161	return 0;
	162	}
	163
	164	static void assabet_irda_set_speed(struct device *dev, unsigned int speed)
	165	{
	166	if (speed < 4000000)
	167	ASSABET_BCR_clear(ASSABET_BCR_IRDA_FSEL);
	168	else
	169	ASSABET_BCR_set(ASSABET_BCR_IRDA_FSEL);
	170	}
	171
	172	static struct irda_platform_data assabet_irda_data = {
	173	.set_power = assabet_irda_set_power,
	174	.set_speed = assabet_irda_set_speed,
	175	};
	176
69dde86a	177	static struct ucb1x00_plat_data assabet_ucb1x00_data = {
6ed3e2ac	178	.reset = assabet_ucb1x00_reset,
69dde86a RK	179	.gpio_base = -1,
	180	};
	181
323cdfc1 RK	182	static struct mcp_plat_data assabet_mcp_data = {
	183	.mccr0 = MCCR0_ADM,
	184	.sclk_rate = 11981000,
69dde86a	185	.codec_pdata = &assabet_ucb1x00_data,
323cdfc1 RK	186	};
323cdfc1 RK	187
086ada54 RK	188	static void assabet_lcd_set_visual(u32 visual)
	189	{
	190	u_int is_true_color = visual == FB_VISUAL_TRUECOLOR;
	191
	192	if (machine_is_assabet()) {
	193	#if 1 // phase 4 or newer Assabet's
	194	if (is_true_color)
	195	ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
	196	else
	197	ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
	198	#else
	199	// older Assabet's
	200	if (is_true_color)
	201	ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
	202	else
	203	ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
	204	#endif
	205	}
	206	}
	207
e1b7a72a	208	#ifndef ASSABET_PAL_VIDEO
086ada54 RK	209	static void assabet_lcd_backlight_power(int on)
	210	{
	211	if (on)
	212	ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
	213	else
	214	ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
	215	}
	216
	217	/*
	218	* Turn on/off the backlight. When turning the backlight on, we wait
	219	* 500us after turning it on so we don't cause the supplies to droop
	220	* when we enable the LCD controller (and cause a hard reset.)
	221	*/
	222	static void assabet_lcd_power(int on)
	223	{
	224	if (on) {
	225	ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
	226	udelay(500);
	227	} else
	228	ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
	229	}
	230
e1b7a72a RK	231	/*
	232	* The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
	233	* takes an RGB666 signal, but we provide it with an RGB565 signal
	234	* instead (def_rgb_16).
	235	*/
	236	static struct sa1100fb_mach_info lq039q2ds54_info = {
	237	.pixclock = 171521, .bpp = 16,
	238	.xres = 320, .yres = 240,
	239
	240	.hsync_len = 5, .vsync_len = 1,
	241	.left_margin = 61, .upper_margin = 3,
	242	.right_margin = 9, .lower_margin = 0,
	243
	244	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	245
	246	.lccr0 = LCCR0_Color \| LCCR0_Sngl \| LCCR0_Act,
	247	.lccr3 = LCCR3_OutEnH \| LCCR3_PixRsEdg \| LCCR3_ACBsDiv(2),
086ada54 RK	248
	249	.backlight_power = assabet_lcd_backlight_power,
	250	.lcd_power = assabet_lcd_power,
	251	.set_visual = assabet_lcd_set_visual,
e1b7a72a RK	252	};
e1b7a72a RK	253	#else
086ada54 RK	254	static void assabet_pal_backlight_power(int on)
	255	{
	256	ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
	257	}
	258
	259	static void assabet_pal_power(int on)
	260	{
	261	ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
	262	}
	263
e1b7a72a RK	264	static struct sa1100fb_mach_info pal_info = {
	265	.pixclock = 67797, .bpp = 16,
	266	.xres = 640, .yres = 512,
	267
	268	.hsync_len = 64, .vsync_len = 6,
	269	.left_margin = 125, .upper_margin = 70,
	270	.right_margin = 115, .lower_margin = 36,
	271
	272	.lccr0 = LCCR0_Color \| LCCR0_Sngl \| LCCR0_Act,
	273	.lccr3 = LCCR3_OutEnH \| LCCR3_PixRsEdg \| LCCR3_ACBsDiv(512),
086ada54 RK	274
	275	.backlight_power = assabet_pal_backlight_power,
	276	.lcd_power = assabet_pal_power,
	277	.set_visual = assabet_lcd_set_visual,
e1b7a72a RK	278	};
	279	#endif
	280
bab50a35 RK	281	#ifdef CONFIG_ASSABET_NEPONSET
	282	static struct resource neponset_resources[] = {
	283	DEFINE_RES_MEM(0x10000000, 0x08000000),
	284	DEFINE_RES_MEM(0x18000000, 0x04000000),
	285	DEFINE_RES_MEM(0x40000000, SZ_8K),
	286	DEFINE_RES_IRQ(IRQ_GPIO25),
	287	};
	288	#endif
	289
1da177e4 LT	290	static void __init assabet_init(void)
	291	{
	292	/*
	293	* Ensure that the power supply is in "high power" mode.
	294	*/
1da177e4	295	GPSR = GPIO_GPIO16;
4f592e6d	296	GPDR \|= GPIO_GPIO16;
1da177e4 LT	297
	298	/*
	299	* Ensure that these pins are set as outputs and are driving
	300	* logic 0. This ensures that we won't inadvertently toggle
	301	* the WS latch in the CPLD, and we don't float causing
	302	* excessive power drain. --rmk
	303	*/
1da177e4	304	GPCR = GPIO_SSP_TXD \| GPIO_SSP_SCLK \| GPIO_SSP_SFRM;
4f592e6d	305	GPDR \|= GPIO_SSP_TXD \| GPIO_SSP_SCLK \| GPIO_SSP_SFRM;
1da177e4	306
49e01e3f RK	307	/*
	308	* Also set GPIO27 as an output; this is used to clock UART3
	309	* via the FPGA and as otherwise has no pullups or pulldowns,
	310	* so stop it floating.
	311	*/
	312	GPCR = GPIO_GPIO27;
	313	GPDR \|= GPIO_GPIO27;
	314
1da177e4 LT	315	/*
	316	* Set up registers for sleep mode.
	317	*/
	318	PWER = PWER_GPIO0;
	319	PGSR = 0;
	320	PCFR = 0;
	321	PSDR = 0;
	322	PPDR \|= PPC_TXD3 \| PPC_TXD1;
	323	PPSR \|= PPC_TXD3 \| PPC_TXD1;
	324
e36e26a8 RK	325	sa11x0_ppc_configure_mcp();
e36e26a8 RK	326
1da177e4 LT	327	if (machine_has_neponset()) {
	328	/*
	329	* Angel sets this, but other bootloaders may not.
	330	*
	331	* This must precede any driver calls to BCR_set()
	332	* or BCR_clear().
	333	*/
	334	ASSABET_BCR = BCR_value = ASSABET_BCR_DB1111;
	335
	336	#ifndef CONFIG_ASSABET_NEPONSET
	337	printk( "Warning: Neponset detected but full support "
	338	"hasn't been configured in the kernel\n" );
bab50a35 RK	339	#else
	340	platform_device_register_simple("neponset", 0,
	341	neponset_resources, ARRAY_SIZE(neponset_resources));
1da177e4 LT	342	#endif
	343	}
	344
e1b7a72a RK	345	#ifndef ASSABET_PAL_VIDEO
	346	sa11x0_register_lcd(&lq039q2ds54_info);
	347	#else
	348	sa11x0_register_lcd(&pal_video);
	349	#endif
7a5b4e16 RK	350	sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
	351	ARRAY_SIZE(assabet_flash_resources));
	352	sa11x0_register_irda(&assabet_irda_data);
	353	sa11x0_register_mcp(&assabet_mcp_data);
1da177e4 LT	354	}
	355
	356	/*
	357	* On Assabet, we must probe for the Neponset board _before_
	358	* paging_init() has occurred to actually determine the amount
	359	* of RAM available. To do so, we map the appropriate IO section
	360	* in the page table here in order to access GPIO registers.
	361	*/
	362	static void __init map_sa1100_gpio_regs( void )
	363	{
	364	unsigned long phys = __PREG(GPLR) & PMD_MASK;
3169663a	365	unsigned long virt = (unsigned long)io_p2v(phys);
1da177e4 LT	366	int prot = PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_DOMAIN(DOMAIN_IO);
	367	pmd_t *pmd;
	368
a61c2332	369	pmd = pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt);
1da177e4 LT	370	*pmd = __pmd(phys \| prot);
	371	flush_pmd_entry(pmd);
	372	}
	373
	374	/*
	375	* Read System Configuration "Register"
	376	* (taken from "Intel StrongARM SA-1110 Microprocessor Development Board
	377	* User's Guide", section 4.4.1)
	378	*
	379	* This same scan is performed in arch/arm/boot/compressed/head-sa1100.S
	380	* to set up the serial port for decompression status messages. We
	381	* repeat it here because the kernel may not be loaded as a zImage, and
	382	* also because it's a hassle to communicate the SCR value to the kernel
	383	* from the decompressor.
	384	*
	385	* Note that IRQs are guaranteed to be disabled.
	386	*/
	387	static void __init get_assabet_scr(void)
	388	{
	389	unsigned long scr, i;
	390
	391	GPDR \|= 0x3fc; /* Configure GPIO 9:2 as outputs */
	392	GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */
	393	GPDR &= ~(0x3fc); /* Configure GPIO 9:2 as inputs */
2f3eca8b RK	394	for(i = 100; i--; ) /* Read GPIO 9:2 */
2f3eca8b RK	395	scr = GPLR;
1da177e4 LT	396	GPDR \|= 0x3fc; /* restore correct pin direction */
	397	scr &= 0x3fc; /* save as system configuration byte. */
	398	SCR_value = scr;
	399	}
	400
	401	static void __init
0744a3ee	402	fixup_assabet(struct tag tags, char cmdline, struct meminfo mi)
1da177e4 LT	403	{
	404	/* This must be done before any call to machine_has_neponset() */
	405	map_sa1100_gpio_regs();
	406	get_assabet_scr();
	407
	408	if (machine_has_neponset())
	409	printk("Neponset expansion board detected\n");
	410	}
	411
	412
	413	static void assabet_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
	414	{
	415	if (port->mapbase == _Ser1UTCR0) {
	416	if (state)
	417	ASSABET_BCR_clear(ASSABET_BCR_RS232EN \|
	418	ASSABET_BCR_COM_RTS \|
	419	ASSABET_BCR_COM_DTR);
	420	else
	421	ASSABET_BCR_set(ASSABET_BCR_RS232EN \|
	422	ASSABET_BCR_COM_RTS \|
	423	ASSABET_BCR_COM_DTR);
	424	}
	425	}
	426
	427	/*
	428	* Assabet uses COM_RTS and COM_DTR for both UART1 (com port)
	429	* and UART3 (radio module). We only handle them for UART1 here.
	430	*/
	431	static void assabet_set_mctrl(struct uart_port *port, u_int mctrl)
	432	{
	433	if (port->mapbase == _Ser1UTCR0) {
	434	u_int set = 0, clear = 0;
	435
	436	if (mctrl & TIOCM_RTS)
	437	clear \|= ASSABET_BCR_COM_RTS;
	438	else
	439	set \|= ASSABET_BCR_COM_RTS;
	440
	441	if (mctrl & TIOCM_DTR)
	442	clear \|= ASSABET_BCR_COM_DTR;
	443	else
	444	set \|= ASSABET_BCR_COM_DTR;
	445
	446	ASSABET_BCR_clear(clear);
	447	ASSABET_BCR_set(set);
	448	}
	449	}
	450
	451	static u_int assabet_get_mctrl(struct uart_port *port)
	452	{
	453	u_int ret = 0;
	454	u_int bsr = ASSABET_BSR;
	455
	456	/* need 2 reads to read current value */
	457	bsr = ASSABET_BSR;
	458
	459	if (port->mapbase == _Ser1UTCR0) {
	460	if (bsr & ASSABET_BSR_COM_DCD)
	461	ret \|= TIOCM_CD;
	462	if (bsr & ASSABET_BSR_COM_CTS)
	463	ret \|= TIOCM_CTS;
	464	if (bsr & ASSABET_BSR_COM_DSR)
	465	ret \|= TIOCM_DSR;
	466	} else if (port->mapbase == _Ser3UTCR0) {
467	if (bsr & ASSABET_BSR_RAD_DCD)
468	ret \|= TIOCM_CD;
469	if (bsr & ASSABET_BSR_RAD_CTS)
470	ret \|= TIOCM_CTS;
471	if (bsr & ASSABET_BSR_RAD_DSR)
472	ret \|= TIOCM_DSR;
473	if (bsr & ASSABET_BSR_RAD_RI)
474	ret \|= TIOCM_RI;
475	} else {
476	ret = TIOCM_CD \| TIOCM_CTS \| TIOCM_DSR;
477	}
478
479	return ret;
480	}
481
482	static struct sa1100_port_fns assabet_port_fns __initdata = {
483	.set_mctrl = assabet_set_mctrl,
484	.get_mctrl = assabet_get_mctrl,
485	.pm = assabet_uart_pm,
486	};
487
488	static struct map_desc assabet_io_desc[] __initdata = {
92519d82 DS	489	{ /* Board Control Register */
	490	.virtual = 0xf1000000,
	491	.pfn = __phys_to_pfn(0x12000000),
	492	.length = 0x00100000,
	493	.type = MT_DEVICE
	494	}, { /* MQ200 */
	495	.virtual = 0xf2800000,
	496	.pfn = __phys_to_pfn(0x4b800000),
	497	.length = 0x00800000,
	498	.type = MT_DEVICE
	499	}
1da177e4 LT	500	};
	501
	502	static void __init assabet_map_io(void)
	503	{
	504	sa1100_map_io();
	505	iotable_init(assabet_io_desc, ARRAY_SIZE(assabet_io_desc));
	506
	507	/*
	508	* Set SUS bit in SDCR0 so serial port 1 functions.
	509	* Its called GPCLKR0 in my SA1110 manual.
	510	*/
	511	Ser1SDCR0 \|= SDCR0_SUS;
	512
374da9da	513	if (!machine_has_neponset())
1da177e4	514	sa1100_register_uart_fns(&assabet_port_fns);
1da177e4 LT	515
	516	/*
	517	* When Neponset is attached, the first UART should be
	518	* UART3. That's what Angel is doing and many documents
	519	* are stating this.
	520	*
	521	* We do the Neponset mapping even if Neponset support
	522	* isn't compiled in so the user will still get something on
	523	* the expected physical serial port.
	524	*
	525	* We no longer do this; not all boot loaders support it,
	526	* and UART3 appears to be somewhat unreliable with blob.
	527	*/
	528	sa1100_register_uart(0, 1);
	529	sa1100_register_uart(2, 3);
	530	}
	531
	532
	533	MACHINE_START(ASSABET, "Intel-Assabet")
17f4425d	534	.atag_offset = 0x100,
e9dea0c6 RK	535	.fixup = fixup_assabet,
e9dea0c6 RK	536	.map_io = assabet_map_io,
f314f33b	537	.nr_irqs = SA1100_NR_IRQS,
e9dea0c6	538	.init_irq = sa1100_init_irq,
1da177e4 LT	539	.timer = &sa1100_timer,
1da177e4 LT	540	.init_machine = assabet_init,
7fea1ba5	541	.init_late = sa11x0_init_late,
e9107ab6 NP	542	#ifdef CONFIG_SA1111
	543	.dma_zone_size = SZ_1M,
	544	#endif
d9ca5839	545	.restart = sa11x0_restart,
1da177e4	546	MACHINE_END