[deliverable/linux.git] / arch / arm / mach-sa1100 / generic.c

/*
 * linux/arch/arm/mach-sa1100/generic.c
 *
 * Author: Nicolas Pitre
 *
 * Code common to all SA11x0 machines.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/pm.h>
#include <linux/cpufreq.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/irqchip/irq-sa11x0.h>

#include <video/sa1100fb.h>

#include <soc/sa1100/pwer.h>

#include <asm/div64.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <asm/irq.h>
#include <asm/system_misc.h>

#include <mach/hardware.h>
#include <mach/irqs.h>

#include "generic.h"
#include <clocksource/pxa.h>

unsigned int reset_status;
EXPORT_SYMBOL(reset_status);

#define NR_FREQS	16

/*
 * This table is setup for a 3.6864MHz Crystal.
 */
struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = {
	{ .frequency = 59000,	/*  59.0 MHz */},
	{ .frequency = 73700,	/*  73.7 MHz */},
	{ .frequency = 88500,	/*  88.5 MHz */},
	{ .frequency = 103200,	/* 103.2 MHz */},
	{ .frequency = 118000,	/* 118.0 MHz */},
	{ .frequency = 132700,	/* 132.7 MHz */},
	{ .frequency = 147500,	/* 147.5 MHz */},
	{ .frequency = 162200,	/* 162.2 MHz */},
	{ .frequency = 176900,	/* 176.9 MHz */},
	{ .frequency = 191700,	/* 191.7 MHz */},
	{ .frequency = 206400,	/* 206.4 MHz */},
	{ .frequency = 221200,	/* 221.2 MHz */},
	{ .frequency = 235900,	/* 235.9 MHz */},
	{ .frequency = 250700,	/* 250.7 MHz */},
	{ .frequency = 265400,	/* 265.4 MHz */},
	{ .frequency = 280200,	/* 280.2 MHz */},
	{ .frequency = CPUFREQ_TABLE_END, },
};

unsigned int sa11x0_getspeed(unsigned int cpu)
{
	if (cpu)
		return 0;
	return sa11x0_freq_table[PPCR & 0xf].frequency;
}

/*
 * Default power-off for SA1100
 */
static void sa1100_power_off(void)
{
	mdelay(100);
	local_irq_disable();
	/* disable internal oscillator, float CS lines */
	PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
	/* enable wake-up on GPIO0 (Assabet...) */
	PWER = GFER = GRER = 1;
	/*
	 * set scratchpad to zero, just in case it is used as a
	 * restart address by the bootloader.
	 */
	PSPR = 0;
	/* enter sleep mode */
	PMCR = PMCR_SF;
}

void sa11x0_restart(enum reboot_mode mode, const char *cmd)
{
	if (mode == REBOOT_SOFT) {
		/* Jump into ROM at address 0 */
		soft_restart(0);
	} else {
		/* Use on-chip reset capability */
		RSRR = RSRR_SWR;
	}
}

static void sa11x0_register_device(struct platform_device *dev, void *data)
{
	int err;
	dev->dev.platform_data = data;
	err = platform_device_register(dev);
	if (err)
		printk(KERN_ERR "Unable to register device %s: %d\n",
			dev->name, err);
}


static struct resource sa11x0udc_resources[] = {
	[0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
};

static u64 sa11x0udc_dma_mask = 0xffffffffUL;

static struct platform_device sa11x0udc_device = {
	.name		= "sa11x0-udc",
	.id		= -1,
	.dev		= {
		.dma_mask = &sa11x0udc_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0udc_resources),
	.resource	= sa11x0udc_resources,
};

static struct resource sa11x0uart1_resources[] = {
	[0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
};

static struct platform_device sa11x0uart1_device = {
	.name		= "sa11x0-uart",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(sa11x0uart1_resources),
	.resource	= sa11x0uart1_resources,
};

static struct resource sa11x0uart3_resources[] = {
	[0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
};

static struct platform_device sa11x0uart3_device = {
	.name		= "sa11x0-uart",
	.id		= 3,
	.num_resources	= ARRAY_SIZE(sa11x0uart3_resources),
	.resource	= sa11x0uart3_resources,
};

static struct resource sa11x0mcp_resources[] = {
	[0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
	[1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
	[2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
};

static u64 sa11x0mcp_dma_mask = 0xffffffffUL;

static struct platform_device sa11x0mcp_device = {
	.name		= "sa11x0-mcp",
	.id		= -1,
	.dev = {
		.dma_mask = &sa11x0mcp_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0mcp_resources),
	.resource	= sa11x0mcp_resources,
};

void __init sa11x0_ppc_configure_mcp(void)
{
	/* Setup the PPC unit for the MCP */
	PPDR &= ~PPC_RXD4;
	PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
	PSDR |= PPC_RXD4;
	PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
	PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
}

void sa11x0_register_mcp(struct mcp_plat_data *data)
{
	sa11x0_register_device(&sa11x0mcp_device, data);
}

static struct resource sa11x0ssp_resources[] = {
	[0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
};

static u64 sa11x0ssp_dma_mask = 0xffffffffUL;

static struct platform_device sa11x0ssp_device = {
	.name		= "sa11x0-ssp",
	.id		= -1,
	.dev = {
		.dma_mask = &sa11x0ssp_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0ssp_resources),
	.resource	= sa11x0ssp_resources,
};

static struct resource sa11x0fb_resources[] = {
	[0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_LCD),
};

static struct platform_device sa11x0fb_device = {
	.name		= "sa11x0-fb",
	.id		= -1,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0fb_resources),
	.resource	= sa11x0fb_resources,
};

void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
{
	sa11x0_register_device(&sa11x0fb_device, inf);
}

static struct platform_device sa11x0pcmcia_device = {
	.name		= "sa11x0-pcmcia",
	.id		= -1,
};

static struct platform_device sa11x0mtd_device = {
	.name		= "sa1100-mtd",
	.id		= -1,
};

void sa11x0_register_mtd(struct flash_platform_data *flash,
			 struct resource *res, int nr)
{
	flash->name = "sa1100";
	sa11x0mtd_device.resource = res;
	sa11x0mtd_device.num_resources = nr;
	sa11x0_register_device(&sa11x0mtd_device, flash);
}

static struct resource sa11x0ir_resources[] = {
	DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
	DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
	DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
	DEFINE_RES_IRQ(IRQ_Ser2ICP),
};

static struct platform_device sa11x0ir_device = {
	.name		= "sa11x0-ir",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(sa11x0ir_resources),
	.resource	= sa11x0ir_resources,
};

void sa11x0_register_irda(struct irda_platform_data *irda)
{
	sa11x0_register_device(&sa11x0ir_device, irda);
}

static struct resource sa1100_rtc_resources[] = {
	DEFINE_RES_MEM(0x90010000, 0x40),
	DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
	DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
};

static struct platform_device sa11x0rtc_device = {
	.name		= "sa1100-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(sa1100_rtc_resources),
	.resource	= sa1100_rtc_resources,
};

static struct resource sa11x0dma_resources[] = {
	DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
	DEFINE_RES_IRQ(IRQ_DMA0),
	DEFINE_RES_IRQ(IRQ_DMA1),
	DEFINE_RES_IRQ(IRQ_DMA2),
	DEFINE_RES_IRQ(IRQ_DMA3),
	DEFINE_RES_IRQ(IRQ_DMA4),
	DEFINE_RES_IRQ(IRQ_DMA5),
};

static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);

static struct platform_device sa11x0dma_device = {
	.name		= "sa11x0-dma",
	.id		= -1,
	.dev = {
		.dma_mask = &sa11x0dma_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0dma_resources),
	.resource	= sa11x0dma_resources,
};

static struct platform_device *sa11x0_devices[] __initdata = {
	&sa11x0udc_device,
	&sa11x0uart1_device,
	&sa11x0uart3_device,
	&sa11x0ssp_device,
	&sa11x0pcmcia_device,
	&sa11x0rtc_device,
	&sa11x0dma_device,
};

static int __init sa1100_init(void)
{
	pm_power_off = sa1100_power_off;
	return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
}

arch_initcall(sa1100_init);

void __init sa11x0_init_late(void)
{
	sa11x0_pm_init();
}

/*
 * Common I/O mapping:
 *
 * Typically, static virtual address mappings are as follow:
 *
 * 0xf0000000-0xf3ffffff:	miscellaneous stuff (CPLDs, etc.)
 * 0xf4000000-0xf4ffffff:	SA-1111
 * 0xf5000000-0xf5ffffff:	reserved (used by cache flushing area)
 * 0xf6000000-0xfffeffff:	reserved (internal SA1100 IO defined above)
 * 0xffff0000-0xffff0fff:	SA1100 exception vectors
 * 0xffff2000-0xffff2fff:	Minicache copy_user_page area
 *
 * Below 0xe8000000 is reserved for vm allocation.
 *
 * The machine specific code must provide the extra mapping beside the
 * default mapping provided here.
 */

static struct map_desc standard_io_desc[] __initdata = {
	{	/* PCM */
		.virtual	=  0xf8000000,
		.pfn		= __phys_to_pfn(0x80000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* SCM */
		.virtual	=  0xfa000000,
		.pfn		= __phys_to_pfn(0x90000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* MER */
		.virtual	=  0xfc000000,
		.pfn		= __phys_to_pfn(0xa0000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* LCD + DMA */
		.virtual	=  0xfe000000,
		.pfn		= __phys_to_pfn(0xb0000000),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	},
};

void __init sa1100_map_io(void)
{
	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
}

void __init sa1100_timer_init(void)
{
	pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000), 3686400);
}

static struct resource irq_resource =
	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");

void __init sa1100_init_irq(void)
{
	request_resource(&iomem_resource, &irq_resource);

	sa11x0_init_irq_nodt(IRQ_GPIO0_SC, irq_resource.start);

	sa1100_init_gpio();
}

/*
 * Disable the memory bus request/grant signals on the SA1110 to
 * ensure that we don't receive spurious memory requests.  We set
 * the MBGNT signal false to ensure the SA1111 doesn't own the
 * SDRAM bus.
 */
void sa1110_mb_disable(void)
{
	unsigned long flags;

	local_irq_save(flags);
	
	PGSR &= ~GPIO_MBGNT;
	GPCR = GPIO_MBGNT;
	GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;

	GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);

	local_irq_restore(flags);
}

/*
 * If the system is going to use the SA-1111 DMA engines, set up
 * the memory bus request/grant pins.
 */
void sa1110_mb_enable(void)
{
	unsigned long flags;

	local_irq_save(flags);

	PGSR &= ~GPIO_MBGNT;
	GPCR = GPIO_MBGNT;
	GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;

	GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
	TUCR |= TUCR_MR;

	local_irq_restore(flags);
}

int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on)
{
	if (on)
		PWER |= BIT(gpio);
	else
		PWER &= ~BIT(gpio);

	return 0;
}

int sa11x0_sc_set_wake(unsigned int irq, unsigned int on)
{
	if (BIT(irq) != IC_RTCAlrm)
		return -EINVAL;

	if (on)
		PWER |= PWER_RTC;
	else
		PWER &= ~PWER_RTC;

	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-sa1100/generic.c
	3	*
	4	* Author: Nicolas Pitre
	5	*
	6	* Code common to all SA11x0 machines.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
2f8163ba	12	#include <linux/gpio.h>
1da177e4 LT	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/delay.h>
7931d92f	17	#include <linux/dma-mapping.h>
1da177e4 LT	18	#include <linux/pm.h>
	19	#include <linux/cpufreq.h>
	20	#include <linux/ioport.h>
d052d1be	21	#include <linux/platform_device.h>
7b6d864b	22	#include <linux/reboot.h>
85e6f097	23	#include <linux/irqchip/irq-sa11x0.h>
1da177e4	24
e1b7a72a RK	25	#include <video/sa1100fb.h>
e1b7a72a RK	26
982b465a DES	27	#include <soc/sa1100/pwer.h>
982b465a DES	28
1da177e4	29	#include <asm/div64.h>
1da177e4	30	#include <asm/mach/map.h>
14e66f76	31	#include <asm/mach/flash.h>
1da177e4	32	#include <asm/irq.h>
9f97da78	33	#include <asm/system_misc.h>
1da177e4	34
f314f33b RH	35	#include <mach/hardware.h>
	36	#include <mach/irqs.h>
	37
1da177e4	38	#include "generic.h"
7a8ca0a0	39	#include <clocksource/pxa.h>
1da177e4	40
04fef228 EM	41	unsigned int reset_status;
	42	EXPORT_SYMBOL(reset_status);
	43
1da177e4 LT	44	#define NR_FREQS 16
	45
	46	/*
	47	* This table is setup for a 3.6864MHz Crystal.
	48	*/
22c8b4f1 VK	49	struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = {
	50	{ .frequency = 59000, /* 59.0 MHz */},
	51	{ .frequency = 73700, /* 73.7 MHz */},
	52	{ .frequency = 88500, /* 88.5 MHz */},
	53	{ .frequency = 103200, /* 103.2 MHz */},
	54	{ .frequency = 118000, /* 118.0 MHz */},
	55	{ .frequency = 132700, /* 132.7 MHz */},
	56	{ .frequency = 147500, /* 147.5 MHz */},
	57	{ .frequency = 162200, /* 162.2 MHz */},
	58	{ .frequency = 176900, /* 176.9 MHz */},
	59	{ .frequency = 191700, /* 191.7 MHz */},
	60	{ .frequency = 206400, /* 206.4 MHz */},
	61	{ .frequency = 221200, /* 221.2 MHz */},
	62	{ .frequency = 235900, /* 235.9 MHz */},
	63	{ .frequency = 250700, /* 250.7 MHz */},
	64	{ .frequency = 265400, /* 265.4 MHz */},
	65	{ .frequency = 280200, /* 280.2 MHz */},
	66	{ .frequency = CPUFREQ_TABLE_END, },
1da177e4 LT	67	};
1da177e4 LT	68
1da177e4 LT	69	unsigned int sa11x0_getspeed(unsigned int cpu)
	70	{
	71	if (cpu)
	72	return 0;
22c8b4f1	73	return sa11x0_freq_table[PPCR & 0xf].frequency;
1da177e4 LT	74	}
1da177e4 LT	75
1da177e4 LT	76	/*
	77	* Default power-off for SA1100
	78	*/
	79	static void sa1100_power_off(void)
	80	{
	81	mdelay(100);
	82	local_irq_disable();
	83	/* disable internal oscillator, float CS lines */
	84	PCFR = (PCFR_OPDE \| PCFR_FP \| PCFR_FS);
	85	/* enable wake-up on GPIO0 (Assabet...) */
	86	PWER = GFER = GRER = 1;
	87	/*
	88	* set scratchpad to zero, just in case it is used as a
	89	* restart address by the bootloader.
	90	*/
	91	PSPR = 0;
	92	/* enter sleep mode */
	93	PMCR = PMCR_SF;
	94	}
	95
7b6d864b	96	void sa11x0_restart(enum reboot_mode mode, const char *cmd)
d9ca5839	97	{
7b6d864b	98	if (mode == REBOOT_SOFT) {
d9ca5839 RK	99	/* Jump into ROM at address 0 */
	100	soft_restart(0);
	101	} else {
	102	/* Use on-chip reset capability */
	103	RSRR = RSRR_SWR;
	104	}
	105	}
	106
7a5b4e16 RK	107	static void sa11x0_register_device(struct platform_device dev, void data)
	108	{
	109	int err;
	110	dev->dev.platform_data = data;
	111	err = platform_device_register(dev);
	112	if (err)
	113	printk(KERN_ERR "Unable to register device %s: %d\n",
	114	dev->name, err);
	115	}
	116
	117
1da177e4	118	static struct resource sa11x0udc_resources[] = {
a181099e RK	119	[0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
a181099e RK	120	[1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
1da177e4 LT	121	};
	122
	123	static u64 sa11x0udc_dma_mask = 0xffffffffUL;
	124
	125	static struct platform_device sa11x0udc_device = {
	126	.name = "sa11x0-udc",
	127	.id = -1,
	128	.dev = {
	129	.dma_mask = &sa11x0udc_dma_mask,
	130	.coherent_dma_mask = 0xffffffff,
	131	},
	132	.num_resources = ARRAY_SIZE(sa11x0udc_resources),
	133	.resource = sa11x0udc_resources,
	134	};
	135
	136	static struct resource sa11x0uart1_resources[] = {
a181099e RK	137	[0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
a181099e RK	138	[1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
1da177e4 LT	139	};
	140
	141	static struct platform_device sa11x0uart1_device = {
	142	.name = "sa11x0-uart",
	143	.id = 1,
	144	.num_resources = ARRAY_SIZE(sa11x0uart1_resources),
	145	.resource = sa11x0uart1_resources,
	146	};
	147
	148	static struct resource sa11x0uart3_resources[] = {
a181099e RK	149	[0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
a181099e RK	150	[1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
1da177e4 LT	151	};
	152
	153	static struct platform_device sa11x0uart3_device = {
	154	.name = "sa11x0-uart",
	155	.id = 3,
	156	.num_resources = ARRAY_SIZE(sa11x0uart3_resources),
	157	.resource = sa11x0uart3_resources,
	158	};
	159
	160	static struct resource sa11x0mcp_resources[] = {
a181099e	161	[0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
7256ecc2 RK	162	[1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
7256ecc2 RK	163	[2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
1da177e4 LT	164	};
	165
	166	static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
	167
	168	static struct platform_device sa11x0mcp_device = {
	169	.name = "sa11x0-mcp",
	170	.id = -1,
	171	.dev = {
	172	.dma_mask = &sa11x0mcp_dma_mask,
	173	.coherent_dma_mask = 0xffffffff,
	174	},
	175	.num_resources = ARRAY_SIZE(sa11x0mcp_resources),
	176	.resource = sa11x0mcp_resources,
	177	};
	178
e36e26a8 RK	179	void __init sa11x0_ppc_configure_mcp(void)
	180	{
	181	/* Setup the PPC unit for the MCP */
	182	PPDR &= ~PPC_RXD4;
	183	PPDR \|= PPC_TXD4 \| PPC_SCLK \| PPC_SFRM;
	184	PSDR \|= PPC_RXD4;
	185	PSDR &= ~(PPC_TXD4 \| PPC_SCLK \| PPC_SFRM);
	186	PPSR &= ~(PPC_TXD4 \| PPC_SCLK \| PPC_SFRM);
	187	}
	188
7a5b4e16	189	void sa11x0_register_mcp(struct mcp_plat_data *data)
323cdfc1	190	{
7a5b4e16	191	sa11x0_register_device(&sa11x0mcp_device, data);
323cdfc1 RK	192	}
323cdfc1 RK	193
1da177e4	194	static struct resource sa11x0ssp_resources[] = {
a181099e RK	195	[0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
a181099e RK	196	[1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
1da177e4 LT	197	};
	198
	199	static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
	200
	201	static struct platform_device sa11x0ssp_device = {
	202	.name = "sa11x0-ssp",
	203	.id = -1,
	204	.dev = {
	205	.dma_mask = &sa11x0ssp_dma_mask,
	206	.coherent_dma_mask = 0xffffffff,
	207	},
	208	.num_resources = ARRAY_SIZE(sa11x0ssp_resources),
	209	.resource = sa11x0ssp_resources,
	210	};
	211
	212	static struct resource sa11x0fb_resources[] = {
a181099e RK	213	[0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
a181099e RK	214	[1] = DEFINE_RES_IRQ(IRQ_LCD),
1da177e4 LT	215	};
	216
	217	static struct platform_device sa11x0fb_device = {
	218	.name = "sa11x0-fb",
	219	.id = -1,
	220	.dev = {
	221	.coherent_dma_mask = 0xffffffff,
	222	},
	223	.num_resources = ARRAY_SIZE(sa11x0fb_resources),
	224	.resource = sa11x0fb_resources,
	225	};
	226
e1b7a72a RK	227	void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
	228	{
	229	sa11x0_register_device(&sa11x0fb_device, inf);
	230	}
	231
1da177e4 LT	232	static struct platform_device sa11x0pcmcia_device = {
	233	.name = "sa11x0-pcmcia",
	234	.id = -1,
	235	};
	236
	237	static struct platform_device sa11x0mtd_device = {
bcc8f3e0	238	.name = "sa1100-mtd",
1da177e4 LT	239	.id = -1,
	240	};
	241
7a5b4e16 RK	242	void sa11x0_register_mtd(struct flash_platform_data *flash,
7a5b4e16 RK	243	struct resource *res, int nr)
1da177e4	244	{
14e66f76	245	flash->name = "sa1100";
1da177e4 LT	246	sa11x0mtd_device.resource = res;
1da177e4 LT	247	sa11x0mtd_device.num_resources = nr;
7a5b4e16	248	sa11x0_register_device(&sa11x0mtd_device, flash);
1da177e4 LT	249	}
	250
	251	static struct resource sa11x0ir_resources[] = {
a181099e RK	252	DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
	253	DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
	254	DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
	255	DEFINE_RES_IRQ(IRQ_Ser2ICP),
1da177e4 LT	256	};
	257
	258	static struct platform_device sa11x0ir_device = {
	259	.name = "sa11x0-ir",
	260	.id = -1,
	261	.num_resources = ARRAY_SIZE(sa11x0ir_resources),
	262	.resource = sa11x0ir_resources,
	263	};
	264
7a5b4e16	265	void sa11x0_register_irda(struct irda_platform_data *irda)
1da177e4	266	{
7a5b4e16	267	sa11x0_register_device(&sa11x0ir_device, irda);
1da177e4 LT	268	}
1da177e4 LT	269
3888c090	270	static struct resource sa1100_rtc_resources[] = {
9f9d27e3	271	DEFINE_RES_MEM(0x90010000, 0x40),
3888c090 HZ	272	DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
	273	DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
	274	};
	275
e842f1c8 RP	276	static struct platform_device sa11x0rtc_device = {
	277	.name = "sa1100-rtc",
	278	.id = -1,
3888c090 HZ	279	.num_resources = ARRAY_SIZE(sa1100_rtc_resources),
3888c090 HZ	280	.resource = sa1100_rtc_resources,
e842f1c8 RP	281	};
e842f1c8 RP	282
7931d92f	283	static struct resource sa11x0dma_resources[] = {
c2132010	284	DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
7931d92f RK	285	DEFINE_RES_IRQ(IRQ_DMA0),
	286	DEFINE_RES_IRQ(IRQ_DMA1),
	287	DEFINE_RES_IRQ(IRQ_DMA2),
	288	DEFINE_RES_IRQ(IRQ_DMA3),
	289	DEFINE_RES_IRQ(IRQ_DMA4),
	290	DEFINE_RES_IRQ(IRQ_DMA5),
	291	};
	292
	293	static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
	294
	295	static struct platform_device sa11x0dma_device = {
	296	.name = "sa11x0-dma",
	297	.id = -1,
	298	.dev = {
	299	.dma_mask = &sa11x0dma_dma_mask,
	300	.coherent_dma_mask = 0xffffffff,
	301	},
	302	.num_resources = ARRAY_SIZE(sa11x0dma_resources),
	303	.resource = sa11x0dma_resources,
	304	};
	305
1da177e4 LT	306	static struct platform_device *sa11x0_devices[] __initdata = {
	307	&sa11x0udc_device,
	308	&sa11x0uart1_device,
	309	&sa11x0uart3_device,
1da177e4 LT	310	&sa11x0ssp_device,
1da177e4 LT	311	&sa11x0pcmcia_device,
e842f1c8	312	&sa11x0rtc_device,
7931d92f	313	&sa11x0dma_device,
1da177e4 LT	314	};
	315
	316	static int __init sa1100_init(void)
	317	{
	318	pm_power_off = sa1100_power_off;
1da177e4 LT	319	return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
	320	}
	321
	322	arch_initcall(sa1100_init);
	323
7fea1ba5 SG	324	void __init sa11x0_init_late(void)
	325	{
	326	sa11x0_pm_init();
	327	}
1da177e4 LT	328
	329	/*
	330	* Common I/O mapping:
	331	*
	332	* Typically, static virtual address mappings are as follow:
	333	*
	334	* 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
	335	* 0xf4000000-0xf4ffffff: SA-1111
	336	* 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
	337	* 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
	338	* 0xffff0000-0xffff0fff: SA1100 exception vectors
	339	* 0xffff2000-0xffff2fff: Minicache copy_user_page area
	340	*
	341	* Below 0xe8000000 is reserved for vm allocation.
	342	*
	343	* The machine specific code must provide the extra mapping beside the
	344	* default mapping provided here.
	345	*/
	346
	347	static struct map_desc standard_io_desc[] __initdata = {
bda03086	348	{ /* PCM */
92519d82 DS	349	.virtual = 0xf8000000,
	350	.pfn = __phys_to_pfn(0x80000000),
	351	.length = 0x00100000,
	352	.type = MT_DEVICE
	353	}, { /* SCM */
	354	.virtual = 0xfa000000,
	355	.pfn = __phys_to_pfn(0x90000000),
	356	.length = 0x00100000,
	357	.type = MT_DEVICE
	358	}, { /* MER */
	359	.virtual = 0xfc000000,
	360	.pfn = __phys_to_pfn(0xa0000000),
	361	.length = 0x00100000,
	362	.type = MT_DEVICE
	363	}, { /* LCD + DMA */
	364	.virtual = 0xfe000000,
	365	.pfn = __phys_to_pfn(0xb0000000),
	366	.length = 0x00200000,
	367	.type = MT_DEVICE
	368	},
1da177e4 LT	369	};
	370
	371	void __init sa1100_map_io(void)
	372	{
	373	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
	374	}
	375
7a8ca0a0 DES	376	void __init sa1100_timer_init(void)
	377	{
	378	pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000), 3686400);
	379	}
	380
85e6f097 DES	381	static struct resource irq_resource =
	382	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
	383
	384	void __init sa1100_init_irq(void)
	385	{
	386	request_resource(&iomem_resource, &irq_resource);
	387
	388	sa11x0_init_irq_nodt(IRQ_GPIO0_SC, irq_resource.start);
	389
	390	sa1100_init_gpio();
	391	}
	392
1da177e4 LT	393	/*
	394	* Disable the memory bus request/grant signals on the SA1110 to
	395	* ensure that we don't receive spurious memory requests. We set
	396	* the MBGNT signal false to ensure the SA1111 doesn't own the
	397	* SDRAM bus.
	398	*/
80ea2065	399	void sa1110_mb_disable(void)
1da177e4 LT	400	{
	401	unsigned long flags;
	402
	403	local_irq_save(flags);
	404
	405	PGSR &= ~GPIO_MBGNT;
	406	GPCR = GPIO_MBGNT;
	407	GPDR = (GPDR & ~GPIO_MBREQ) \| GPIO_MBGNT;
	408
	409	GAFR &= ~(GPIO_MBGNT \| GPIO_MBREQ);
	410
	411	local_irq_restore(flags);
	412	}
	413
	414	/*
	415	* If the system is going to use the SA-1111 DMA engines, set up
	416	* the memory bus request/grant pins.
	417	*/
80ea2065	418	void sa1110_mb_enable(void)
1da177e4 LT	419	{
	420	unsigned long flags;
	421
	422	local_irq_save(flags);
	423
	424	PGSR &= ~GPIO_MBGNT;
	425	GPCR = GPIO_MBGNT;
	426	GPDR = (GPDR & ~GPIO_MBREQ) \| GPIO_MBGNT;
	427
	428	GAFR \|= (GPIO_MBGNT \| GPIO_MBREQ);
	429	TUCR \|= TUCR_MR;
	430
	431	local_irq_restore(flags);
	432	}
	433
982b465a DES	434	int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on)
	435	{
	436	if (on)
	437	PWER \|= BIT(gpio);
	438	else
	439	PWER &= ~BIT(gpio);
	440
	441	return 0;
	442	}
	443
	444	int sa11x0_sc_set_wake(unsigned int irq, unsigned int on)
	445	{
	446	if (BIT(irq) != IC_RTCAlrm)
	447	return -EINVAL;
	448
	449	if (on)
	450	PWER \|= PWER_RTC;
	451	else
	452	PWER &= ~PWER_RTC;
	453
	454	return 0;
	455	}