[deliverable/linux.git] / arch / arm / mach-sa1100 / irq.c

/*
 * linux/arch/arm/mach-sa1100/irq.c
 *
 * Copyright (C) 1999-2001 Nicolas Pitre
 *
 * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/ioport.h>
#include <linux/syscore_ops.h>

#include <mach/hardware.h>
#include <mach/irqs.h>
#include <asm/mach/irq.h>

#include "generic.h"


/*
 * SA1100 GPIO edge detection for IRQs:
 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
 * Use this instead of directly setting GRER/GFER.
 */
static int GPIO_IRQ_rising_edge;
static int GPIO_IRQ_falling_edge;
static int GPIO_IRQ_mask = (1 << 11) - 1;

/*
 * To get the GPIO number from an IRQ number
 */
#define GPIO_11_27_IRQ(i)	((i) - 21)
#define GPIO11_27_MASK(irq)	(1 << GPIO_11_27_IRQ(irq))

static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
{
	unsigned int mask;

	if (d->irq <= 10)
		mask = 1 << d->irq;
	else
		mask = GPIO11_27_MASK(d->irq);

	if (type == IRQ_TYPE_PROBE) {
		if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
			return 0;
		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	}

	if (type & IRQ_TYPE_EDGE_RISING) {
		GPIO_IRQ_rising_edge |= mask;
	} else
		GPIO_IRQ_rising_edge &= ~mask;
	if (type & IRQ_TYPE_EDGE_FALLING) {
		GPIO_IRQ_falling_edge |= mask;
	} else
		GPIO_IRQ_falling_edge &= ~mask;

	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;

	return 0;
}

/*
 * GPIO IRQs must be acknowledged.  This is for IRQs from 0 to 10.
 */
static void sa1100_low_gpio_ack(struct irq_data *d)
{
	GEDR = (1 << d->irq);
}

static void sa1100_low_gpio_mask(struct irq_data *d)
{
	ICMR &= ~(1 << d->irq);
}

static void sa1100_low_gpio_unmask(struct irq_data *d)
{
	ICMR |= 1 << d->irq;
}

static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
{
	if (on)
		PWER |= 1 << d->irq;
	else
		PWER &= ~(1 << d->irq);
	return 0;
}

static struct irq_chip sa1100_low_gpio_chip = {
	.name		= "GPIO-l",
	.irq_ack	= sa1100_low_gpio_ack,
	.irq_mask	= sa1100_low_gpio_mask,
	.irq_unmask	= sa1100_low_gpio_unmask,
	.irq_set_type	= sa1100_gpio_type,
	.irq_set_wake	= sa1100_low_gpio_wake,
};

/*
 * IRQ11 (GPIO11 through 27) handler.  We enter here with the
 * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
 * and call the handler.
 */
static void
sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned int mask;

	mask = GEDR & 0xfffff800;
	do {
		/*
		 * clear down all currently active IRQ sources.
		 * We will be processing them all.
		 */
		GEDR = mask;

		irq = IRQ_GPIO11;
		mask >>= 11;
		do {
			if (mask & 1)
				generic_handle_irq(irq);
			mask >>= 1;
			irq++;
		} while (mask);

		mask = GEDR & 0xfffff800;
	} while (mask);
}

/*
 * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
 * In addition, the IRQs are all collected up into one bit in the
 * interrupt controller registers.
 */
static void sa1100_high_gpio_ack(struct irq_data *d)
{
	unsigned int mask = GPIO11_27_MASK(d->irq);

	GEDR = mask;
}

static void sa1100_high_gpio_mask(struct irq_data *d)
{
	unsigned int mask = GPIO11_27_MASK(d->irq);

	GPIO_IRQ_mask &= ~mask;

	GRER &= ~mask;
	GFER &= ~mask;
}

static void sa1100_high_gpio_unmask(struct irq_data *d)
{
	unsigned int mask = GPIO11_27_MASK(d->irq);

	GPIO_IRQ_mask |= mask;

	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
}

static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
{
	if (on)
		PWER |= GPIO11_27_MASK(d->irq);
	else
		PWER &= ~GPIO11_27_MASK(d->irq);
	return 0;
}

static struct irq_chip sa1100_high_gpio_chip = {
	.name		= "GPIO-h",
	.irq_ack	= sa1100_high_gpio_ack,
	.irq_mask	= sa1100_high_gpio_mask,
	.irq_unmask	= sa1100_high_gpio_unmask,
	.irq_set_type	= sa1100_gpio_type,
	.irq_set_wake	= sa1100_high_gpio_wake,
};

/*
 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
 * this is for internal IRQs i.e. from 11 to 31.
 */
static void sa1100_mask_irq(struct irq_data *d)
{
	ICMR &= ~(1 << d->irq);
}

static void sa1100_unmask_irq(struct irq_data *d)
{
	ICMR |= (1 << d->irq);
}

/*
 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
 */
static int sa1100_set_wake(struct irq_data *d, unsigned int on)
{
	if (d->irq == IRQ_RTCAlrm) {
		if (on)
			PWER |= PWER_RTC;
		else
			PWER &= ~PWER_RTC;
		return 0;
	}
	return -EINVAL;
}

static struct irq_chip sa1100_normal_chip = {
	.name		= "SC",
	.irq_ack	= sa1100_mask_irq,
	.irq_mask	= sa1100_mask_irq,
	.irq_unmask	= sa1100_unmask_irq,
	.irq_set_wake	= sa1100_set_wake,
};

static struct resource irq_resource =
	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");

static struct sa1100irq_state {
	unsigned int	saved;
	unsigned int	icmr;
	unsigned int	iclr;
	unsigned int	iccr;
} sa1100irq_state;

static int sa1100irq_suspend(void)
{
	struct sa1100irq_state *st = &sa1100irq_state;

	st->saved = 1;
	st->icmr = ICMR;
	st->iclr = ICLR;
	st->iccr = ICCR;

	/*
	 * Disable all GPIO-based interrupts.
	 */
	ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
		  IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
		  IC_GPIO1|IC_GPIO0);

	/*
	 * Set the appropriate edges for wakeup.
	 */
	GRER = PWER & GPIO_IRQ_rising_edge;
	GFER = PWER & GPIO_IRQ_falling_edge;
	
	/*
	 * Clear any pending GPIO interrupts.
	 */
	GEDR = GEDR;

	return 0;
}

static void sa1100irq_resume(void)
{
	struct sa1100irq_state *st = &sa1100irq_state;

	if (st->saved) {
		ICCR = st->iccr;
		ICLR = st->iclr;

		GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
		GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;

		ICMR = st->icmr;
	}
}

static struct syscore_ops sa1100irq_syscore_ops = {
	.suspend	= sa1100irq_suspend,
	.resume		= sa1100irq_resume,
};

static int __init sa1100irq_init_devicefs(void)
{
	register_syscore_ops(&sa1100irq_syscore_ops);
	return 0;
}

device_initcall(sa1100irq_init_devicefs);

void __init sa1100_init_irq(void)
{
	unsigned int irq;

	request_resource(&iomem_resource, &irq_resource);

	/* disable all IRQs */
	ICMR = 0;

	/* all IRQs are IRQ, not FIQ */
	ICLR = 0;

	/* clear all GPIO edge detects */
	GFER = 0;
	GRER = 0;
	GEDR = -1;

	/*
	 * Whatever the doc says, this has to be set for the wait-on-irq
	 * instruction to work... on a SA1100 rev 9 at least.
	 */
	ICCR = 1;

	for (irq = 0; irq <= 10; irq++) {
		irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
					 handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	for (irq = 12; irq <= 31; irq++) {
		irq_set_chip_and_handler(irq, &sa1100_normal_chip,
					 handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	for (irq = 32; irq <= 48; irq++) {
		irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
					 handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	/*
	 * Install handler for GPIO 11-27 edge detect interrupts
	 */
	irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
	irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);

	sa1100_init_gpio();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-sa1100/irq.c
	3	*
	4	* Copyright (C) 1999-2001 Nicolas Pitre
	5	*
	6	* Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12	#include <linux/init.h>
	13	#include <linux/module.h>
119c641c	14	#include <linux/interrupt.h>
3169663a	15	#include <linux/io.h>
119c641c	16	#include <linux/irq.h>
1da177e4	17	#include <linux/ioport.h>
90533980	18	#include <linux/syscore_ops.h>
1da177e4	19
a09e64fb	20	#include <mach/hardware.h>
f314f33b	21	#include <mach/irqs.h>
1da177e4 LT	22	#include <asm/mach/irq.h>
	23
	24	#include "generic.h"
	25
	26
	27	/*
	28	* SA1100 GPIO edge detection for IRQs:
	29	* IRQs are generated on Falling-Edge, Rising-Edge, or both.
	30	* Use this instead of directly setting GRER/GFER.
	31	*/
	32	static int GPIO_IRQ_rising_edge;
	33	static int GPIO_IRQ_falling_edge;
	34	static int GPIO_IRQ_mask = (1 << 11) - 1;
	35
	36	/*
	37	* To get the GPIO number from an IRQ number
	38	*/
	39	#define GPIO_11_27_IRQ(i) ((i) - 21)
	40	#define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq))
	41
c4e8964e	42	static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
1da177e4 LT	43	{
	44	unsigned int mask;
	45
c4e8964e LB	46	if (d->irq <= 10)
c4e8964e LB	47	mask = 1 << d->irq;
1da177e4	48	else
c4e8964e	49	mask = GPIO11_27_MASK(d->irq);
1da177e4	50
6cab4860	51	if (type == IRQ_TYPE_PROBE) {
1da177e4 LT	52	if ((GPIO_IRQ_rising_edge \| GPIO_IRQ_falling_edge) & mask)
1da177e4 LT	53	return 0;
6cab4860	54	type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
1da177e4 LT	55	}
1da177e4 LT	56
6cab4860	57	if (type & IRQ_TYPE_EDGE_RISING) {
1da177e4 LT	58	GPIO_IRQ_rising_edge \|= mask;
	59	} else
	60	GPIO_IRQ_rising_edge &= ~mask;
6cab4860	61	if (type & IRQ_TYPE_EDGE_FALLING) {
1da177e4 LT	62	GPIO_IRQ_falling_edge \|= mask;
	63	} else
	64	GPIO_IRQ_falling_edge &= ~mask;
	65
	66	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	67	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
	68
	69	return 0;
	70	}
	71
	72	/*
	73	* GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10.
	74	*/
c4e8964e	75	static void sa1100_low_gpio_ack(struct irq_data *d)
1da177e4	76	{
c4e8964e	77	GEDR = (1 << d->irq);
1da177e4 LT	78	}
1da177e4 LT	79
c4e8964e	80	static void sa1100_low_gpio_mask(struct irq_data *d)
1da177e4	81	{
c4e8964e	82	ICMR &= ~(1 << d->irq);
1da177e4 LT	83	}
1da177e4 LT	84
c4e8964e	85	static void sa1100_low_gpio_unmask(struct irq_data *d)
1da177e4	86	{
c4e8964e	87	ICMR \|= 1 << d->irq;
1da177e4 LT	88	}
1da177e4 LT	89
c4e8964e	90	static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
1da177e4 LT	91	{
1da177e4 LT	92	if (on)
c4e8964e	93	PWER \|= 1 << d->irq;
1da177e4	94	else
c4e8964e	95	PWER &= ~(1 << d->irq);
1da177e4 LT	96	return 0;
	97	}
	98
38c677cb DB	99	static struct irq_chip sa1100_low_gpio_chip = {
38c677cb DB	100	.name = "GPIO-l",
c4e8964e LB	101	.irq_ack = sa1100_low_gpio_ack,
	102	.irq_mask = sa1100_low_gpio_mask,
	103	.irq_unmask = sa1100_low_gpio_unmask,
	104	.irq_set_type = sa1100_gpio_type,
	105	.irq_set_wake = sa1100_low_gpio_wake,
1da177e4 LT	106	};
	107
	108	/*
	109	* IRQ11 (GPIO11 through 27) handler. We enter here with the
	110	* irq_controller_lock held, and IRQs disabled. Decode the IRQ
	111	* and call the handler.
	112	*/
	113	static void
10dd5ce2	114	sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
1da177e4 LT	115	{
	116	unsigned int mask;
	117
	118	mask = GEDR & 0xfffff800;
	119	do {
	120	/*
	121	* clear down all currently active IRQ sources.
	122	* We will be processing them all.
	123	*/
	124	GEDR = mask;
	125
	126	irq = IRQ_GPIO11;
1da177e4 LT	127	mask >>= 11;
	128	do {
	129	if (mask & 1)
d8aa0251	130	generic_handle_irq(irq);
1da177e4 LT	131	mask >>= 1;
1da177e4 LT	132	irq++;
1da177e4 LT	133	} while (mask);
	134
	135	mask = GEDR & 0xfffff800;
	136	} while (mask);
	137	}
	138
	139	/*
	140	* Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
	141	* In addition, the IRQs are all collected up into one bit in the
	142	* interrupt controller registers.
	143	*/
c4e8964e	144	static void sa1100_high_gpio_ack(struct irq_data *d)
1da177e4	145	{
c4e8964e	146	unsigned int mask = GPIO11_27_MASK(d->irq);
1da177e4 LT	147
	148	GEDR = mask;
	149	}
	150
c4e8964e	151	static void sa1100_high_gpio_mask(struct irq_data *d)
1da177e4	152	{
c4e8964e	153	unsigned int mask = GPIO11_27_MASK(d->irq);
1da177e4 LT	154
	155	GPIO_IRQ_mask &= ~mask;
	156
	157	GRER &= ~mask;
	158	GFER &= ~mask;
	159	}
	160
c4e8964e	161	static void sa1100_high_gpio_unmask(struct irq_data *d)
1da177e4	162	{
c4e8964e	163	unsigned int mask = GPIO11_27_MASK(d->irq);
1da177e4 LT	164
	165	GPIO_IRQ_mask \|= mask;
	166
	167	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	168	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
	169	}
	170
c4e8964e	171	static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
1da177e4 LT	172	{
1da177e4 LT	173	if (on)
c4e8964e	174	PWER \|= GPIO11_27_MASK(d->irq);
1da177e4	175	else
c4e8964e	176	PWER &= ~GPIO11_27_MASK(d->irq);
1da177e4 LT	177	return 0;
	178	}
	179
38c677cb DB	180	static struct irq_chip sa1100_high_gpio_chip = {
38c677cb DB	181	.name = "GPIO-h",
c4e8964e LB	182	.irq_ack = sa1100_high_gpio_ack,
	183	.irq_mask = sa1100_high_gpio_mask,
	184	.irq_unmask = sa1100_high_gpio_unmask,
	185	.irq_set_type = sa1100_gpio_type,
	186	.irq_set_wake = sa1100_high_gpio_wake,
1da177e4 LT	187	};
	188
	189	/*
	190	* We don't need to ACK IRQs on the SA1100 unless they're GPIOs
	191	* this is for internal IRQs i.e. from 11 to 31.
	192	*/
c4e8964e	193	static void sa1100_mask_irq(struct irq_data *d)
1da177e4	194	{
c4e8964e	195	ICMR &= ~(1 << d->irq);
1da177e4 LT	196	}
1da177e4 LT	197
c4e8964e	198	static void sa1100_unmask_irq(struct irq_data *d)
1da177e4	199	{
c4e8964e	200	ICMR \|= (1 << d->irq);
1da177e4 LT	201	}
1da177e4 LT	202
19ca5d27 RK	203	/*
	204	* Apart form GPIOs, only the RTC alarm can be a wakeup event.
	205	*/
c4e8964e	206	static int sa1100_set_wake(struct irq_data *d, unsigned int on)
19ca5d27	207	{
c4e8964e	208	if (d->irq == IRQ_RTCAlrm) {
19ca5d27 RK	209	if (on)
	210	PWER \|= PWER_RTC;
	211	else
	212	PWER &= ~PWER_RTC;
	213	return 0;
	214	}
	215	return -EINVAL;
	216	}
	217
38c677cb DB	218	static struct irq_chip sa1100_normal_chip = {
38c677cb DB	219	.name = "SC",
c4e8964e LB	220	.irq_ack = sa1100_mask_irq,
	221	.irq_mask = sa1100_mask_irq,
	222	.irq_unmask = sa1100_unmask_irq,
	223	.irq_set_wake = sa1100_set_wake,
1da177e4 LT	224	};
1da177e4 LT	225
a181099e RK	226	static struct resource irq_resource =
a181099e RK	227	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
1da177e4 LT	228
	229	static struct sa1100irq_state {
	230	unsigned int saved;
	231	unsigned int icmr;
	232	unsigned int iclr;
	233	unsigned int iccr;
	234	} sa1100irq_state;
	235
90533980	236	static int sa1100irq_suspend(void)
1da177e4 LT	237	{
	238	struct sa1100irq_state *st = &sa1100irq_state;
	239
	240	st->saved = 1;
	241	st->icmr = ICMR;
	242	st->iclr = ICLR;
	243	st->iccr = ICCR;
	244
	245	/*
	246	* Disable all GPIO-based interrupts.
	247	*/
	248	ICMR &= ~(IC_GPIO11_27\|IC_GPIO10\|IC_GPIO9\|IC_GPIO8\|IC_GPIO7\|
	249	IC_GPIO6\|IC_GPIO5\|IC_GPIO4\|IC_GPIO3\|IC_GPIO2\|
	250	IC_GPIO1\|IC_GPIO0);
	251
	252	/*
	253	* Set the appropriate edges for wakeup.
	254	*/
	255	GRER = PWER & GPIO_IRQ_rising_edge;
	256	GFER = PWER & GPIO_IRQ_falling_edge;
	257
	258	/*
	259	* Clear any pending GPIO interrupts.
	260	*/
	261	GEDR = GEDR;
	262
	263	return 0;
	264	}
	265
90533980	266	static void sa1100irq_resume(void)
1da177e4 LT	267	{
	268	struct sa1100irq_state *st = &sa1100irq_state;
	269
	270	if (st->saved) {
	271	ICCR = st->iccr;
	272	ICLR = st->iclr;
	273
	274	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	275	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
	276
	277	ICMR = st->icmr;
	278	}
1da177e4 LT	279	}
1da177e4 LT	280
90533980	281	static struct syscore_ops sa1100irq_syscore_ops = {
1da177e4 LT	282	.suspend = sa1100irq_suspend,
	283	.resume = sa1100irq_resume,
	284	};
	285
1da177e4 LT	286	static int __init sa1100irq_init_devicefs(void)
1da177e4 LT	287	{
90533980 RW	288	register_syscore_ops(&sa1100irq_syscore_ops);
90533980 RW	289	return 0;
1da177e4 LT	290	}
	291
	292	device_initcall(sa1100irq_init_devicefs);
	293
	294	void __init sa1100_init_irq(void)
	295	{
	296	unsigned int irq;
	297
	298	request_resource(&iomem_resource, &irq_resource);
	299
	300	/* disable all IRQs */
	301	ICMR = 0;
	302
	303	/* all IRQs are IRQ, not FIQ */
	304	ICLR = 0;
	305
	306	/* clear all GPIO edge detects */
	307	GFER = 0;
	308	GRER = 0;
	309	GEDR = -1;
	310
	311	/*
	312	* Whatever the doc says, this has to be set for the wait-on-irq
	313	* instruction to work... on a SA1100 rev 9 at least.
	314	*/
	315	ICCR = 1;
	316
	317	for (irq = 0; irq <= 10; irq++) {
f38c02f3 TG	318	irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
f38c02f3 TG	319	handle_edge_irq);
1da177e4 LT	320	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	321	}
	322
	323	for (irq = 12; irq <= 31; irq++) {
f38c02f3 TG	324	irq_set_chip_and_handler(irq, &sa1100_normal_chip,
f38c02f3 TG	325	handle_level_irq);
1da177e4 LT	326	set_irq_flags(irq, IRQF_VALID);
	327	}
	328
	329	for (irq = 32; irq <= 48; irq++) {
f38c02f3 TG	330	irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
f38c02f3 TG	331	handle_edge_irq);
1da177e4 LT	332	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	333	}
	334
	335	/*
	336	* Install handler for GPIO 11-27 edge detect interrupts
	337	*/
6845664a TG	338	irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
6845664a TG	339	irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
45528e38 DB	340
45528e38 DB	341	sa1100_init_gpio();
1da177e4	342	}