[deliverable/linux.git] / arch / arm / mach-sa1100 / irq.c

/*
 * linux/arch/arm/mach-sa1100/irq.c
 *
 * Copyright (C) 1999-2001 Nicolas Pitre
 *
 * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/ioport.h>
#include <linux/syscore_ops.h>

#include <mach/hardware.h>
#include <mach/irqs.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>

#include "generic.h"


/*
 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
 * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
 */
static void sa1100_mask_irq(struct irq_data *d)
{
	ICMR &= ~BIT(d->hwirq);
}

static void sa1100_unmask_irq(struct irq_data *d)
{
	ICMR |= BIT(d->hwirq);
}

/*
 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
 */
static int sa1100_set_wake(struct irq_data *d, unsigned int on)
{
	if (BIT(d->hwirq) == IC_RTCAlrm) {
		if (on)
			PWER |= PWER_RTC;
		else
			PWER &= ~PWER_RTC;
		return 0;
	}
	return -EINVAL;
}

static struct irq_chip sa1100_normal_chip = {
	.name		= "SC",
	.irq_ack	= sa1100_mask_irq,
	.irq_mask	= sa1100_mask_irq,
	.irq_unmask	= sa1100_unmask_irq,
	.irq_set_wake	= sa1100_set_wake,
};

static int sa1100_normal_irqdomain_map(struct irq_domain *d,
		unsigned int irq, irq_hw_number_t hwirq)
{
	irq_set_chip_and_handler(irq, &sa1100_normal_chip,
				 handle_level_irq);
	set_irq_flags(irq, IRQF_VALID);

	return 0;
}

static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
	.map = sa1100_normal_irqdomain_map,
	.xlate = irq_domain_xlate_onetwocell,
};

static struct irq_domain *sa1100_normal_irqdomain;

static struct resource irq_resource =
	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");

static struct sa1100irq_state {
	unsigned int	saved;
	unsigned int	icmr;
	unsigned int	iclr;
	unsigned int	iccr;
} sa1100irq_state;

static int sa1100irq_suspend(void)
{
	struct sa1100irq_state *st = &sa1100irq_state;

	st->saved = 1;
	st->icmr = ICMR;
	st->iclr = ICLR;
	st->iccr = ICCR;

	/*
	 * Disable all GPIO-based interrupts.
	 */
	ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
		  IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
		  IC_GPIO1|IC_GPIO0);

	return 0;
}

static void sa1100irq_resume(void)
{
	struct sa1100irq_state *st = &sa1100irq_state;

	if (st->saved) {
		ICCR = st->iccr;
		ICLR = st->iclr;

		ICMR = st->icmr;
	}
}

static struct syscore_ops sa1100irq_syscore_ops = {
	.suspend	= sa1100irq_suspend,
	.resume		= sa1100irq_resume,
};

static int __init sa1100irq_init_devicefs(void)
{
	register_syscore_ops(&sa1100irq_syscore_ops);
	return 0;
}

device_initcall(sa1100irq_init_devicefs);

static asmlinkage void __exception_irq_entry
sa1100_handle_irq(struct pt_regs *regs)
{
	uint32_t icip, icmr, mask;

	do {
		icip = (ICIP);
		icmr = (ICMR);
		mask = icip & icmr;

		if (mask == 0)
			break;

		handle_domain_irq(sa1100_normal_irqdomain,
				ffs(mask) - 1, regs);
	} while (1);
}

void __init sa1100_init_irq(void)
{
	request_resource(&iomem_resource, &irq_resource);

	/* disable all IRQs */
	ICMR = 0;

	/* all IRQs are IRQ, not FIQ */
	ICLR = 0;

	/*
	 * Whatever the doc says, this has to be set for the wait-on-irq
	 * instruction to work... on a SA1100 rev 9 at least.
	 */
	ICCR = 1;

	sa1100_normal_irqdomain = irq_domain_add_simple(NULL,
			32, IRQ_GPIO0_SC,
			&sa1100_normal_irqdomain_ops, NULL);

	set_handle_irq(sa1100_handle_irq);

	sa1100_init_gpio();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-sa1100/irq.c
	3	*
	4	* Copyright (C) 1999-2001 Nicolas Pitre
	5	*
	6	* Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12	#include <linux/init.h>
	13	#include <linux/module.h>
119c641c	14	#include <linux/interrupt.h>
3169663a	15	#include <linux/io.h>
119c641c	16	#include <linux/irq.h>
1eca42b4	17	#include <linux/irqdomain.h>
1da177e4	18	#include <linux/ioport.h>
90533980	19	#include <linux/syscore_ops.h>
1da177e4	20
a09e64fb	21	#include <mach/hardware.h>
f314f33b	22	#include <mach/irqs.h>
1da177e4	23	#include <asm/mach/irq.h>
affcab32	24	#include <asm/exception.h>
1da177e4 LT	25
	26	#include "generic.h"
	27
	28
ab71f99f DES	29	/*
	30	* We don't need to ACK IRQs on the SA1100 unless they're GPIOs
	31	* this is for internal IRQs i.e. from IRQ LCD to RTCAlrm.
	32	*/
	33	static void sa1100_mask_irq(struct irq_data *d)
	34	{
	35	ICMR &= ~BIT(d->hwirq);
	36	}
	37
	38	static void sa1100_unmask_irq(struct irq_data *d)
	39	{
	40	ICMR \|= BIT(d->hwirq);
	41	}
	42
	43	/*
	44	* Apart form GPIOs, only the RTC alarm can be a wakeup event.
	45	*/
	46	static int sa1100_set_wake(struct irq_data *d, unsigned int on)
	47	{
	48	if (BIT(d->hwirq) == IC_RTCAlrm) {
	49	if (on)
	50	PWER \|= PWER_RTC;
	51	else
	52	PWER &= ~PWER_RTC;
	53	return 0;
	54	}
	55	return -EINVAL;
	56	}
	57
	58	static struct irq_chip sa1100_normal_chip = {
	59	.name = "SC",
	60	.irq_ack = sa1100_mask_irq,
	61	.irq_mask = sa1100_mask_irq,
	62	.irq_unmask = sa1100_unmask_irq,
	63	.irq_set_wake = sa1100_set_wake,
	64	};
	65
	66	static int sa1100_normal_irqdomain_map(struct irq_domain *d,
	67	unsigned int irq, irq_hw_number_t hwirq)
	68	{
	69	irq_set_chip_and_handler(irq, &sa1100_normal_chip,
	70	handle_level_irq);
	71	set_irq_flags(irq, IRQF_VALID);
	72
	73	return 0;
	74	}
	75
	76	static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
	77	.map = sa1100_normal_irqdomain_map,
	78	.xlate = irq_domain_xlate_onetwocell,
	79	};
	80
	81	static struct irq_domain *sa1100_normal_irqdomain;
	82
a181099e RK	83	static struct resource irq_resource =
a181099e RK	84	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
1da177e4 LT	85
	86	static struct sa1100irq_state {
	87	unsigned int saved;
	88	unsigned int icmr;
	89	unsigned int iclr;
	90	unsigned int iccr;
	91	} sa1100irq_state;
	92
90533980	93	static int sa1100irq_suspend(void)
1da177e4 LT	94	{
	95	struct sa1100irq_state *st = &sa1100irq_state;
	96
	97	st->saved = 1;
	98	st->icmr = ICMR;
	99	st->iclr = ICLR;
	100	st->iccr = ICCR;
	101
	102	/*
	103	* Disable all GPIO-based interrupts.
	104	*/
	105	ICMR &= ~(IC_GPIO11_27\|IC_GPIO10\|IC_GPIO9\|IC_GPIO8\|IC_GPIO7\|
	106	IC_GPIO6\|IC_GPIO5\|IC_GPIO4\|IC_GPIO3\|IC_GPIO2\|
	107	IC_GPIO1\|IC_GPIO0);
	108
1da177e4 LT	109	return 0;
	110	}
	111
90533980	112	static void sa1100irq_resume(void)
1da177e4 LT	113	{
	114	struct sa1100irq_state *st = &sa1100irq_state;
	115
	116	if (st->saved) {
	117	ICCR = st->iccr;
	118	ICLR = st->iclr;
	119
1da177e4 LT	120	ICMR = st->icmr;
1da177e4 LT	121	}
1da177e4 LT	122	}
1da177e4 LT	123
90533980	124	static struct syscore_ops sa1100irq_syscore_ops = {
1da177e4 LT	125	.suspend = sa1100irq_suspend,
	126	.resume = sa1100irq_resume,
	127	};
	128
1da177e4 LT	129	static int __init sa1100irq_init_devicefs(void)
1da177e4 LT	130	{
90533980 RW	131	register_syscore_ops(&sa1100irq_syscore_ops);
90533980 RW	132	return 0;
1da177e4 LT	133	}
	134
	135	device_initcall(sa1100irq_init_devicefs);
	136
affcab32 DES	137	static asmlinkage void __exception_irq_entry
	138	sa1100_handle_irq(struct pt_regs *regs)
	139	{
	140	uint32_t icip, icmr, mask;
	141
	142	do {
	143	icip = (ICIP);
	144	icmr = (ICMR);
	145	mask = icip & icmr;
	146
	147	if (mask == 0)
	148	break;
	149
364e3869 DES	150	handle_domain_irq(sa1100_normal_irqdomain,
364e3869 DES	151	ffs(mask) - 1, regs);
affcab32 DES	152	} while (1);
	153	}
	154
1da177e4 LT	155	void __init sa1100_init_irq(void)
1da177e4 LT	156	{
1da177e4 LT	157	request_resource(&iomem_resource, &irq_resource);
	158
	159	/* disable all IRQs */
	160	ICMR = 0;
	161
	162	/* all IRQs are IRQ, not FIQ */
	163	ICLR = 0;
	164
1da177e4 LT	165	/*
	166	* Whatever the doc says, this has to be set for the wait-on-irq
	167	* instruction to work... on a SA1100 rev 9 at least.
	168	*/
	169	ICCR = 1;
	170
a82be3f0 DES	171	sa1100_normal_irqdomain = irq_domain_add_simple(NULL,
a82be3f0 DES	172	32, IRQ_GPIO0_SC,
83508093 DES	173	&sa1100_normal_irqdomain_ops, NULL);
83508093 DES	174
affcab32 DES	175	set_handle_irq(sa1100_handle_irq);
affcab32 DES	176
45528e38	177	sa1100_init_gpio();
1da177e4	178	}