Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-sa1100/irq.c | |
3 | * | |
4 | * Copyright (C) 1999-2001 Nicolas Pitre | |
5 | * | |
6 | * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
119c641c | 14 | #include <linux/interrupt.h> |
3169663a | 15 | #include <linux/io.h> |
119c641c | 16 | #include <linux/irq.h> |
1da177e4 | 17 | #include <linux/ioport.h> |
90533980 | 18 | #include <linux/syscore_ops.h> |
1da177e4 | 19 | |
a09e64fb | 20 | #include <mach/hardware.h> |
f314f33b | 21 | #include <mach/irqs.h> |
1da177e4 | 22 | #include <asm/mach/irq.h> |
affcab32 | 23 | #include <asm/exception.h> |
1da177e4 LT |
24 | |
25 | #include "generic.h" | |
26 | ||
27 | ||
28 | /* | |
29 | * SA1100 GPIO edge detection for IRQs: | |
30 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | |
31 | * Use this instead of directly setting GRER/GFER. | |
32 | */ | |
33 | static int GPIO_IRQ_rising_edge; | |
34 | static int GPIO_IRQ_falling_edge; | |
35 | static int GPIO_IRQ_mask = (1 << 11) - 1; | |
36 | ||
37 | /* | |
38 | * To get the GPIO number from an IRQ number | |
39 | */ | |
40 | #define GPIO_11_27_IRQ(i) ((i) - 21) | |
41 | #define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq)) | |
42 | ||
c4e8964e | 43 | static int sa1100_gpio_type(struct irq_data *d, unsigned int type) |
1da177e4 LT |
44 | { |
45 | unsigned int mask; | |
46 | ||
c4e8964e LB |
47 | if (d->irq <= 10) |
48 | mask = 1 << d->irq; | |
1da177e4 | 49 | else |
c4e8964e | 50 | mask = GPIO11_27_MASK(d->irq); |
1da177e4 | 51 | |
6cab4860 | 52 | if (type == IRQ_TYPE_PROBE) { |
1da177e4 LT |
53 | if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) |
54 | return 0; | |
6cab4860 | 55 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
1da177e4 LT |
56 | } |
57 | ||
6cab4860 | 58 | if (type & IRQ_TYPE_EDGE_RISING) { |
1da177e4 LT |
59 | GPIO_IRQ_rising_edge |= mask; |
60 | } else | |
61 | GPIO_IRQ_rising_edge &= ~mask; | |
6cab4860 | 62 | if (type & IRQ_TYPE_EDGE_FALLING) { |
1da177e4 LT |
63 | GPIO_IRQ_falling_edge |= mask; |
64 | } else | |
65 | GPIO_IRQ_falling_edge &= ~mask; | |
66 | ||
67 | GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; | |
68 | GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; | |
69 | ||
70 | return 0; | |
71 | } | |
72 | ||
73 | /* | |
74 | * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10. | |
75 | */ | |
c4e8964e | 76 | static void sa1100_low_gpio_ack(struct irq_data *d) |
1da177e4 | 77 | { |
c4e8964e | 78 | GEDR = (1 << d->irq); |
1da177e4 LT |
79 | } |
80 | ||
c4e8964e | 81 | static void sa1100_low_gpio_mask(struct irq_data *d) |
1da177e4 | 82 | { |
c4e8964e | 83 | ICMR &= ~(1 << d->irq); |
1da177e4 LT |
84 | } |
85 | ||
c4e8964e | 86 | static void sa1100_low_gpio_unmask(struct irq_data *d) |
1da177e4 | 87 | { |
c4e8964e | 88 | ICMR |= 1 << d->irq; |
1da177e4 LT |
89 | } |
90 | ||
c4e8964e | 91 | static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on) |
1da177e4 LT |
92 | { |
93 | if (on) | |
c4e8964e | 94 | PWER |= 1 << d->irq; |
1da177e4 | 95 | else |
c4e8964e | 96 | PWER &= ~(1 << d->irq); |
1da177e4 LT |
97 | return 0; |
98 | } | |
99 | ||
38c677cb DB |
100 | static struct irq_chip sa1100_low_gpio_chip = { |
101 | .name = "GPIO-l", | |
c4e8964e LB |
102 | .irq_ack = sa1100_low_gpio_ack, |
103 | .irq_mask = sa1100_low_gpio_mask, | |
104 | .irq_unmask = sa1100_low_gpio_unmask, | |
105 | .irq_set_type = sa1100_gpio_type, | |
106 | .irq_set_wake = sa1100_low_gpio_wake, | |
1da177e4 LT |
107 | }; |
108 | ||
109 | /* | |
110 | * IRQ11 (GPIO11 through 27) handler. We enter here with the | |
111 | * irq_controller_lock held, and IRQs disabled. Decode the IRQ | |
112 | * and call the handler. | |
113 | */ | |
114 | static void | |
10dd5ce2 | 115 | sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc) |
1da177e4 LT |
116 | { |
117 | unsigned int mask; | |
118 | ||
119 | mask = GEDR & 0xfffff800; | |
120 | do { | |
121 | /* | |
122 | * clear down all currently active IRQ sources. | |
123 | * We will be processing them all. | |
124 | */ | |
125 | GEDR = mask; | |
126 | ||
127 | irq = IRQ_GPIO11; | |
1da177e4 LT |
128 | mask >>= 11; |
129 | do { | |
130 | if (mask & 1) | |
d8aa0251 | 131 | generic_handle_irq(irq); |
1da177e4 LT |
132 | mask >>= 1; |
133 | irq++; | |
1da177e4 LT |
134 | } while (mask); |
135 | ||
136 | mask = GEDR & 0xfffff800; | |
137 | } while (mask); | |
138 | } | |
139 | ||
140 | /* | |
141 | * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially. | |
142 | * In addition, the IRQs are all collected up into one bit in the | |
143 | * interrupt controller registers. | |
144 | */ | |
c4e8964e | 145 | static void sa1100_high_gpio_ack(struct irq_data *d) |
1da177e4 | 146 | { |
c4e8964e | 147 | unsigned int mask = GPIO11_27_MASK(d->irq); |
1da177e4 LT |
148 | |
149 | GEDR = mask; | |
150 | } | |
151 | ||
c4e8964e | 152 | static void sa1100_high_gpio_mask(struct irq_data *d) |
1da177e4 | 153 | { |
c4e8964e | 154 | unsigned int mask = GPIO11_27_MASK(d->irq); |
1da177e4 LT |
155 | |
156 | GPIO_IRQ_mask &= ~mask; | |
157 | ||
158 | GRER &= ~mask; | |
159 | GFER &= ~mask; | |
160 | } | |
161 | ||
c4e8964e | 162 | static void sa1100_high_gpio_unmask(struct irq_data *d) |
1da177e4 | 163 | { |
c4e8964e | 164 | unsigned int mask = GPIO11_27_MASK(d->irq); |
1da177e4 LT |
165 | |
166 | GPIO_IRQ_mask |= mask; | |
167 | ||
168 | GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; | |
169 | GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; | |
170 | } | |
171 | ||
c4e8964e | 172 | static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on) |
1da177e4 LT |
173 | { |
174 | if (on) | |
c4e8964e | 175 | PWER |= GPIO11_27_MASK(d->irq); |
1da177e4 | 176 | else |
c4e8964e | 177 | PWER &= ~GPIO11_27_MASK(d->irq); |
1da177e4 LT |
178 | return 0; |
179 | } | |
180 | ||
38c677cb DB |
181 | static struct irq_chip sa1100_high_gpio_chip = { |
182 | .name = "GPIO-h", | |
c4e8964e LB |
183 | .irq_ack = sa1100_high_gpio_ack, |
184 | .irq_mask = sa1100_high_gpio_mask, | |
185 | .irq_unmask = sa1100_high_gpio_unmask, | |
186 | .irq_set_type = sa1100_gpio_type, | |
187 | .irq_set_wake = sa1100_high_gpio_wake, | |
1da177e4 LT |
188 | }; |
189 | ||
190 | /* | |
191 | * We don't need to ACK IRQs on the SA1100 unless they're GPIOs | |
192 | * this is for internal IRQs i.e. from 11 to 31. | |
193 | */ | |
c4e8964e | 194 | static void sa1100_mask_irq(struct irq_data *d) |
1da177e4 | 195 | { |
c4e8964e | 196 | ICMR &= ~(1 << d->irq); |
1da177e4 LT |
197 | } |
198 | ||
c4e8964e | 199 | static void sa1100_unmask_irq(struct irq_data *d) |
1da177e4 | 200 | { |
c4e8964e | 201 | ICMR |= (1 << d->irq); |
1da177e4 LT |
202 | } |
203 | ||
19ca5d27 RK |
204 | /* |
205 | * Apart form GPIOs, only the RTC alarm can be a wakeup event. | |
206 | */ | |
c4e8964e | 207 | static int sa1100_set_wake(struct irq_data *d, unsigned int on) |
19ca5d27 | 208 | { |
c4e8964e | 209 | if (d->irq == IRQ_RTCAlrm) { |
19ca5d27 RK |
210 | if (on) |
211 | PWER |= PWER_RTC; | |
212 | else | |
213 | PWER &= ~PWER_RTC; | |
214 | return 0; | |
215 | } | |
216 | return -EINVAL; | |
217 | } | |
218 | ||
38c677cb DB |
219 | static struct irq_chip sa1100_normal_chip = { |
220 | .name = "SC", | |
c4e8964e LB |
221 | .irq_ack = sa1100_mask_irq, |
222 | .irq_mask = sa1100_mask_irq, | |
223 | .irq_unmask = sa1100_unmask_irq, | |
224 | .irq_set_wake = sa1100_set_wake, | |
1da177e4 LT |
225 | }; |
226 | ||
a181099e RK |
227 | static struct resource irq_resource = |
228 | DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs"); | |
1da177e4 LT |
229 | |
230 | static struct sa1100irq_state { | |
231 | unsigned int saved; | |
232 | unsigned int icmr; | |
233 | unsigned int iclr; | |
234 | unsigned int iccr; | |
235 | } sa1100irq_state; | |
236 | ||
90533980 | 237 | static int sa1100irq_suspend(void) |
1da177e4 LT |
238 | { |
239 | struct sa1100irq_state *st = &sa1100irq_state; | |
240 | ||
241 | st->saved = 1; | |
242 | st->icmr = ICMR; | |
243 | st->iclr = ICLR; | |
244 | st->iccr = ICCR; | |
245 | ||
246 | /* | |
247 | * Disable all GPIO-based interrupts. | |
248 | */ | |
249 | ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7| | |
250 | IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2| | |
251 | IC_GPIO1|IC_GPIO0); | |
252 | ||
253 | /* | |
254 | * Set the appropriate edges for wakeup. | |
255 | */ | |
256 | GRER = PWER & GPIO_IRQ_rising_edge; | |
257 | GFER = PWER & GPIO_IRQ_falling_edge; | |
258 | ||
259 | /* | |
260 | * Clear any pending GPIO interrupts. | |
261 | */ | |
262 | GEDR = GEDR; | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
90533980 | 267 | static void sa1100irq_resume(void) |
1da177e4 LT |
268 | { |
269 | struct sa1100irq_state *st = &sa1100irq_state; | |
270 | ||
271 | if (st->saved) { | |
272 | ICCR = st->iccr; | |
273 | ICLR = st->iclr; | |
274 | ||
275 | GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; | |
276 | GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; | |
277 | ||
278 | ICMR = st->icmr; | |
279 | } | |
1da177e4 LT |
280 | } |
281 | ||
90533980 | 282 | static struct syscore_ops sa1100irq_syscore_ops = { |
1da177e4 LT |
283 | .suspend = sa1100irq_suspend, |
284 | .resume = sa1100irq_resume, | |
285 | }; | |
286 | ||
1da177e4 LT |
287 | static int __init sa1100irq_init_devicefs(void) |
288 | { | |
90533980 RW |
289 | register_syscore_ops(&sa1100irq_syscore_ops); |
290 | return 0; | |
1da177e4 LT |
291 | } |
292 | ||
293 | device_initcall(sa1100irq_init_devicefs); | |
294 | ||
affcab32 DES |
295 | static asmlinkage void __exception_irq_entry |
296 | sa1100_handle_irq(struct pt_regs *regs) | |
297 | { | |
298 | uint32_t icip, icmr, mask; | |
299 | ||
300 | do { | |
301 | icip = (ICIP); | |
302 | icmr = (ICMR); | |
303 | mask = icip & icmr; | |
304 | ||
305 | if (mask == 0) | |
306 | break; | |
307 | ||
308 | handle_IRQ(ffs(mask) - 1 + IRQ_GPIO0, regs); | |
309 | } while (1); | |
310 | } | |
311 | ||
1da177e4 LT |
312 | void __init sa1100_init_irq(void) |
313 | { | |
314 | unsigned int irq; | |
315 | ||
316 | request_resource(&iomem_resource, &irq_resource); | |
317 | ||
318 | /* disable all IRQs */ | |
319 | ICMR = 0; | |
320 | ||
321 | /* all IRQs are IRQ, not FIQ */ | |
322 | ICLR = 0; | |
323 | ||
324 | /* clear all GPIO edge detects */ | |
325 | GFER = 0; | |
326 | GRER = 0; | |
327 | GEDR = -1; | |
328 | ||
329 | /* | |
330 | * Whatever the doc says, this has to be set for the wait-on-irq | |
331 | * instruction to work... on a SA1100 rev 9 at least. | |
332 | */ | |
333 | ICCR = 1; | |
334 | ||
335 | for (irq = 0; irq <= 10; irq++) { | |
f38c02f3 TG |
336 | irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip, |
337 | handle_edge_irq); | |
1da177e4 LT |
338 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
339 | } | |
340 | ||
341 | for (irq = 12; irq <= 31; irq++) { | |
f38c02f3 TG |
342 | irq_set_chip_and_handler(irq, &sa1100_normal_chip, |
343 | handle_level_irq); | |
1da177e4 LT |
344 | set_irq_flags(irq, IRQF_VALID); |
345 | } | |
346 | ||
347 | for (irq = 32; irq <= 48; irq++) { | |
f38c02f3 TG |
348 | irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip, |
349 | handle_edge_irq); | |
1da177e4 LT |
350 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
351 | } | |
352 | ||
353 | /* | |
354 | * Install handler for GPIO 11-27 edge detect interrupts | |
355 | */ | |
6845664a TG |
356 | irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip); |
357 | irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); | |
45528e38 | 358 | |
affcab32 DES |
359 | set_handle_irq(sa1100_handle_irq); |
360 | ||
45528e38 | 361 | sa1100_init_gpio(); |
1da177e4 | 362 | } |