[deliverable/linux.git] / arch / arm / mach-sa1100 / irq.c

/*
 * linux/arch/arm/mach-sa1100/irq.c
 *
 * Copyright (C) 1999-2001 Nicolas Pitre
 *
 * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/ioport.h>
#include <linux/sysdev.h>

#include <mach/hardware.h>
#include <asm/mach/irq.h>

#include "generic.h"


/*
 * SA1100 GPIO edge detection for IRQs:
 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
 * Use this instead of directly setting GRER/GFER.
 */
static int GPIO_IRQ_rising_edge;
static int GPIO_IRQ_falling_edge;
static int GPIO_IRQ_mask = (1 << 11) - 1;

/*
 * To get the GPIO number from an IRQ number
 */
#define GPIO_11_27_IRQ(i)	((i) - 21)
#define GPIO11_27_MASK(irq)	(1 << GPIO_11_27_IRQ(irq))

static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
{
	unsigned int mask;

	if (d->irq <= 10)
		mask = 1 << d->irq;
	else
		mask = GPIO11_27_MASK(d->irq);

	if (type == IRQ_TYPE_PROBE) {
		if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
			return 0;
		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	}

	if (type & IRQ_TYPE_EDGE_RISING) {
		GPIO_IRQ_rising_edge |= mask;
	} else
		GPIO_IRQ_rising_edge &= ~mask;
	if (type & IRQ_TYPE_EDGE_FALLING) {
		GPIO_IRQ_falling_edge |= mask;
	} else
		GPIO_IRQ_falling_edge &= ~mask;

	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;

	return 0;
}

/*
 * GPIO IRQs must be acknowledged.  This is for IRQs from 0 to 10.
 */
static void sa1100_low_gpio_ack(struct irq_data *d)
{
	GEDR = (1 << d->irq);
}

static void sa1100_low_gpio_mask(struct irq_data *d)
{
	ICMR &= ~(1 << d->irq);
}

static void sa1100_low_gpio_unmask(struct irq_data *d)
{
	ICMR |= 1 << d->irq;
}

static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
{
	if (on)
		PWER |= 1 << d->irq;
	else
		PWER &= ~(1 << d->irq);
	return 0;
}

static struct irq_chip sa1100_low_gpio_chip = {
	.name		= "GPIO-l",
	.irq_ack	= sa1100_low_gpio_ack,
	.irq_mask	= sa1100_low_gpio_mask,
	.irq_unmask	= sa1100_low_gpio_unmask,
	.irq_set_type	= sa1100_gpio_type,
	.irq_set_wake	= sa1100_low_gpio_wake,
};

/*
 * IRQ11 (GPIO11 through 27) handler.  We enter here with the
 * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
 * and call the handler.
 */
static void
sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned int mask;

	mask = GEDR & 0xfffff800;
	do {
		/*
		 * clear down all currently active IRQ sources.
		 * We will be processing them all.
		 */
		GEDR = mask;

		irq = IRQ_GPIO11;
		mask >>= 11;
		do {
			if (mask & 1)
				generic_handle_irq(irq);
			mask >>= 1;
			irq++;
		} while (mask);

		mask = GEDR & 0xfffff800;
	} while (mask);
}

/*
 * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
 * In addition, the IRQs are all collected up into one bit in the
 * interrupt controller registers.
 */
static void sa1100_high_gpio_ack(struct irq_data *d)
{
	unsigned int mask = GPIO11_27_MASK(d->irq);

	GEDR = mask;
}

static void sa1100_high_gpio_mask(struct irq_data *d)
{
	unsigned int mask = GPIO11_27_MASK(d->irq);

	GPIO_IRQ_mask &= ~mask;

	GRER &= ~mask;
	GFER &= ~mask;
}

static void sa1100_high_gpio_unmask(struct irq_data *d)
{
	unsigned int mask = GPIO11_27_MASK(d->irq);

	GPIO_IRQ_mask |= mask;

	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
}

static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
{
	if (on)
		PWER |= GPIO11_27_MASK(d->irq);
	else
		PWER &= ~GPIO11_27_MASK(d->irq);
	return 0;
}

static struct irq_chip sa1100_high_gpio_chip = {
	.name		= "GPIO-h",
	.irq_ack	= sa1100_high_gpio_ack,
	.irq_mask	= sa1100_high_gpio_mask,
	.irq_unmask	= sa1100_high_gpio_unmask,
	.irq_set_type	= sa1100_gpio_type,
	.irq_set_wake	= sa1100_high_gpio_wake,
};

/*
 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
 * this is for internal IRQs i.e. from 11 to 31.
 */
static void sa1100_mask_irq(struct irq_data *d)
{
	ICMR &= ~(1 << d->irq);
}

static void sa1100_unmask_irq(struct irq_data *d)
{
	ICMR |= (1 << d->irq);
}

/*
 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
 */
static int sa1100_set_wake(struct irq_data *d, unsigned int on)
{
	if (d->irq == IRQ_RTCAlrm) {
		if (on)
			PWER |= PWER_RTC;
		else
			PWER &= ~PWER_RTC;
		return 0;
	}
	return -EINVAL;
}

static struct irq_chip sa1100_normal_chip = {
	.name		= "SC",
	.irq_ack	= sa1100_mask_irq,
	.irq_mask	= sa1100_mask_irq,
	.irq_unmask	= sa1100_unmask_irq,
	.irq_set_wake	= sa1100_set_wake,
};

static struct resource irq_resource = {
	.name	= "irqs",
	.start	= 0x90050000,
	.end	= 0x9005ffff,
};

static struct sa1100irq_state {
	unsigned int	saved;
	unsigned int	icmr;
	unsigned int	iclr;
	unsigned int	iccr;
} sa1100irq_state;

static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state)
{
	struct sa1100irq_state *st = &sa1100irq_state;

	st->saved = 1;
	st->icmr = ICMR;
	st->iclr = ICLR;
	st->iccr = ICCR;

	/*
	 * Disable all GPIO-based interrupts.
	 */
	ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
		  IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
		  IC_GPIO1|IC_GPIO0);

	/*
	 * Set the appropriate edges for wakeup.
	 */
	GRER = PWER & GPIO_IRQ_rising_edge;
	GFER = PWER & GPIO_IRQ_falling_edge;
	
	/*
	 * Clear any pending GPIO interrupts.
	 */
	GEDR = GEDR;

	return 0;
}

static int sa1100irq_resume(struct sys_device *dev)
{
	struct sa1100irq_state *st = &sa1100irq_state;

	if (st->saved) {
		ICCR = st->iccr;
		ICLR = st->iclr;

		GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
		GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;

		ICMR = st->icmr;
	}
	return 0;
}

static struct sysdev_class sa1100irq_sysclass = {
	.name		= "sa11x0-irq",
	.suspend	= sa1100irq_suspend,
	.resume		= sa1100irq_resume,
};

static struct sys_device sa1100irq_device = {
	.id		= 0,
	.cls		= &sa1100irq_sysclass,
};

static int __init sa1100irq_init_devicefs(void)
{
	sysdev_class_register(&sa1100irq_sysclass);
	return sysdev_register(&sa1100irq_device);
}

device_initcall(sa1100irq_init_devicefs);

void __init sa1100_init_irq(void)
{
	unsigned int irq;

	request_resource(&iomem_resource, &irq_resource);

	/* disable all IRQs */
	ICMR = 0;

	/* all IRQs are IRQ, not FIQ */
	ICLR = 0;

	/* clear all GPIO edge detects */
	GFER = 0;
	GRER = 0;
	GEDR = -1;

	/*
	 * Whatever the doc says, this has to be set for the wait-on-irq
	 * instruction to work... on a SA1100 rev 9 at least.
	 */
	ICCR = 1;

	for (irq = 0; irq <= 10; irq++) {
		irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
					 handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	for (irq = 12; irq <= 31; irq++) {
		irq_set_chip_and_handler(irq, &sa1100_normal_chip,
					 handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	for (irq = 32; irq <= 48; irq++) {
		irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
					 handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	/*
	 * Install handler for GPIO 11-27 edge detect interrupts
	 */
	irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
	irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);

	sa1100_init_gpio();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-sa1100/irq.c
	3	*
	4	* Copyright (C) 1999-2001 Nicolas Pitre
	5	*
	6	* Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12	#include <linux/init.h>
	13	#include <linux/module.h>
119c641c TG	14	#include <linux/interrupt.h>
119c641c TG	15	#include <linux/irq.h>
1da177e4	16	#include <linux/ioport.h>
1da177e4 LT	17	#include <linux/sysdev.h>
1da177e4 LT	18
a09e64fb	19	#include <mach/hardware.h>
1da177e4 LT	20	#include <asm/mach/irq.h>
	21
	22	#include "generic.h"
	23
	24
	25	/*
	26	* SA1100 GPIO edge detection for IRQs:
	27	* IRQs are generated on Falling-Edge, Rising-Edge, or both.
	28	* Use this instead of directly setting GRER/GFER.
	29	*/
	30	static int GPIO_IRQ_rising_edge;
	31	static int GPIO_IRQ_falling_edge;
	32	static int GPIO_IRQ_mask = (1 << 11) - 1;
	33
	34	/*
	35	* To get the GPIO number from an IRQ number
	36	*/
	37	#define GPIO_11_27_IRQ(i) ((i) - 21)
	38	#define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq))
	39
c4e8964e	40	static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
1da177e4 LT	41	{
	42	unsigned int mask;
	43
c4e8964e LB	44	if (d->irq <= 10)
c4e8964e LB	45	mask = 1 << d->irq;
1da177e4	46	else
c4e8964e	47	mask = GPIO11_27_MASK(d->irq);
1da177e4	48
6cab4860	49	if (type == IRQ_TYPE_PROBE) {
1da177e4 LT	50	if ((GPIO_IRQ_rising_edge \| GPIO_IRQ_falling_edge) & mask)
1da177e4 LT	51	return 0;
6cab4860	52	type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
1da177e4 LT	53	}
1da177e4 LT	54
6cab4860	55	if (type & IRQ_TYPE_EDGE_RISING) {
1da177e4 LT	56	GPIO_IRQ_rising_edge \|= mask;
	57	} else
	58	GPIO_IRQ_rising_edge &= ~mask;
6cab4860	59	if (type & IRQ_TYPE_EDGE_FALLING) {
1da177e4 LT	60	GPIO_IRQ_falling_edge \|= mask;
	61	} else
	62	GPIO_IRQ_falling_edge &= ~mask;
	63
	64	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	65	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
	66
	67	return 0;
	68	}
	69
	70	/*
	71	* GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10.
	72	*/
c4e8964e	73	static void sa1100_low_gpio_ack(struct irq_data *d)
1da177e4	74	{
c4e8964e	75	GEDR = (1 << d->irq);
1da177e4 LT	76	}
1da177e4 LT	77
c4e8964e	78	static void sa1100_low_gpio_mask(struct irq_data *d)
1da177e4	79	{
c4e8964e	80	ICMR &= ~(1 << d->irq);
1da177e4 LT	81	}
1da177e4 LT	82
c4e8964e	83	static void sa1100_low_gpio_unmask(struct irq_data *d)
1da177e4	84	{
c4e8964e	85	ICMR \|= 1 << d->irq;
1da177e4 LT	86	}
1da177e4 LT	87
c4e8964e	88	static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
1da177e4 LT	89	{
1da177e4 LT	90	if (on)
c4e8964e	91	PWER \|= 1 << d->irq;
1da177e4	92	else
c4e8964e	93	PWER &= ~(1 << d->irq);
1da177e4 LT	94	return 0;
	95	}
	96
38c677cb DB	97	static struct irq_chip sa1100_low_gpio_chip = {
38c677cb DB	98	.name = "GPIO-l",
c4e8964e LB	99	.irq_ack = sa1100_low_gpio_ack,
	100	.irq_mask = sa1100_low_gpio_mask,
	101	.irq_unmask = sa1100_low_gpio_unmask,
	102	.irq_set_type = sa1100_gpio_type,
	103	.irq_set_wake = sa1100_low_gpio_wake,
1da177e4 LT	104	};
	105
	106	/*
	107	* IRQ11 (GPIO11 through 27) handler. We enter here with the
	108	* irq_controller_lock held, and IRQs disabled. Decode the IRQ
	109	* and call the handler.
	110	*/
	111	static void
10dd5ce2	112	sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
1da177e4 LT	113	{
	114	unsigned int mask;
	115
	116	mask = GEDR & 0xfffff800;
	117	do {
	118	/*
	119	* clear down all currently active IRQ sources.
	120	* We will be processing them all.
	121	*/
	122	GEDR = mask;
	123
	124	irq = IRQ_GPIO11;
1da177e4 LT	125	mask >>= 11;
	126	do {
	127	if (mask & 1)
d8aa0251	128	generic_handle_irq(irq);
1da177e4 LT	129	mask >>= 1;
1da177e4 LT	130	irq++;
1da177e4 LT	131	} while (mask);
	132
	133	mask = GEDR & 0xfffff800;
	134	} while (mask);
	135	}
	136
	137	/*
	138	* Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
	139	* In addition, the IRQs are all collected up into one bit in the
	140	* interrupt controller registers.
	141	*/
c4e8964e	142	static void sa1100_high_gpio_ack(struct irq_data *d)
1da177e4	143	{
c4e8964e	144	unsigned int mask = GPIO11_27_MASK(d->irq);
1da177e4 LT	145
	146	GEDR = mask;
	147	}
	148
c4e8964e	149	static void sa1100_high_gpio_mask(struct irq_data *d)
1da177e4	150	{
c4e8964e	151	unsigned int mask = GPIO11_27_MASK(d->irq);
1da177e4 LT	152
	153	GPIO_IRQ_mask &= ~mask;
	154
	155	GRER &= ~mask;
	156	GFER &= ~mask;
	157	}
	158
c4e8964e	159	static void sa1100_high_gpio_unmask(struct irq_data *d)
1da177e4	160	{
c4e8964e	161	unsigned int mask = GPIO11_27_MASK(d->irq);
1da177e4 LT	162
	163	GPIO_IRQ_mask \|= mask;
	164
	165	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	166	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
	167	}
	168
c4e8964e	169	static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
1da177e4 LT	170	{
1da177e4 LT	171	if (on)
c4e8964e	172	PWER \|= GPIO11_27_MASK(d->irq);
1da177e4	173	else
c4e8964e	174	PWER &= ~GPIO11_27_MASK(d->irq);
1da177e4 LT	175	return 0;
	176	}
	177
38c677cb DB	178	static struct irq_chip sa1100_high_gpio_chip = {
38c677cb DB	179	.name = "GPIO-h",
c4e8964e LB	180	.irq_ack = sa1100_high_gpio_ack,
	181	.irq_mask = sa1100_high_gpio_mask,
	182	.irq_unmask = sa1100_high_gpio_unmask,
	183	.irq_set_type = sa1100_gpio_type,
	184	.irq_set_wake = sa1100_high_gpio_wake,
1da177e4 LT	185	};
	186
	187	/*
	188	* We don't need to ACK IRQs on the SA1100 unless they're GPIOs
	189	* this is for internal IRQs i.e. from 11 to 31.
	190	*/
c4e8964e	191	static void sa1100_mask_irq(struct irq_data *d)
1da177e4	192	{
c4e8964e	193	ICMR &= ~(1 << d->irq);
1da177e4 LT	194	}
1da177e4 LT	195
c4e8964e	196	static void sa1100_unmask_irq(struct irq_data *d)
1da177e4	197	{
c4e8964e	198	ICMR \|= (1 << d->irq);
1da177e4 LT	199	}
1da177e4 LT	200
19ca5d27 RK	201	/*
	202	* Apart form GPIOs, only the RTC alarm can be a wakeup event.
	203	*/
c4e8964e	204	static int sa1100_set_wake(struct irq_data *d, unsigned int on)
19ca5d27	205	{
c4e8964e	206	if (d->irq == IRQ_RTCAlrm) {
19ca5d27 RK	207	if (on)
	208	PWER \|= PWER_RTC;
	209	else
	210	PWER &= ~PWER_RTC;
	211	return 0;
	212	}
	213	return -EINVAL;
	214	}
	215
38c677cb DB	216	static struct irq_chip sa1100_normal_chip = {
38c677cb DB	217	.name = "SC",
c4e8964e LB	218	.irq_ack = sa1100_mask_irq,
	219	.irq_mask = sa1100_mask_irq,
	220	.irq_unmask = sa1100_unmask_irq,
	221	.irq_set_wake = sa1100_set_wake,
1da177e4 LT	222	};
	223
	224	static struct resource irq_resource = {
	225	.name = "irqs",
	226	.start = 0x90050000,
	227	.end = 0x9005ffff,
	228	};
	229
	230	static struct sa1100irq_state {
	231	unsigned int saved;
	232	unsigned int icmr;
	233	unsigned int iclr;
	234	unsigned int iccr;
	235	} sa1100irq_state;
	236
	237	static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state)
	238	{
	239	struct sa1100irq_state *st = &sa1100irq_state;
	240
	241	st->saved = 1;
	242	st->icmr = ICMR;
	243	st->iclr = ICLR;
	244	st->iccr = ICCR;
	245
	246	/*
	247	* Disable all GPIO-based interrupts.
	248	*/
	249	ICMR &= ~(IC_GPIO11_27\|IC_GPIO10\|IC_GPIO9\|IC_GPIO8\|IC_GPIO7\|
	250	IC_GPIO6\|IC_GPIO5\|IC_GPIO4\|IC_GPIO3\|IC_GPIO2\|
	251	IC_GPIO1\|IC_GPIO0);
	252
	253	/*
	254	* Set the appropriate edges for wakeup.
	255	*/
	256	GRER = PWER & GPIO_IRQ_rising_edge;
	257	GFER = PWER & GPIO_IRQ_falling_edge;
	258
	259	/*
	260	* Clear any pending GPIO interrupts.
	261	*/
	262	GEDR = GEDR;
	263
	264	return 0;
	265	}
	266
	267	static int sa1100irq_resume(struct sys_device *dev)
	268	{
	269	struct sa1100irq_state *st = &sa1100irq_state;
	270
	271	if (st->saved) {
	272	ICCR = st->iccr;
	273	ICLR = st->iclr;
	274
	275	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	276	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
	277
	278	ICMR = st->icmr;
	279	}
	280	return 0;
	281	}
	282
	283	static struct sysdev_class sa1100irq_sysclass = {
af5ca3f4	284	.name = "sa11x0-irq",
1da177e4 LT	285	.suspend = sa1100irq_suspend,
	286	.resume = sa1100irq_resume,
	287	};
	288
	289	static struct sys_device sa1100irq_device = {
	290	.id = 0,
	291	.cls = &sa1100irq_sysclass,
	292	};
	293
	294	static int __init sa1100irq_init_devicefs(void)
	295	{
	296	sysdev_class_register(&sa1100irq_sysclass);
	297	return sysdev_register(&sa1100irq_device);
	298	}
	299
	300	device_initcall(sa1100irq_init_devicefs);
	301
	302	void __init sa1100_init_irq(void)
	303	{
	304	unsigned int irq;
	305
	306	request_resource(&iomem_resource, &irq_resource);
	307
	308	/* disable all IRQs */
	309	ICMR = 0;
	310
	311	/* all IRQs are IRQ, not FIQ */
	312	ICLR = 0;
	313
	314	/* clear all GPIO edge detects */
	315	GFER = 0;
	316	GRER = 0;
	317	GEDR = -1;
	318
	319	/*
	320	* Whatever the doc says, this has to be set for the wait-on-irq
	321	* instruction to work... on a SA1100 rev 9 at least.
	322	*/
	323	ICCR = 1;
	324
	325	for (irq = 0; irq <= 10; irq++) {
f38c02f3 TG	326	irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
f38c02f3 TG	327	handle_edge_irq);
1da177e4 LT	328	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	329	}
	330
	331	for (irq = 12; irq <= 31; irq++) {
f38c02f3 TG	332	irq_set_chip_and_handler(irq, &sa1100_normal_chip,
f38c02f3 TG	333	handle_level_irq);
1da177e4 LT	334	set_irq_flags(irq, IRQF_VALID);
	335	}
	336
	337	for (irq = 32; irq <= 48; irq++) {
f38c02f3 TG	338	irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
f38c02f3 TG	339	handle_edge_irq);
1da177e4 LT	340	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	341	}
	342
	343	/*
	344	* Install handler for GPIO 11-27 edge detect interrupts
	345	*/
6845664a TG	346	irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
6845664a TG	347	irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
45528e38 DB	348
45528e38 DB	349	sa1100_init_gpio();
1da177e4	350	}