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1da177e4 LT |
1 | /* |
2 | * SA1100 Power Management Routines | |
3 | * | |
4 | * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License. | |
8 | * | |
9 | * History: | |
10 | * | |
11 | * 2001-02-06: Cliff Brake Initial code | |
12 | * | |
13 | * 2001-02-25: Sukjae Cho <sjcho@east.isi.edu> & | |
14 | * Chester Kuo <chester@linux.org.tw> | |
15 | * Save more value for the resume function! Support | |
16 | * Bitsy/Assabet/Freebird board | |
17 | * | |
2f82af08 | 18 | * 2001-08-29: Nicolas Pitre <nico@fluxnic.net> |
1da177e4 LT |
19 | * Cleaned up, pushed platform dependent stuff |
20 | * in the platform specific files. | |
21 | * | |
22 | * 2002-05-27: Nicolas Pitre Killed sleep.h and the kmalloced save array. | |
23 | * Storage is local on the stack now. | |
24 | */ | |
25 | #include <linux/init.h> | |
26 | #include <linux/suspend.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/time.h> | |
29 | ||
a09e64fb | 30 | #include <mach/hardware.h> |
1da177e4 LT |
31 | #include <asm/memory.h> |
32 | #include <asm/system.h> | |
33 | #include <asm/mach/time.h> | |
34 | ||
34c79de6 | 35 | extern void sa1100_finish_suspend(unsigned long); |
1da177e4 LT |
36 | |
37 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x | |
38 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
39 | ||
40 | /* | |
41 | * List of global SA11x0 peripheral registers to preserve. | |
42 | * More ones like CP and general purpose register values are preserved | |
43 | * on the stack and then the stack pointer is stored last in sleep.S. | |
44 | */ | |
649de51b | 45 | enum { SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR, |
1da177e4 LT |
46 | SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR, |
47 | ||
48 | SLEEP_SAVE_Ser1SDCR0, | |
49 | ||
649de51b | 50 | SLEEP_SAVE_COUNT |
1da177e4 LT |
51 | }; |
52 | ||
53 | ||
54 | static int sa11x0_pm_enter(suspend_state_t state) | |
55 | { | |
649de51b | 56 | unsigned long gpio, sleep_save[SLEEP_SAVE_COUNT]; |
1da177e4 | 57 | |
1da177e4 LT |
58 | gpio = GPLR; |
59 | ||
60 | /* save vital registers */ | |
61 | SAVE(GPDR); | |
62 | SAVE(GAFR); | |
63 | ||
64 | SAVE(PPDR); | |
65 | SAVE(PPSR); | |
66 | SAVE(PPAR); | |
67 | SAVE(PSDR); | |
68 | ||
69 | SAVE(Ser1SDCR0); | |
70 | ||
71 | /* Clear previous reset status */ | |
72 | RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR; | |
73 | ||
74 | /* set resume return address */ | |
96c20015 | 75 | PSPR = virt_to_phys(cpu_resume); |
1da177e4 LT |
76 | |
77 | /* go zzz */ | |
34c79de6 | 78 | cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, 0, sa1100_finish_suspend); |
1da177e4 LT |
79 | |
80 | /* | |
81 | * Ensure not to come back here if it wasn't intended | |
82 | */ | |
83 | PSPR = 0; | |
84 | ||
85 | /* | |
86 | * Ensure interrupt sources are disabled; we will re-init | |
87 | * the interrupt subsystem via the device manager. | |
88 | */ | |
89 | ICLR = 0; | |
90 | ICCR = 1; | |
91 | ICMR = 0; | |
92 | ||
93 | /* restore registers */ | |
94 | RESTORE(GPDR); | |
95 | RESTORE(GAFR); | |
96 | ||
97 | RESTORE(PPDR); | |
98 | RESTORE(PPSR); | |
99 | RESTORE(PPAR); | |
100 | RESTORE(PSDR); | |
101 | ||
102 | RESTORE(Ser1SDCR0); | |
103 | ||
104 | GPSR = gpio; | |
105 | GPCR = ~gpio; | |
106 | ||
107 | /* | |
108 | * Clear the peripheral sleep-hold bit. | |
109 | */ | |
110 | PSSR = PSSR_PH; | |
111 | ||
1da177e4 LT |
112 | return 0; |
113 | } | |
114 | ||
2f55ac07 | 115 | static const struct platform_suspend_ops sa11x0_pm_ops = { |
1da177e4 | 116 | .enter = sa11x0_pm_enter, |
26398a70 | 117 | .valid = suspend_valid_only_mem, |
1da177e4 LT |
118 | }; |
119 | ||
120 | static int __init sa11x0_pm_init(void) | |
121 | { | |
26398a70 | 122 | suspend_set_ops(&sa11x0_pm_ops); |
1da177e4 LT |
123 | return 0; |
124 | } | |
125 | ||
126 | late_initcall(sa11x0_pm_init); |