[deliverable/linux.git] / arch / arm / mach-shark / irq.c

/*
 *  linux/arch/arm/mach-shark/irq.c
 *
 * by Alexander Schulz
 *
 * derived from linux/arch/ppc/kernel/i8259.c and:
 * arch/arm/mach-ebsa110/include/mach/irq.h
 * Copyright (C) 1996-1998 Russell King
 */

#include <linux/init.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#include <asm/irq.h>
#include <asm/mach/irq.h>

/*
 * 8259A PIC functions to handle ISA devices:
 */

/*
 * This contains the irq mask for both 8259A irq controllers,
 * Let through the cascade-interrupt no. 2 (ff-(1<<2)==fb)
 */
static unsigned char cached_irq_mask[2] = { 0xfb, 0xff };

/*
 * These have to be protected by the irq controller spinlock
 * before being called.
 */
static void shark_disable_8259A_irq(struct irq_data *d)
{
	unsigned int mask;
	if (d->irq<8) {
	  mask = 1 << d->irq;
	  cached_irq_mask[0] |= mask;
	  outb(cached_irq_mask[1],0xA1);
	} else {
	  mask = 1 << (d->irq-8);
	  cached_irq_mask[1] |= mask;
	  outb(cached_irq_mask[0],0x21);
	}
}

static void shark_enable_8259A_irq(struct irq_data *d)
{
	unsigned int mask;
	if (d->irq<8) {
	  mask = ~(1 << d->irq);
	  cached_irq_mask[0] &= mask;
	  outb(cached_irq_mask[0],0x21);
	} else {
	  mask = ~(1 << (d->irq-8));
	  cached_irq_mask[1] &= mask;
	  outb(cached_irq_mask[1],0xA1);
	}
}

static void shark_ack_8259A_irq(struct irq_data *d){}

static irqreturn_t bogus_int(int irq, void *dev_id)
{
	printk("Got interrupt %i!\n",irq);
	return IRQ_NONE;
}

static struct irqaction cascade;

static struct irq_chip fb_chip = {
	.name		= "XT-PIC",
	.irq_ack	= shark_ack_8259A_irq,
	.irq_mask	= shark_disable_8259A_irq,
	.irq_unmask	= shark_enable_8259A_irq,
};

void __init shark_init_irq(void)
{
	int irq;

	for (irq = 0; irq < NR_IRQS; irq++) {
		irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	/* init master interrupt controller */
	outb(0x11, 0x20); /* Start init sequence, edge triggered (level: 0x19)*/
	outb(0x00, 0x21); /* Vector base */
	outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */
	outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/
	outb(0x0A, 0x20);
	/* init slave interrupt controller */
	outb(0x11, 0xA0); /* Start init sequence, edge triggered */
	outb(0x08, 0xA1); /* Vector base */
	outb(0x02, 0xA1); /* Cascade (slave) on IRQ2 */
	outb(0x03, 0xA1); /* Select 8086 mode, auto eoi */
	outb(0x0A, 0xA0);
	outb(cached_irq_mask[1],0xA1);
	outb(cached_irq_mask[0],0x21);
	//request_region(0x20,0x2,"pic1");
	//request_region(0xA0,0x2,"pic2");

	cascade.handler = bogus_int;
	cascade.name = "cascade";
	setup_irq(2,&cascade);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-shark/irq.c
	3	*
	4	* by Alexander Schulz
	5	*
	6	* derived from linux/arch/ppc/kernel/i8259.c and:
a09e64fb	7	* arch/arm/mach-ebsa110/include/mach/irq.h
1da177e4 LT	8	* Copyright (C) 1996-1998 Russell King
	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/fs.h>
1da177e4	13	#include <linux/interrupt.h>
fced80c7	14	#include <linux/io.h>
1da177e4 LT	15
1da177e4 LT	16	#include <asm/irq.h>
1da177e4 LT	17	#include <asm/mach/irq.h>
	18
	19	/*
	20	* 8259A PIC functions to handle ISA devices:
	21	*/
	22
	23	/*
	24	* This contains the irq mask for both 8259A irq controllers,
	25	* Let through the cascade-interrupt no. 2 (ff-(1<<2)==fb)
	26	*/
	27	static unsigned char cached_irq_mask[2] = { 0xfb, 0xff };
	28
	29	/*
	30	* These have to be protected by the irq controller spinlock
	31	* before being called.
	32	*/
aab0c637	33	static void shark_disable_8259A_irq(struct irq_data *d)
1da177e4 LT	34	{
1da177e4 LT	35	unsigned int mask;
aab0c637 LB	36	if (d->irq<8) {
aab0c637 LB	37	mask = 1 << d->irq;
1da177e4 LT	38	cached_irq_mask[0] \|= mask;
	39	outb(cached_irq_mask[1],0xA1);
	40	} else {
aab0c637	41	mask = 1 << (d->irq-8);
1da177e4 LT	42	cached_irq_mask[1] \|= mask;
	43	outb(cached_irq_mask[0],0x21);
	44	}
	45	}
	46
aab0c637	47	static void shark_enable_8259A_irq(struct irq_data *d)
1da177e4 LT	48	{
1da177e4 LT	49	unsigned int mask;
aab0c637 LB	50	if (d->irq<8) {
aab0c637 LB	51	mask = ~(1 << d->irq);
1da177e4 LT	52	cached_irq_mask[0] &= mask;
	53	outb(cached_irq_mask[0],0x21);
	54	} else {
aab0c637	55	mask = ~(1 << (d->irq-8));
1da177e4 LT	56	cached_irq_mask[1] &= mask;
	57	outb(cached_irq_mask[1],0xA1);
	58	}
	59	}
	60
aab0c637	61	static void shark_ack_8259A_irq(struct irq_data *d){}
1da177e4	62
0cd61b68	63	static irqreturn_t bogus_int(int irq, void *dev_id)
1da177e4 LT	64	{
	65	printk("Got interrupt %i!\n",irq);
	66	return IRQ_NONE;
	67	}
	68
	69	static struct irqaction cascade;
	70
38c677cb	71	static struct irq_chip fb_chip = {
aab0c637 LB	72	.name = "XT-PIC",
	73	.irq_ack = shark_ack_8259A_irq,
	74	.irq_mask = shark_disable_8259A_irq,
	75	.irq_unmask = shark_enable_8259A_irq,
1da177e4 LT	76	};
	77
	78	void __init shark_init_irq(void)
	79	{
	80	int irq;
	81
	82	for (irq = 0; irq < NR_IRQS; irq++) {
f38c02f3	83	irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq);
1da177e4 LT	84	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	85	}
	86
	87	/* init master interrupt controller */
	88	outb(0x11, 0x20); /* Start init sequence, edge triggered (level: 0x19)*/
	89	outb(0x00, 0x21); /* Vector base */
	90	outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */
	91	outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/
	92	outb(0x0A, 0x20);
	93	/* init slave interrupt controller */
	94	outb(0x11, 0xA0); /* Start init sequence, edge triggered */
	95	outb(0x08, 0xA1); /* Vector base */
	96	outb(0x02, 0xA1); /* Cascade (slave) on IRQ2 */
	97	outb(0x03, 0xA1); /* Select 8086 mode, auto eoi */
	98	outb(0x0A, 0xA0);
	99	outb(cached_irq_mask[1],0xA1);
	100	outb(cached_irq_mask[0],0x21);
	101	//request_region(0x20,0x2,"pic1");
	102	//request_region(0xA0,0x2,"pic2");
	103
	104	cascade.handler = bogus_int;
	105	cascade.name = "cascade";
	106	setup_irq(2,&cascade);
	107	}
	108