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ARM: shmobile: use machine specific hook for late init
[deliverable/linux.git] / arch / arm / mach-shmobile / board-ap4evb.c
CommitLineData
2b7eda63
MD		 1/*
2 * AP4EVB board support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
8eda2f21 20#include <linux/clk.h>
2b7eda63
MD		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
410d878b 27#include <linux/mfd/tmio.h>
341291a6 28#include <linux/mmc/host.h>
17e75d82 29#include <linux/mmc/sh_mobile_sdhi.h>
2b7eda63
MD		 30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h>
32#include <linux/mtd/physmap.h>
c8ee3d4b 33#include <linux/mmc/sh_mmcif.h>
91cf5082
KM		 34#include <linux/i2c.h>
35#include <linux/i2c/tsc2007.h>
2b7eda63 36#include <linux/io.h>
1b7e0677 37#include <linux/smsc911x.h>
cb9215e1
KM		 38#include <linux/sh_intc.h>
39#include <linux/sh_clk.h>
1b7e0677 40#include <linux/gpio.h>
17ccb834 41#include <linux/input.h>
2863e935 42#include <linux/leds.h>
17ccb834 43#include <linux/input/sh_keysc.h>
fb54d268 44#include <linux/usb/r8a66597.h>
b5e8d269 45#include <linux/pm_clock.h>
9b742024 46#include <linux/dma-mapping.h>
8eda2f21 47
1a0b1eac
GL		 48#include <media/sh_mobile_ceu.h>
49#include <media/sh_mobile_csi2.h>
50#include <media/soc_camera.h>
51
cb9215e1
KM		 52#include <sound/sh_fsi.h>
53
dfbcdf64 54#include <video/sh_mobile_hdmi.h>
8eda2f21
GL		 55#include <video/sh_mobile_lcdc.h>
56#include <video/sh_mipi_dsi.h>
57
2b7eda63 58#include <mach/common.h>
8eda2f21 59#include <mach/irqs.h>
1b7e0677 60#include <mach/sh7372.h>
8eda2f21 61
2b7eda63
MD		 62#include <asm/mach-types.h>
63#include <asm/mach/arch.h>
3d09fbcd 64#include <asm/setup.h>
2b7eda63 65
02624a17
KM		 66/*
67 * Address Interface BusWidth note
68 * ------------------------------------------------------------------
69 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON
70 * 0x0800_0000 user area -
71 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF
72 * 0x1400_0000 Ether (LAN9220) 16bit
73 * 0x1600_0000 user area - cannot use with NAND
74 * 0x1800_0000 user area -
75 * 0x1A00_0000 -
76 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit
77 */
78
79/*
80 * NOR Flash ROM
81 *
82 * SW1 | SW2 | SW7 | NOR Flash ROM
83 * bit1 | bit1 bit2 | bit1 | Memory allocation
84 * ------+------------+------+------------------
85 * OFF | ON OFF | ON | Area 0
86 * OFF | ON OFF | OFF | Area 4
87 */
88
89/*
90 * NAND Flash ROM
91 *
92 * SW1 | SW2 | SW7 | NAND Flash ROM
93 * bit1 | bit1 bit2 | bit2 | Memory allocation
94 * ------+------------+------+------------------
95 * OFF | ON OFF | ON | FCE 0
96 * OFF | ON OFF | OFF | FCE 1
97 */
98
99/*
100 * SMSC 9220
101 *
102 * SW1 SMSC 9220
103 * -----------------------
104 * ON access disable
105 * OFF access enable
106 */
107
17ccb834 108/*
dda128dc 109 * LCD / IRQ / KEYSC / IrDA
17ccb834 110 *
9fa1b7fe
KM		 111 * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen)
112 * LCD = 2nd LCDC (WVGA)
dda128dc
KM		 113 *
114 * | SW43 |
115 * SW3 | ON | OFF |
116 * -------------+-----------------------+---------------+
117 * ON | KEY / IrDA | LCD |
118 * OFF | KEY / IrDA / IRQ | IRQ |
9fa1b7fe
KM		 119 *
120 *
121 * QHD / WVGA display
122 *
123 * You can choice display type on menuconfig.
124 * Then, check above dip-switch.
17ccb834
KM		 125 */
126
fb54d268
KM		 127/*
128 * USB
129 *
130 * J7 : 1-2 MAX3355E VBUS
131 * 2-3 DC 5.0V
132 *
133 * S39: bit2: off
134 */
135
cb9215e1
KM		 136/*
137 * FSI/FSMI
138 *
139 * SW41 : ON : SH-Mobile AP4 Audio Mode
140 * : OFF : Bluetooth Audio Mode
141 */
142
c8ee3d4b 143/*
d3d03e48 144 * MMC0/SDHI1 (CN7)
c8ee3d4b 145 *
d3d03e48
KM		 146 * J22 : select card voltage
147 * 1-2 pin : 1.8v
148 * 2-3 pin : 3.3v
149 *
150 * SW1 | SW33
151 * | bit1 | bit2 | bit3 | bit4
152 * ------------+------+------+------+-------
153 * MMC0 OFF | OFF | ON | ON | X
154 * SDHI1 OFF | ON | X | OFF | ON
155 *
156 * voltage lebel
157 * CN7 : 1.8v
158 * CN12: 3.3v
c8ee3d4b
KM		 159 */
160
1b7e0677 161/* MTD */
2b7eda63
MD		 162static struct mtd_partition nor_flash_partitions[] = {
163 {
164 .name = "loader",
165 .offset = 0x00000000,
166 .size = 512 * 1024,
2e351ec6 167 .mask_flags = MTD_WRITEABLE,
2b7eda63
MD		 168 },
169 {
170 .name = "bootenv",
171 .offset = MTDPART_OFS_APPEND,
172 .size = 512 * 1024,
2e351ec6 173 .mask_flags = MTD_WRITEABLE,
2b7eda63
MD		 174 },
175 {
176 .name = "kernel_ro",
177 .offset = MTDPART_OFS_APPEND,
178 .size = 8 * 1024 * 1024,
179 .mask_flags = MTD_WRITEABLE,
180 },
181 {
182 .name = "kernel",
183 .offset = MTDPART_OFS_APPEND,
184 .size = 8 * 1024 * 1024,
185 },
186 {
187 .name = "data",
188 .offset = MTDPART_OFS_APPEND,
189 .size = MTDPART_SIZ_FULL,
190 },
191};
192
193static struct physmap_flash_data nor_flash_data = {
194 .width = 2,
195 .parts = nor_flash_partitions,
196 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
197};
198
199static struct resource nor_flash_resources[] = {
200 [0] = {
832217da 201 .start = 0x20000000, /* CS0 shadow instead of regular CS0 */
8e6a4675 202 .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
2b7eda63
MD		 203 .flags = IORESOURCE_MEM,
204 }
205};
206
207static struct platform_device nor_flash_device = {
208 .name = "physmap-flash",
209 .dev = {
210 .platform_data = &nor_flash_data,
211 },
212 .num_resources = ARRAY_SIZE(nor_flash_resources),
213 .resource = nor_flash_resources,
214};
215
1b7e0677
KM		 216/* SMSC 9220 */
217static struct resource smc911x_resources[] = {
218 {
219 .start = 0x14000000,
220 .end = 0x16000000 - 1,
221 .flags = IORESOURCE_MEM,
222 }, {
33c9607a 223 .start = evt2irq(0x02c0) /* IRQ6A */,
1b7e0677
KM		 224 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
225 },
226};
227
228static struct smsc911x_platform_config smsc911x_info = {
229 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
230 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
231 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
232};
233
234static struct platform_device smc911x_device = {
235 .name = "smsc911x",
236 .id = -1,
237 .num_resources = ARRAY_SIZE(smc911x_resources),
238 .resource = smc911x_resources,
239 .dev = {
240 .platform_data = &smsc911x_info,
241 },
242};
2b7eda63 243
68accd73
AH		 244/*
245 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
246 * connected to GPIO A22 of SH7372 (GPIO_PORT41).
247 */
248static int slot_cn7_get_cd(struct platform_device *pdev)
249{
ceb50f33 250 return !gpio_get_value(GPIO_PORT41);
68accd73 251}
1c7fcbed
D		 252/* MERAM */
253static struct sh_mobile_meram_info meram_info = {
254 .addr_mode = SH_MOBILE_MERAM_MODE1,
255};
256
257static struct resource meram_resources[] = {
258 [0] = {
e71504d5
LP		 259 .name = "regs",
260 .start = 0xe8000000,
261 .end = 0xe807ffff,
262 .flags = IORESOURCE_MEM,
263 },
264 [1] = {
265 .name = "meram",
266 .start = 0xe8080000,
267 .end = 0xe81fffff,
268 .flags = IORESOURCE_MEM,
1c7fcbed
D		 269 },
270};
271
272static struct platform_device meram_device = {
273 .name = "sh_mobile_meram",
274 .id = 0,
275 .num_resources = ARRAY_SIZE(meram_resources),
276 .resource = meram_resources,
277 .dev = {
278 .platform_data = &meram_info,
279 },
280};
68accd73 281
c8ee3d4b
KM		 282/* SH_MMCIF */
283static struct resource sh_mmcif_resources[] = {
284 [0] = {
0fb0834b 285 .name = "MMCIF",
c8ee3d4b
KM		 286 .start = 0xE6BD0000,
287 .end = 0xE6BD00FF,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 /* MMC ERR */
8d569341 292 .start = evt2irq(0x1ac0),
c8ee3d4b
KM		 293 .flags = IORESOURCE_IRQ,
294 },
295 [2] = {
296 /* MMC NOR */
8d569341 297 .start = evt2irq(0x1ae0),
c8ee3d4b
KM		 298 .flags = IORESOURCE_IRQ,
299 },
300};
301
bb04e197 302static struct sh_mmcif_plat_data sh_mmcif_plat = {
c8ee3d4b
KM		 303 .sup_pclk = 0,
304 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
305 .caps = MMC_CAP_4_BIT_DATA |
306 MMC_CAP_8_BIT_DATA |
307 MMC_CAP_NEEDS_POLL,
68accd73 308 .get_cd = slot_cn7_get_cd,
d5bb386d
GL		 309 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
310 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
c8ee3d4b
KM		 311};
312
313static struct platform_device sh_mmcif_device = {
314 .name = "sh_mmcif",
315 .id = 0,
316 .dev = {
317 .dma_mask = NULL,
318 .coherent_dma_mask = 0xffffffff,
319 .platform_data = &sh_mmcif_plat,
320 },
321 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
322 .resource = sh_mmcif_resources,
323};
324
3a14d039 325/* SDHI0 */
69bf6f45 326static struct sh_mobile_sdhi_info sdhi0_info = {
341291a6
GL		 327 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
328 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
330e4e71 329 .tmio_caps = MMC_CAP_SDIO_IRQ,
69bf6f45
GL		 330};
331
3a14d039
MD		 332static struct resource sdhi0_resources[] = {
333 [0] = {
334 .name = "SDHI0",
335 .start = 0xe6850000,
31d31fe7 336 .end = 0xe68500ff,
3a14d039
MD		 337 .flags = IORESOURCE_MEM,
338 },
339 [1] = {
2007aea1
SH		 340 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
341 .flags = IORESOURCE_IRQ,
342 },
343 [2] = {
344 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
345 .flags = IORESOURCE_IRQ,
346 },
347 [3] = {
348 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
349 .flags = IORESOURCE_IRQ,
3a14d039
MD		 350 },
351};
352
353static struct platform_device sdhi0_device = {
354 .name = "sh_mobile_sdhi",
355 .num_resources = ARRAY_SIZE(sdhi0_resources),
356 .resource = sdhi0_resources,
357 .id = 0,
69bf6f45
GL		 358 .dev = {
359 .platform_data = &sdhi0_info,
360 },
3a14d039
MD		 361};
362
341291a6
GL		 363/* SDHI1 */
364static struct sh_mobile_sdhi_info sdhi1_info = {
365 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
366 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
367 .tmio_ocr_mask = MMC_VDD_165_195,
410d878b 368 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
330e4e71 369 .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
68accd73 370 .get_cd = slot_cn7_get_cd,
341291a6
GL		 371};
372
373static struct resource sdhi1_resources[] = {
374 [0] = {
375 .name = "SDHI1",
376 .start = 0xe6860000,
31d31fe7 377 .end = 0xe68600ff,
341291a6
GL		 378 .flags = IORESOURCE_MEM,
379 },
380 [1] = {
2007aea1
SH		 381 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
382 .flags = IORESOURCE_IRQ,
383 },
384 [2] = {
385 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
386 .flags = IORESOURCE_IRQ,
387 },
388 [3] = {
389 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
390 .flags = IORESOURCE_IRQ,
341291a6
GL		 391 },
392};
393
394static struct platform_device sdhi1_device = {
395 .name = "sh_mobile_sdhi",
396 .num_resources = ARRAY_SIZE(sdhi1_resources),
397 .resource = sdhi1_resources,
398 .id = 1,
399 .dev = {
400 .platform_data = &sdhi1_info,
401 },
402};
403
fb54d268 404/* USB1 */
bb04e197 405static void usb1_host_port_power(int port, int power)
fb54d268
KM		 406{
407 if (!power) /* only power-on supported for now */
408 return;
409
410 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
411 __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
412}
413
414static struct r8a66597_platdata usb1_host_data = {
415 .on_chip = 1,
416 .port_power = usb1_host_port_power,
417};
418
419static struct resource usb1_host_resources[] = {
420 [0] = {
421 .name = "USBHS",
422 .start = 0xE68B0000,
423 .end = 0xE68B00E6 - 1,
424 .flags = IORESOURCE_MEM,
425 },
426 [1] = {
33c9607a 427 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
fb54d268
KM		 428 .flags = IORESOURCE_IRQ,
429 },
430};
431
432static struct platform_device usb1_host_device = {
433 .name = "r8a66597_hcd",
434 .id = 1,
435 .dev = {
436 .dma_mask = NULL, /* not use dma */
437 .coherent_dma_mask = 0xffffffff,
438 .platform_data = &usb1_host_data,
439 },
440 .num_resources = ARRAY_SIZE(usb1_host_resources),
441 .resource = usb1_host_resources,
442};
443
9fa1b7fe
KM		 444/*
445 * QHD display
446 */
447#ifdef CONFIG_AP4EVB_QHD
448
449/* KEYSC (Needs SW43 set to ON) */
450static struct sh_keysc_info keysc_info = {
451 .mode = SH_KEYSC_MODE_1,
452 .scan_timing = 3,
453 .delay = 2500,
454 .keycodes = {
455 KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
456 KEY_5, KEY_6, KEY_7, KEY_8, KEY_9,
457 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
458 KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
459 KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
460 },
461};
462
463static struct resource keysc_resources[] = {
464 [0] = {
465 .name = "KEYSC",
466 .start = 0xe61b0000,
467 .end = 0xe61b0063,
468 .flags = IORESOURCE_MEM,
469 },
470 [1] = {
471 .start = evt2irq(0x0be0), /* KEYSC_KEY */
472 .flags = IORESOURCE_IRQ,
473 },
474};
475
476static struct platform_device keysc_device = {
477 .name = "sh_keysc",
478 .id = 0, /* "keysc0" clock */
479 .num_resources = ARRAY_SIZE(keysc_resources),
480 .resource = keysc_resources,
481 .dev = {
482 .platform_data = &keysc_info,
483 },
484};
485
486/* MIPI-DSI */
5e47431a
KM		 487static int sh_mipi_set_dot_clock(struct platform_device *pdev,
488 void __iomem *base,
489 int enable)
490{
491 struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
5e47431a
KM		 492
493 if (IS_ERR(pck))
494 return PTR_ERR(pck);
495
496 if (enable) {
8f9c60f2
KM		 497 /*
498 * DSIPCLK = 24MHz
499 * D-PHY = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl)
500 * HsByteCLK = D-PHY/8 = 39MHz
501 *
502 * X * Y * FPS =
503 * (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz
504 */
5e47431a 505 clk_set_rate(pck, clk_round_rate(pck, 24000000));
5e47431a
KM		 506 clk_enable(pck);
507 } else {
508 clk_disable(pck);
509 }
510
511 clk_put(pck);
512
513 return 0;
514}
515
8eda2f21
GL		 516static struct resource mipidsi0_resources[] = {
517 [0] = {
518 .start = 0xffc60000,
5958d58a
MD		 519 .end = 0xffc63073,
520 .flags = IORESOURCE_MEM,
521 },
522 [1] = {
523 .start = 0xffc68000,
524 .end = 0xffc680ef,
8eda2f21
GL		 525 .flags = IORESOURCE_MEM,
526 },
527};
528
a1022adb
LP		 529static struct sh_mobile_lcdc_info lcdc_info;
530
8eda2f21
GL		 531static struct sh_mipi_dsi_info mipidsi0_info = {
532 .data_format = MIPI_RGB888,
9fa1b7fe 533 .lcd_chan = &lcdc_info.ch[0],
26c3d7ac 534 .lane = 2,
6fd46595 535 .vsynw_offset = 17,
8f9c60f2 536 .phyctrl = 0x6 << 8,
a2e62971
KM		 537 .flags = SH_MIPI_DSI_SYNC_PULSES_MODE |
538 SH_MIPI_DSI_HSbyteCLK,
5e47431a 539 .set_dot_clock = sh_mipi_set_dot_clock,
8eda2f21
GL		 540};
541
542static struct platform_device mipidsi0_device = {
543 .name = "sh-mipi-dsi",
544 .num_resources = ARRAY_SIZE(mipidsi0_resources),
545 .resource = mipidsi0_resources,
546 .id = 0,
547 .dev = {
548 .platform_data = &mipidsi0_info,
549 },
550};
551
9fa1b7fe
KM		 552static struct platform_device *qhd_devices[] __initdata = {
553 &mipidsi0_device,
554 &keysc_device,
555};
556#endif /* CONFIG_AP4EVB_QHD */
557
a1022adb
LP		 558/* LCDC0 */
559static const struct fb_videomode ap4evb_lcdc_modes[] = {
560 {
561#ifdef CONFIG_AP4EVB_QHD
562 .name = "R63302(QHD)",
563 .xres = 544,
564 .yres = 961,
565 .left_margin = 72,
566 .right_margin = 600,
567 .hsync_len = 16,
568 .upper_margin = 8,
569 .lower_margin = 8,
570 .vsync_len = 2,
571 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
572#else
573 .name = "WVGA Panel",
574 .xres = 800,
575 .yres = 480,
576 .left_margin = 220,
577 .right_margin = 110,
578 .hsync_len = 70,
579 .upper_margin = 20,
580 .lower_margin = 5,
581 .vsync_len = 5,
582 .sync = 0,
583#endif
584 },
585};
c241a0e0
LP		 586
587static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
a1022adb 588 .icb[0] = {
a1022adb
LP		 589 .meram_size = 0x40,
590 },
591 .icb[1] = {
a1022adb
LP		 592 .meram_size = 0x40,
593 },
594};
595
596static struct sh_mobile_lcdc_info lcdc_info = {
597 .meram_dev = &meram_info,
598 .ch[0] = {
599 .chan = LCDC_CHAN_MAINLCD,
600 .fourcc = V4L2_PIX_FMT_RGB565,
93ff2598
LP		 601 .lcd_modes = ap4evb_lcdc_modes,
602 .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes),
a1022adb
LP		 603 .meram_cfg = &lcd_meram_cfg,
604#ifdef CONFIG_AP4EVB_QHD
605 .tx_dev = &mipidsi0_device,
606#endif
607 }
608};
609
610static struct resource lcdc_resources[] = {
611 [0] = {
612 .name = "LCDC",
613 .start = 0xfe940000, /* P4-only space */
614 .end = 0xfe943fff,
615 .flags = IORESOURCE_MEM,
616 },
617 [1] = {
618 .start = intcs_evt2irq(0x580),
619 .flags = IORESOURCE_IRQ,
620 },
621};
622
623static struct platform_device lcdc_device = {
624 .name = "sh_mobile_lcdc_fb",
625 .num_resources = ARRAY_SIZE(lcdc_resources),
626 .resource = lcdc_resources,
627 .dev = {
628 .platform_data = &lcdc_info,
629 .coherent_dma_mask = ~0,
630 },
631};
632
cb9215e1
KM		 633/* FSI */
634#define IRQ_FSI evt2irq(0x1840)
d4bc99b9
KM		 635static int __fsi_set_rate(struct clk *clk, long rate, int enable)
636{
637 int ret = 0;
638
639 if (rate <= 0)
640 return ret;
2669efec 641
d4bc99b9 642 if (enable) {
22de4e1f 643 ret = clk_set_rate(clk, rate);
d4bc99b9
KM		 644 if (0 == ret)
645 ret = clk_enable(clk);
646 } else {
647 clk_disable(clk);
648 }
649
650 return ret;
651}
652
22de4e1f
KM		 653static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
654{
655 return __fsi_set_rate(clk, clk_round_rate(clk, rate), enable);
656}
657
658static int fsi_ak4642_set_rate(struct device *dev, int rate, int enable)
659{
660 struct clk *fsia_ick;
661 struct clk *fsiack;
662 int ret = -EIO;
663
664 fsia_ick = clk_get(dev, "icka");
665 if (IS_ERR(fsia_ick))
666 return PTR_ERR(fsia_ick);
667
668 /*
669 * FSIACK is connected to AK4642,
670 * and use external clock pin from it.
671 * it is parent of fsia_ick now.
672 */
673 fsiack = clk_get_parent(fsia_ick);
674 if (!fsiack)
675 goto fsia_ick_out;
676
677 /*
678 * we get 1/1 divided clock by setting same rate to fsiack and fsia_ick
679 *
680 ** FIXME **
681 * Because the freq_table of external clk (fsiack) are all 0,
682 * the return value of clk_round_rate became 0.
683 * So, it use __fsi_set_rate here.
684 */
685 ret = __fsi_set_rate(fsiack, rate, enable);
686 if (ret < 0)
687 goto fsiack_out;
688
689 ret = __fsi_set_round_rate(fsia_ick, rate, enable);
690 if ((ret < 0) && enable)
691 __fsi_set_round_rate(fsiack, rate, 0); /* disable FSI ACK */
692
693fsiack_out:
694 clk_put(fsiack);
695
696fsia_ick_out:
697 clk_put(fsia_ick);
698
699 return 0;
700}
701
702static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
2669efec
KM		 703{
704 struct clk *fsib_clk;
705 struct clk *fdiv_clk = &sh7372_fsidivb_clk;
d4bc99b9
KM		 706 long fsib_rate = 0;
707 long fdiv_rate = 0;
708 int ackmd_bpfmd;
2669efec
KM		 709 int ret;
710
2669efec 711 switch (rate) {
574490e3 712 case 44100:
d4bc99b9
KM		 713 fsib_rate = rate * 256;
714 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
574490e3 715 break;
2669efec 716 case 48000:
d4bc99b9
KM		 717 fsib_rate = 85428000; /* around 48kHz x 256 x 7 */
718 fdiv_rate = rate * 256;
719 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
2669efec
KM		 720 break;
721 default:
722 pr_err("unsupported rate in FSI2 port B\n");
d4bc99b9 723 return -EINVAL;
2669efec
KM		 724 }
725
d4bc99b9
KM		 726 /* FSI B setting */
727 fsib_clk = clk_get(dev, "ickb");
728 if (IS_ERR(fsib_clk))
729 return -EIO;
730
22de4e1f 731 ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
d4bc99b9 732 if (ret < 0)
73674648 733 goto fsi_set_rate_end;
d4bc99b9
KM		 734
735 /* FSI DIV setting */
22de4e1f 736 ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
d4bc99b9
KM		 737 if (ret < 0) {
738 /* disable FSI B */
739 if (enable)
22de4e1f 740 __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
73674648 741 goto fsi_set_rate_end;
d4bc99b9 742 }
2669efec 743
73674648
KM		 744 ret = ackmd_bpfmd;
745
746fsi_set_rate_end:
747 clk_put(fsib_clk);
748 return ret;
2669efec
KM		 749}
750
bb04e197 751static struct sh_fsi_platform_info fsi_info = {
fec691e7
KM		 752 .port_a = {
753 .flags = SH_FSI_BRS_INV,
754 .set_rate = fsi_ak4642_set_rate,
755 },
756 .port_b = {
757 .flags = SH_FSI_BRS_INV |
758 SH_FSI_BRM_INV |
759 SH_FSI_LRS_INV |
760 SH_FSI_FMT_SPDIF,
761 .set_rate = fsi_hdmi_set_rate,
762 },
cb9215e1
KM		 763};
764
765static struct resource fsi_resources[] = {
766 [0] = {
767 .name = "FSI",
768 .start = 0xFE3C0000,
769 .end = 0xFE3C0400 - 1,
770 .flags = IORESOURCE_MEM,
771 },
772 [1] = {
773 .start = IRQ_FSI,
774 .flags = IORESOURCE_IRQ,
775 },
776};
777
778static struct platform_device fsi_device = {
779 .name = "sh_fsi2",
9f6f11b6 780 .id = -1,
cb9215e1
KM		 781 .num_resources = ARRAY_SIZE(fsi_resources),
782 .resource = fsi_resources,
783 .dev = {
784 .platform_data = &fsi_info,
785 },
786};
787
45f31216
KM		 788static struct fsi_ak4642_info fsi2_ak4643_info = {
789 .name = "AK4643",
790 .card = "FSI2A-AK4643",
791 .cpu_dai = "fsia-dai",
792 .codec = "ak4642-codec.0-0013",
793 .platform = "sh_fsi2",
794 .id = FSI_PORT_A,
795};
796
c8d6bf9a 797static struct platform_device fsi_ak4643_device = {
45f31216
KM		 798 .name = "fsi-ak4642-audio",
799 .dev = {
e49d603c 800 .platform_data = &fsi2_ak4643_info,
45f31216 801 },
c8d6bf9a 802};
45f31216 803
a1022adb 804/* LCDC1 */
640dcfa0
GL		 805static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
806 unsigned long *parent_freq);
807
dfbcdf64 808static struct sh_mobile_hdmi_info hdmi_info = {
2669efec 809 .flags = HDMI_SND_SRC_SPDIF,
640dcfa0 810 .clk_optimize_parent = ap4evb_clk_optimize,
dfbcdf64
GL		 811};
812
813static struct resource hdmi_resources[] = {
814 [0] = {
815 .name = "HDMI",
816 .start = 0xe6be0000,
817 .end = 0xe6be00ff,
818 .flags = IORESOURCE_MEM,
819 },
820 [1] = {
821 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
822 .start = evt2irq(0x17e0),
823 .flags = IORESOURCE_IRQ,
824 },
825};
826
827static struct platform_device hdmi_device = {
828 .name = "sh-mobile-hdmi",
829 .num_resources = ARRAY_SIZE(hdmi_resources),
830 .resource = hdmi_resources,
831 .id = -1,
832 .dev = {
833 .platform_data = &hdmi_info,
834 },
835};
836
640dcfa0
GL		 837static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
838 unsigned long *parent_freq)
839{
840 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
841 long error;
842
843 if (IS_ERR(hdmi_ick)) {
844 int ret = PTR_ERR(hdmi_ick);
845 pr_err("Cannot get HDMI ICK: %d\n", ret);
846 return ret;
847 }
848
849 error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
850
851 clk_put(hdmi_ick);
852
853 return error;
854}
855
c241a0e0 856static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
1c7fcbed 857 .icb[0] = {
1c7fcbed
D		 858 .meram_size = 0x100,
859 },
860 .icb[1] = {
1c7fcbed
D		 861 .meram_size = 0x100,
862 },
863};
c8d6bf9a 864
dfbcdf64
GL		 865static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
866 .clock_source = LCDC_CLK_EXTERNAL,
1c7fcbed 867 .meram_dev = &meram_info,
dfbcdf64
GL		 868 .ch[0] = {
869 .chan = LCDC_CHAN_MAINLCD,
edd153a3 870 .fourcc = V4L2_PIX_FMT_RGB565,
dfbcdf64
GL		 871 .interface_type = RGB24,
872 .clock_divider = 1,
873 .flags = LCDC_FLAGS_DWPOL,
1c7fcbed 874 .meram_cfg = &hdmi_meram_cfg,
a1022adb 875 .tx_dev = &hdmi_device,
dfbcdf64
GL		 876 }
877};
878
879static struct resource lcdc1_resources[] = {
880 [0] = {
881 .name = "LCDC1",
882 .start = 0xfe944000,
883 .end = 0xfe947fff,
884 .flags = IORESOURCE_MEM,
885 },
886 [1] = {
88c759a2 887 .start = intcs_evt2irq(0x1780),
dfbcdf64
GL		 888 .flags = IORESOURCE_IRQ,
889 },
890};
891
892static struct platform_device lcdc1_device = {
893 .name = "sh_mobile_lcdc_fb",
894 .num_resources = ARRAY_SIZE(lcdc1_resources),
895 .resource = lcdc1_resources,
896 .id = 1,
897 .dev = {
898 .platform_data = &sh_mobile_lcdc1_info,
899 .coherent_dma_mask = ~0,
900 },
901};
902
3f25c9cc
KM		 903static struct platform_device fsi_hdmi_device = {
904 .name = "sh_fsi2_b_hdmi",
905};
906
2863e935
AH		 907static struct gpio_led ap4evb_leds[] = {
908 {
909 .name = "led4",
910 .gpio = GPIO_PORT185,
911 .default_state = LEDS_GPIO_DEFSTATE_ON,
912 },
913 {
914 .name = "led2",
915 .gpio = GPIO_PORT186,
916 .default_state = LEDS_GPIO_DEFSTATE_ON,
917 },
918 {
919 .name = "led3",
920 .gpio = GPIO_PORT187,
921 .default_state = LEDS_GPIO_DEFSTATE_ON,
922 },
923 {
924 .name = "led1",
925 .gpio = GPIO_PORT188,
926 .default_state = LEDS_GPIO_DEFSTATE_ON,
927 }
928};
929
930static struct gpio_led_platform_data ap4evb_leds_pdata = {
931 .num_leds = ARRAY_SIZE(ap4evb_leds),
8050fbf2 932 .leds = ap4evb_leds,
2863e935
AH		 933};
934
935static struct platform_device leds_device = {
936 .name = "leds-gpio",
937 .id = 0,
938 .dev = {
939 .platform_data = &ap4evb_leds_pdata,
940 },
941};
942
1a0b1eac
GL		 943static struct i2c_board_info imx074_info = {
944 I2C_BOARD_INFO("imx074", 0x1a),
945};
946
4d4d6fbb 947static struct soc_camera_link imx074_link = {
1a0b1eac
GL		 948 .bus_id = 0,
949 .board_info = &imx074_info,
950 .i2c_adapter_id = 0,
951 .module_name = "imx074",
952};
953
954static struct platform_device ap4evb_camera = {
955 .name = "soc-camera-pdrv",
956 .id = 0,
957 .dev = {
958 .platform_data = &imx074_link,
959 },
960};
961
962static struct sh_csi2_client_config csi2_clients[] = {
963 {
964 .phy = SH_CSI2_PHY_MAIN,
19a1780b 965 .lanes = 0, /* default: 2 lanes */
1a0b1eac
GL		 966 .channel = 0,
967 .pdev = &ap4evb_camera,
968 },
969};
970
971static struct sh_csi2_pdata csi2_info = {
972 .type = SH_CSI2C,
973 .clients = csi2_clients,
974 .num_clients = ARRAY_SIZE(csi2_clients),
975 .flags = SH_CSI2_ECC | SH_CSI2_CRC,
976};
977
978static struct resource csi2_resources[] = {
979 [0] = {
980 .name = "CSI2",
981 .start = 0xffc90000,
982 .end = 0xffc90fff,
983 .flags = IORESOURCE_MEM,
984 },
985 [1] = {
986 .start = intcs_evt2irq(0x17a0),
987 .flags = IORESOURCE_IRQ,
988 },
989};
990
6b526fed
GL		 991static struct sh_mobile_ceu_companion csi2 = {
992 .id = 0,
1a0b1eac
GL		 993 .num_resources = ARRAY_SIZE(csi2_resources),
994 .resource = csi2_resources,
6b526fed 995 .platform_data = &csi2_info,
1a0b1eac
GL		 996};
997
998static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
999 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
6b526fed 1000 .csi2 = &csi2,
1a0b1eac
GL		 1001};
1002
1003static struct resource ceu_resources[] = {
1004 [0] = {
1005 .name = "CEU",
1006 .start = 0xfe910000,
1007 .end = 0xfe91009f,
1008 .flags = IORESOURCE_MEM,
1009 },
1010 [1] = {
1011 .start = intcs_evt2irq(0x880),
1012 .flags = IORESOURCE_IRQ,
1013 },
1014 [2] = {
1015 /* place holder for contiguous memory */
1016 },
1017};
1018
1019static struct platform_device ceu_device = {
1020 .name = "sh_mobile_ceu",
1021 .id = 0, /* "ceu0" clock */
1022 .num_resources = ARRAY_SIZE(ceu_resources),
1023 .resource = ceu_resources,
1024 .dev = {
05a5f01c
GL		 1025 .platform_data = &sh_mobile_ceu_info,
1026 .coherent_dma_mask = 0xffffffff,
1a0b1eac
GL		 1027 },
1028};
1029
2b7eda63 1030static struct platform_device *ap4evb_devices[] __initdata = {
2863e935 1031 &leds_device,
2b7eda63 1032 &nor_flash_device,
1b7e0677 1033 &smc911x_device,
3a14d039 1034 &sdhi0_device,
341291a6 1035 &sdhi1_device,
fb54d268 1036 &usb1_host_device,
cb9215e1 1037 &fsi_device,
c8d6bf9a 1038 &fsi_ak4643_device,
3f25c9cc 1039 &fsi_hdmi_device,
beccb12f 1040 &sh_mmcif_device,
dfbcdf64 1041 &hdmi_device,
a1022adb
LP		 1042 &lcdc_device,
1043 &lcdc1_device,
1a0b1eac
GL		 1044 &ceu_device,
1045 &ap4evb_camera,
1c7fcbed 1046 &meram_device,
2b7eda63
MD		 1047};
1048
2ce51f8b 1049static void __init hdmi_init_pm_clock(void)
dfbcdf64
GL		 1050{
1051 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
1052 int ret;
1053 long rate;
1054
1055 if (IS_ERR(hdmi_ick)) {
1056 ret = PTR_ERR(hdmi_ick);
1057 pr_err("Cannot get HDMI ICK: %d\n", ret);
1058 goto out;
1059 }
1060
685e4080 1061 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
dfbcdf64 1062 if (ret < 0) {
685e4080 1063 pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
dfbcdf64
GL		 1064 goto out;
1065 }
1066
685e4080 1067 pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
dfbcdf64 1068
685e4080 1069 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
dfbcdf64
GL		 1070 if (rate < 0) {
1071 pr_err("Cannot get suitable rate: %ld\n", rate);
1072 ret = rate;
1073 goto out;
1074 }
1075
685e4080 1076 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
dfbcdf64
GL		 1077 if (ret < 0) {
1078 pr_err("Cannot set rate %ld: %d\n", rate, ret);
1079 goto out;
1080 }
1081
1082 pr_debug("PLLC2 set frequency %lu\n", rate);
1083
685e4080 1084 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
2ce51f8b 1085 if (ret < 0)
dfbcdf64 1086 pr_err("Cannot set HDMI parent: %d\n", ret);
dfbcdf64
GL		 1087
1088out:
1089 if (!IS_ERR(hdmi_ick))
1090 clk_put(hdmi_ick);
dfbcdf64
GL		 1091}
1092
6084c81e 1093static void __init fsi_init_pm_clock(void)
69ce8aa4
KM		 1094{
1095 struct clk *fsia_ick;
1096 int ret;
1097
69ce8aa4
KM		 1098 fsia_ick = clk_get(&fsi_device.dev, "icka");
1099 if (IS_ERR(fsia_ick)) {
1100 ret = PTR_ERR(fsia_ick);
1101 pr_err("Cannot get FSI ICK: %d\n", ret);
6084c81e 1102 return;
69ce8aa4
KM		 1103 }
1104
1105 ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk);
69ce8aa4 1106 if (ret < 0)
22de4e1f 1107 pr_err("Cannot set FSI-A parent: %d\n", ret);
69ce8aa4 1108
69ce8aa4 1109 clk_put(fsia_ick);
69ce8aa4 1110}
69ce8aa4 1111
71c3ba9a
KM		 1112/*
1113 * FIXME !!
1114 *
1115 * gpio_no_direction
71c3ba9a
KM		 1116 * are quick_hack.
1117 *
1118 * current gpio frame work doesn't have
1119 * the method to control only pull up/down/free.
1120 * this function should be replaced by correct gpio function
1121 */
1122static void __init gpio_no_direction(u32 addr)
1123{
1124 __raw_writeb(0x00, addr);
1125}
1126
9fa1b7fe 1127/* TouchScreen */
52d5ac00
KM		 1128#ifdef CONFIG_AP4EVB_QHD
1129# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
1130# define GPIO_TSC_PORT GPIO_PORT123
1131#else /* WVGA */
1132# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
1133# define GPIO_TSC_PORT GPIO_PORT40
1134#endif
1135
33c9607a 1136#define IRQ28 evt2irq(0x3380) /* IRQ28A */
9fa1b7fe 1137#define IRQ7 evt2irq(0x02e0) /* IRQ7A */
71c3ba9a
KM		 1138static int ts_get_pendown_state(void)
1139{
52d5ac00 1140 int val;
71c3ba9a 1141
52d5ac00 1142 gpio_free(GPIO_TSC_IRQ);
71c3ba9a 1143
52d5ac00 1144 gpio_request(GPIO_TSC_PORT, NULL);
71c3ba9a 1145
52d5ac00 1146 gpio_direction_input(GPIO_TSC_PORT);
71c3ba9a 1147
52d5ac00 1148 val = gpio_get_value(GPIO_TSC_PORT);
71c3ba9a 1149
52d5ac00 1150 gpio_request(GPIO_TSC_IRQ, NULL);
71c3ba9a 1151
52d5ac00 1152 return !val;
71c3ba9a
KM		 1153}
1154
71c3ba9a
KM		 1155static int ts_init(void)
1156{
52d5ac00 1157 gpio_request(GPIO_TSC_IRQ, NULL);
71c3ba9a
KM		 1158
1159 return 0;
1160}
1161
bb04e197 1162static struct tsc2007_platform_data tsc2007_info = {
91cf5082
KM		 1163 .model = 2007,
1164 .x_plate_ohms = 180,
71c3ba9a
KM		 1165 .get_pendown_state = ts_get_pendown_state,
1166 .init_platform_hw = ts_init,
91cf5082
KM		 1167};
1168
9fa1b7fe
KM		 1169static struct i2c_board_info tsc_device = {
1170 I2C_BOARD_INFO("tsc2007", 0x48),
1171 .type = "tsc2007",
1172 .platform_data = &tsc2007_info,
1173 /*.irq is selected on ap4evb_init */
1174};
1175
91cf5082 1176/* I2C */
cb9215e1
KM		 1177static struct i2c_board_info i2c0_devices[] = {
1178 {
1179 I2C_BOARD_INFO("ak4643", 0x13),
1180 },
1181};
1182
91cf5082 1183static struct i2c_board_info i2c1_devices[] = {
8fc883c2
KM		 1184 {
1185 I2C_BOARD_INFO("r2025sd", 0x32),
1186 },
91cf5082
KM		 1187};
1188
2b7eda63 1189
cb9215e1
KM		 1190#define GPIO_PORT9CR 0xE6051009
1191#define GPIO_PORT10CR 0xE605100A
2669efec 1192#define USCCR1 0xE6058144
2b7eda63
MD		 1193static void __init ap4evb_init(void)
1194{
dfbcdf64 1195 u32 srcr4;
cb9215e1
KM		 1196 struct clk *clk;
1197
e3b0161b
MD		 1198 /* External clock source */
1199 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1200
1b7e0677
KM		 1201 sh7372_pinmux_init();
1202
b228b48e
KM		 1203 /* enable SCIFA0 */
1204 gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
1205 gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
1206
1b7e0677
KM		 1207 /* enable SMSC911X */
1208 gpio_request(GPIO_FN_CS5A, NULL);
1209 gpio_request(GPIO_FN_IRQ6_39, NULL);
1210
8cb3a2eb
KM		 1211 /* enable Debug switch (S6) */
1212 gpio_request(GPIO_PORT32, NULL);
1213 gpio_request(GPIO_PORT33, NULL);
1214 gpio_request(GPIO_PORT34, NULL);
1215 gpio_request(GPIO_PORT35, NULL);
1216 gpio_direction_input(GPIO_PORT32);
1217 gpio_direction_input(GPIO_PORT33);
1218 gpio_direction_input(GPIO_PORT34);
1219 gpio_direction_input(GPIO_PORT35);
1220 gpio_export(GPIO_PORT32, 0);
1221 gpio_export(GPIO_PORT33, 0);
1222 gpio_export(GPIO_PORT34, 0);
1223 gpio_export(GPIO_PORT35, 0);
1224
3a14d039
MD		 1225 /* SDHI0 */
1226 gpio_request(GPIO_FN_SDHICD0, NULL);
1227 gpio_request(GPIO_FN_SDHIWP0, NULL);
1228 gpio_request(GPIO_FN_SDHICMD0, NULL);
1229 gpio_request(GPIO_FN_SDHICLK0, NULL);
1230 gpio_request(GPIO_FN_SDHID0_3, NULL);
1231 gpio_request(GPIO_FN_SDHID0_2, NULL);
1232 gpio_request(GPIO_FN_SDHID0_1, NULL);
1233 gpio_request(GPIO_FN_SDHID0_0, NULL);
1234
9fa1b7fe
KM		 1235 /* SDHI1 */
1236 gpio_request(GPIO_FN_SDHICMD1, NULL);
1237 gpio_request(GPIO_FN_SDHICLK1, NULL);
1238 gpio_request(GPIO_FN_SDHID1_3, NULL);
1239 gpio_request(GPIO_FN_SDHID1_2, NULL);
1240 gpio_request(GPIO_FN_SDHID1_1, NULL);
1241 gpio_request(GPIO_FN_SDHID1_0, NULL);
91cf5082 1242
c8ee3d4b
KM		 1243 /* MMCIF */
1244 gpio_request(GPIO_FN_MMCD0_0, NULL);
1245 gpio_request(GPIO_FN_MMCD0_1, NULL);
1246 gpio_request(GPIO_FN_MMCD0_2, NULL);
1247 gpio_request(GPIO_FN_MMCD0_3, NULL);
1248 gpio_request(GPIO_FN_MMCD0_4, NULL);
1249 gpio_request(GPIO_FN_MMCD0_5, NULL);
1250 gpio_request(GPIO_FN_MMCD0_6, NULL);
1251 gpio_request(GPIO_FN_MMCD0_7, NULL);
1252 gpio_request(GPIO_FN_MMCCMD0, NULL);
1253 gpio_request(GPIO_FN_MMCCLK0, NULL);
1254
fb54d268
KM		 1255 /* USB enable */
1256 gpio_request(GPIO_FN_VBUS0_1, NULL);
1257 gpio_request(GPIO_FN_IDIN_1_18, NULL);
1258 gpio_request(GPIO_FN_PWEN_1_115, NULL);
1259 gpio_request(GPIO_FN_OVCN_1_114, NULL);
1260 gpio_request(GPIO_FN_EXTLP_1, NULL);
1261 gpio_request(GPIO_FN_OVCN2_1, NULL);
1262
1263 /* setup USB phy */
d0fb0c4b 1264 __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */
fb54d268 1265
2669efec 1266 /* enable FSI2 port A (ak4643) */
cb9215e1
KM		 1267 gpio_request(GPIO_FN_FSIAIBT, NULL);
1268 gpio_request(GPIO_FN_FSIAILR, NULL);
1269 gpio_request(GPIO_FN_FSIAISLD, NULL);
1270 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1271 gpio_request(GPIO_PORT161, NULL);
1272 gpio_direction_output(GPIO_PORT161, 0); /* slave */
1273
1274 gpio_request(GPIO_PORT9, NULL);
1275 gpio_request(GPIO_PORT10, NULL);
1276 gpio_no_direction(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1277 gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
1278
68accd73
AH		 1279 /* card detect pin for MMC slot (CN7) */
1280 gpio_request(GPIO_PORT41, NULL);
1281 gpio_direction_input(GPIO_PORT41);
1282
2669efec
KM		 1283 /* setup FSI2 port B (HDMI) */
1284 gpio_request(GPIO_FN_FSIBCK, NULL);
1285 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
1286
cb9215e1
KM		 1287 /* set SPU2 clock to 119.6 MHz */
1288 clk = clk_get(NULL, "spu_clk");
2ae2b766 1289 if (!IS_ERR(clk)) {
cb9215e1
KM		 1290 clk_set_rate(clk, clk_round_rate(clk, 119600000));
1291 clk_put(clk);
1292 }
1293
cb9215e1
KM		 1294 /*
1295 * set irq priority, to avoid sound chopping
1296 * when NFS rootfs is used
1297 * FSI(3) > SMSC911X(2)
1298 */
1299 intc_set_priority(IRQ_FSI, 3);
1300
1301 i2c_register_board_info(0, i2c0_devices,
1302 ARRAY_SIZE(i2c0_devices));
1303
1304 i2c_register_board_info(1, i2c1_devices,
1305 ARRAY_SIZE(i2c1_devices));
1306
9fa1b7fe 1307#ifdef CONFIG_AP4EVB_QHD
dd8a61a7 1308
9fa1b7fe 1309 /*
dd8a61a7
MD		 1310 * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
1311 * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
9fa1b7fe
KM		 1312 */
1313
1314 /* enable KEYSC */
1315 gpio_request(GPIO_FN_KEYOUT0, NULL);
1316 gpio_request(GPIO_FN_KEYOUT1, NULL);
1317 gpio_request(GPIO_FN_KEYOUT2, NULL);
1318 gpio_request(GPIO_FN_KEYOUT3, NULL);
1319 gpio_request(GPIO_FN_KEYOUT4, NULL);
1320 gpio_request(GPIO_FN_KEYIN0_136, NULL);
1321 gpio_request(GPIO_FN_KEYIN1_135, NULL);
1322 gpio_request(GPIO_FN_KEYIN2_134, NULL);
1323 gpio_request(GPIO_FN_KEYIN3_133, NULL);
1324 gpio_request(GPIO_FN_KEYIN4, NULL);
1325
1326 /* enable TouchScreen */
6845664a 1327 irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
9fa1b7fe
KM		 1328
1329 tsc_device.irq = IRQ28;
1330 i2c_register_board_info(1, &tsc_device, 1);
1331
1332 /* LCDC0 */
1333 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
1334 lcdc_info.ch[0].interface_type = RGB24;
1335 lcdc_info.ch[0].clock_divider = 1;
1336 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
afaad83b
LP		 1337 lcdc_info.ch[0].panel_cfg.width = 44;
1338 lcdc_info.ch[0].panel_cfg.height = 79;
9fa1b7fe
KM		 1339
1340 platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
1341
1342#else
1343 /*
dd8a61a7
MD		 1344 * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
1345 * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
9fa1b7fe 1346 */
dd8a61a7 1347
9fa1b7fe
KM		 1348 gpio_request(GPIO_FN_LCDD17, NULL);
1349 gpio_request(GPIO_FN_LCDD16, NULL);
1350 gpio_request(GPIO_FN_LCDD15, NULL);
1351 gpio_request(GPIO_FN_LCDD14, NULL);
1352 gpio_request(GPIO_FN_LCDD13, NULL);
1353 gpio_request(GPIO_FN_LCDD12, NULL);
1354 gpio_request(GPIO_FN_LCDD11, NULL);
1355 gpio_request(GPIO_FN_LCDD10, NULL);
1356 gpio_request(GPIO_FN_LCDD9, NULL);
1357 gpio_request(GPIO_FN_LCDD8, NULL);
1358 gpio_request(GPIO_FN_LCDD7, NULL);
1359 gpio_request(GPIO_FN_LCDD6, NULL);
1360 gpio_request(GPIO_FN_LCDD5, NULL);
1361 gpio_request(GPIO_FN_LCDD4, NULL);
1362 gpio_request(GPIO_FN_LCDD3, NULL);
1363 gpio_request(GPIO_FN_LCDD2, NULL);
1364 gpio_request(GPIO_FN_LCDD1, NULL);
1365 gpio_request(GPIO_FN_LCDD0, NULL);
1366 gpio_request(GPIO_FN_LCDDISP, NULL);
1367 gpio_request(GPIO_FN_LCDDCK, NULL);
1368
1369 gpio_request(GPIO_PORT189, NULL); /* backlight */
1370 gpio_direction_output(GPIO_PORT189, 1);
1371
1372 gpio_request(GPIO_PORT151, NULL); /* LCDDON */
1373 gpio_direction_output(GPIO_PORT151, 1);
1374
1375 lcdc_info.clock_source = LCDC_CLK_BUS;
1376 lcdc_info.ch[0].interface_type = RGB18;
f60cb470 1377 lcdc_info.ch[0].clock_divider = 3;
9fa1b7fe 1378 lcdc_info.ch[0].flags = 0;
afaad83b
LP		 1379 lcdc_info.ch[0].panel_cfg.width = 152;
1380 lcdc_info.ch[0].panel_cfg.height = 91;
9fa1b7fe
KM		 1381
1382 /* enable TouchScreen */
6845664a 1383 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
9fa1b7fe
KM		 1384
1385 tsc_device.irq = IRQ7;
1386 i2c_register_board_info(0, &tsc_device, 1);
1387#endif /* CONFIG_AP4EVB_QHD */
341291a6 1388
1a0b1eac
GL		 1389 /* CEU */
1390
1391 /*
1392 * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
1393 * becomes available
1394 */
1395
1396 /* MIPI-CSI stuff */
1397 gpio_request(GPIO_FN_VIO_CKO, NULL);
1398
1399 clk = clk_get(NULL, "vck1_clk");
1400 if (!IS_ERR(clk)) {
1401 clk_set_rate(clk, clk_round_rate(clk, 13000000));
1402 clk_enable(clk);
1403 clk_put(clk);
1404 }
1405
2b7eda63
MD		 1406 sh7372_add_standard_devices();
1407
dfbcdf64
GL		 1408 /* HDMI */
1409 gpio_request(GPIO_FN_HDMI_HPD, NULL);
1410 gpio_request(GPIO_FN_HDMI_CEC, NULL);
1411
1412 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
1413#define SRCR4 0xe61580bc
1414 srcr4 = __raw_readl(SRCR4);
1415 __raw_writel(srcr4 | (1 << 13), SRCR4);
1416 udelay(50);
1417 __raw_writel(srcr4 & ~(1 << 13), SRCR4);
1418
2b7eda63 1419 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
2ce51f8b 1420
96f7934e
MD		 1421 sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc1_device);
1422 sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
c1ba5bb5 1423 sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
96f7934e 1424
d93f5cde
MD		 1425 sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
1426 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
1427 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
382414b9 1428 sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
d93f5cde 1429
2ce51f8b 1430 hdmi_init_pm_clock();
6084c81e 1431 fsi_init_pm_clock();
97991657 1432 sh7372_pm_init();
a41b6466 1433 pm_clk_add(&fsi_device.dev, "spu2");
d0168fdc 1434 pm_clk_add(&lcdc1_device.dev, "hdmi");
2b7eda63
MD		 1435}
1436
1437MACHINE_START(AP4EVB, "ap4evb")
5d7220ec
MD		 1438 .map_io = sh7372_map_io,
1439 .init_early = sh7372_add_early_devices,
2b7eda63 1440 .init_irq = sh7372_init_irq,
863b1719 1441 .handle_irq = shmobile_handle_irq_intc,
2b7eda63 1442 .init_machine = ap4evb_init,
21cc1b7e 1443 .init_late = shmobile_init_late,
17254bff 1444 .timer = &shmobile_timer,
2b7eda63 1445MACHINE_END
Linux kernel - Deliverables
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