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ARM: shmobile: ap4evb: Simplify tsc2007 pen state read function
[deliverable/linux.git] / arch / arm / mach-shmobile / board-ap4evb.c
CommitLineData
2b7eda63
MD		 1/*
2 * AP4EVB board support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
8eda2f21 20#include <linux/clk.h>
2b7eda63
MD		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
410d878b 27#include <linux/mfd/tmio.h>
341291a6 28#include <linux/mmc/host.h>
17e75d82 29#include <linux/mmc/sh_mobile_sdhi.h>
2b7eda63
MD		 30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h>
32#include <linux/mtd/physmap.h>
c8ee3d4b 33#include <linux/mmc/sh_mmcif.h>
91cf5082
KM		 34#include <linux/i2c.h>
35#include <linux/i2c/tsc2007.h>
2b7eda63 36#include <linux/io.h>
e6bd960e 37#include <linux/pinctrl/machine.h>
8778b8f4
GL		 38#include <linux/regulator/fixed.h>
39#include <linux/regulator/machine.h>
1b7e0677 40#include <linux/smsc911x.h>
cb9215e1
KM		 41#include <linux/sh_intc.h>
42#include <linux/sh_clk.h>
1b7e0677 43#include <linux/gpio.h>
17ccb834 44#include <linux/input.h>
2863e935 45#include <linux/leds.h>
17ccb834 46#include <linux/input/sh_keysc.h>
fb54d268 47#include <linux/usb/r8a66597.h>
b5e8d269 48#include <linux/pm_clock.h>
9b742024 49#include <linux/dma-mapping.h>
8eda2f21 50
1a0b1eac
GL		 51#include <media/sh_mobile_ceu.h>
52#include <media/sh_mobile_csi2.h>
53#include <media/soc_camera.h>
54
cb9215e1 55#include <sound/sh_fsi.h>
af8a2fe1 56#include <sound/simple_card.h>
cb9215e1 57
dfbcdf64 58#include <video/sh_mobile_hdmi.h>
8eda2f21
GL		 59#include <video/sh_mobile_lcdc.h>
60#include <video/sh_mipi_dsi.h>
61
2b7eda63 62#include <mach/common.h>
8eda2f21 63#include <mach/irqs.h>
1b7e0677 64#include <mach/sh7372.h>
8eda2f21 65
2b7eda63
MD		 66#include <asm/mach-types.h>
67#include <asm/mach/arch.h>
3d09fbcd 68#include <asm/setup.h>
2b7eda63 69
66791859
RH		 70#include "sh-gpio.h"
71
02624a17
KM		 72/*
73 * Address Interface BusWidth note
74 * ------------------------------------------------------------------
75 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON
76 * 0x0800_0000 user area -
77 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF
78 * 0x1400_0000 Ether (LAN9220) 16bit
79 * 0x1600_0000 user area - cannot use with NAND
80 * 0x1800_0000 user area -
81 * 0x1A00_0000 -
82 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit
83 */
84
85/*
86 * NOR Flash ROM
87 *
88 * SW1 | SW2 | SW7 | NOR Flash ROM
89 * bit1 | bit1 bit2 | bit1 | Memory allocation
90 * ------+------------+------+------------------
91 * OFF | ON OFF | ON | Area 0
92 * OFF | ON OFF | OFF | Area 4
93 */
94
95/*
96 * NAND Flash ROM
97 *
98 * SW1 | SW2 | SW7 | NAND Flash ROM
99 * bit1 | bit1 bit2 | bit2 | Memory allocation
100 * ------+------------+------+------------------
101 * OFF | ON OFF | ON | FCE 0
102 * OFF | ON OFF | OFF | FCE 1
103 */
104
105/*
106 * SMSC 9220
107 *
108 * SW1 SMSC 9220
109 * -----------------------
110 * ON access disable
111 * OFF access enable
112 */
113
17ccb834 114/*
dda128dc 115 * LCD / IRQ / KEYSC / IrDA
17ccb834 116 *
9fa1b7fe
KM		 117 * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen)
118 * LCD = 2nd LCDC (WVGA)
dda128dc
KM		 119 *
120 * | SW43 |
121 * SW3 | ON | OFF |
122 * -------------+-----------------------+---------------+
123 * ON | KEY / IrDA | LCD |
124 * OFF | KEY / IrDA / IRQ | IRQ |
9fa1b7fe
KM		 125 *
126 *
127 * QHD / WVGA display
128 *
129 * You can choice display type on menuconfig.
130 * Then, check above dip-switch.
17ccb834
KM		 131 */
132
fb54d268
KM		 133/*
134 * USB
135 *
136 * J7 : 1-2 MAX3355E VBUS
137 * 2-3 DC 5.0V
138 *
139 * S39: bit2: off
140 */
141
cb9215e1
KM		 142/*
143 * FSI/FSMI
144 *
145 * SW41 : ON : SH-Mobile AP4 Audio Mode
146 * : OFF : Bluetooth Audio Mode
d2b0812d
KM		 147 *
148 * it needs amixer settings for playing
149 *
150 * amixer set "Headphone Enable" on
cb9215e1
KM		 151 */
152
c8ee3d4b 153/*
d3d03e48 154 * MMC0/SDHI1 (CN7)
c8ee3d4b 155 *
d3d03e48
KM		 156 * J22 : select card voltage
157 * 1-2 pin : 1.8v
158 * 2-3 pin : 3.3v
159 *
160 * SW1 | SW33
161 * | bit1 | bit2 | bit3 | bit4
162 * ------------+------+------+------+-------
163 * MMC0 OFF | OFF | ON | ON | X
164 * SDHI1 OFF | ON | X | OFF | ON
165 *
166 * voltage lebel
167 * CN7 : 1.8v
168 * CN12: 3.3v
c8ee3d4b
KM		 169 */
170
8778b8f4
GL		 171/* Dummy supplies, where voltage doesn't matter */
172static struct regulator_consumer_supply fixed1v8_power_consumers[] =
173{
174 /* J22 default position: 1.8V */
175 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
176 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
177 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
178 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
179};
180
181static struct regulator_consumer_supply fixed3v3_power_consumers[] =
182{
183 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
184 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
185};
186
187static struct regulator_consumer_supply dummy_supplies[] = {
188 REGULATOR_SUPPLY("vddvario", "smsc911x"),
189 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
190};
191
1b7e0677 192/* MTD */
2b7eda63
MD		 193static struct mtd_partition nor_flash_partitions[] = {
194 {
195 .name = "loader",
196 .offset = 0x00000000,
197 .size = 512 * 1024,
2e351ec6 198 .mask_flags = MTD_WRITEABLE,
2b7eda63
MD		 199 },
200 {
201 .name = "bootenv",
202 .offset = MTDPART_OFS_APPEND,
203 .size = 512 * 1024,
2e351ec6 204 .mask_flags = MTD_WRITEABLE,
2b7eda63
MD		 205 },
206 {
207 .name = "kernel_ro",
208 .offset = MTDPART_OFS_APPEND,
209 .size = 8 * 1024 * 1024,
210 .mask_flags = MTD_WRITEABLE,
211 },
212 {
213 .name = "kernel",
214 .offset = MTDPART_OFS_APPEND,
215 .size = 8 * 1024 * 1024,
216 },
217 {
218 .name = "data",
219 .offset = MTDPART_OFS_APPEND,
220 .size = MTDPART_SIZ_FULL,
221 },
222};
223
224static struct physmap_flash_data nor_flash_data = {
225 .width = 2,
226 .parts = nor_flash_partitions,
227 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
228};
229
230static struct resource nor_flash_resources[] = {
231 [0] = {
832217da 232 .start = 0x20000000, /* CS0 shadow instead of regular CS0 */
8e6a4675 233 .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
2b7eda63
MD		 234 .flags = IORESOURCE_MEM,
235 }
236};
237
238static struct platform_device nor_flash_device = {
239 .name = "physmap-flash",
240 .dev = {
241 .platform_data = &nor_flash_data,
242 },
243 .num_resources = ARRAY_SIZE(nor_flash_resources),
244 .resource = nor_flash_resources,
245};
246
1b7e0677
KM		 247/* SMSC 9220 */
248static struct resource smc911x_resources[] = {
249 {
250 .start = 0x14000000,
251 .end = 0x16000000 - 1,
252 .flags = IORESOURCE_MEM,
253 }, {
33c9607a 254 .start = evt2irq(0x02c0) /* IRQ6A */,
1b7e0677
KM		 255 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
256 },
257};
258
259static struct smsc911x_platform_config smsc911x_info = {
260 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
261 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
262 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
263};
264
265static struct platform_device smc911x_device = {
266 .name = "smsc911x",
267 .id = -1,
268 .num_resources = ARRAY_SIZE(smc911x_resources),
269 .resource = smc911x_resources,
270 .dev = {
271 .platform_data = &smsc911x_info,
272 },
273};
2b7eda63 274
68accd73
AH		 275/*
276 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
be2edfcc 277 * connected to GPIO A22 of SH7372 (GPIO 41).
68accd73
AH		 278 */
279static int slot_cn7_get_cd(struct platform_device *pdev)
280{
be2edfcc 281 return !gpio_get_value(41);
68accd73 282}
1c7fcbed
D		 283/* MERAM */
284static struct sh_mobile_meram_info meram_info = {
285 .addr_mode = SH_MOBILE_MERAM_MODE1,
286};
287
288static struct resource meram_resources[] = {
289 [0] = {
e71504d5
LP		 290 .name = "regs",
291 .start = 0xe8000000,
292 .end = 0xe807ffff,
293 .flags = IORESOURCE_MEM,
294 },
295 [1] = {
296 .name = "meram",
297 .start = 0xe8080000,
298 .end = 0xe81fffff,
299 .flags = IORESOURCE_MEM,
1c7fcbed
D		 300 },
301};
302
303static struct platform_device meram_device = {
304 .name = "sh_mobile_meram",
305 .id = 0,
306 .num_resources = ARRAY_SIZE(meram_resources),
307 .resource = meram_resources,
308 .dev = {
309 .platform_data = &meram_info,
310 },
311};
68accd73 312
c8ee3d4b
KM		 313/* SH_MMCIF */
314static struct resource sh_mmcif_resources[] = {
315 [0] = {
0fb0834b 316 .name = "MMCIF",
c8ee3d4b
KM		 317 .start = 0xE6BD0000,
318 .end = 0xE6BD00FF,
319 .flags = IORESOURCE_MEM,
320 },
321 [1] = {
322 /* MMC ERR */
8d569341 323 .start = evt2irq(0x1ac0),
c8ee3d4b
KM		 324 .flags = IORESOURCE_IRQ,
325 },
326 [2] = {
327 /* MMC NOR */
8d569341 328 .start = evt2irq(0x1ae0),
c8ee3d4b
KM		 329 .flags = IORESOURCE_IRQ,
330 },
331};
332
bb04e197 333static struct sh_mmcif_plat_data sh_mmcif_plat = {
c8ee3d4b
KM		 334 .sup_pclk = 0,
335 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
336 .caps = MMC_CAP_4_BIT_DATA |
337 MMC_CAP_8_BIT_DATA |
338 MMC_CAP_NEEDS_POLL,
68accd73 339 .get_cd = slot_cn7_get_cd,
d5bb386d
GL		 340 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
341 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
c8ee3d4b
KM		 342};
343
344static struct platform_device sh_mmcif_device = {
345 .name = "sh_mmcif",
346 .id = 0,
347 .dev = {
348 .dma_mask = NULL,
349 .coherent_dma_mask = 0xffffffff,
350 .platform_data = &sh_mmcif_plat,
351 },
352 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
353 .resource = sh_mmcif_resources,
354};
355
3a14d039 356/* SDHI0 */
69bf6f45 357static struct sh_mobile_sdhi_info sdhi0_info = {
341291a6
GL		 358 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
359 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
330e4e71 360 .tmio_caps = MMC_CAP_SDIO_IRQ,
69bf6f45
GL		 361};
362
3a14d039
MD		 363static struct resource sdhi0_resources[] = {
364 [0] = {
365 .name = "SDHI0",
366 .start = 0xe6850000,
31d31fe7 367 .end = 0xe68500ff,
3a14d039
MD		 368 .flags = IORESOURCE_MEM,
369 },
370 [1] = {
2007aea1
SH		 371 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
372 .flags = IORESOURCE_IRQ,
373 },
374 [2] = {
375 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
376 .flags = IORESOURCE_IRQ,
377 },
378 [3] = {
379 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
380 .flags = IORESOURCE_IRQ,
3a14d039
MD		 381 },
382};
383
384static struct platform_device sdhi0_device = {
385 .name = "sh_mobile_sdhi",
386 .num_resources = ARRAY_SIZE(sdhi0_resources),
387 .resource = sdhi0_resources,
388 .id = 0,
69bf6f45
GL		 389 .dev = {
390 .platform_data = &sdhi0_info,
391 },
3a14d039
MD		 392};
393
341291a6
GL		 394/* SDHI1 */
395static struct sh_mobile_sdhi_info sdhi1_info = {
396 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
397 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
398 .tmio_ocr_mask = MMC_VDD_165_195,
410d878b 399 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
330e4e71 400 .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
68accd73 401 .get_cd = slot_cn7_get_cd,
341291a6
GL		 402};
403
404static struct resource sdhi1_resources[] = {
405 [0] = {
406 .name = "SDHI1",
407 .start = 0xe6860000,
31d31fe7 408 .end = 0xe68600ff,
341291a6
GL		 409 .flags = IORESOURCE_MEM,
410 },
411 [1] = {
2007aea1
SH		 412 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
413 .flags = IORESOURCE_IRQ,
414 },
415 [2] = {
416 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
417 .flags = IORESOURCE_IRQ,
418 },
419 [3] = {
420 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
421 .flags = IORESOURCE_IRQ,
341291a6
GL		 422 },
423};
424
425static struct platform_device sdhi1_device = {
426 .name = "sh_mobile_sdhi",
427 .num_resources = ARRAY_SIZE(sdhi1_resources),
428 .resource = sdhi1_resources,
429 .id = 1,
430 .dev = {
431 .platform_data = &sdhi1_info,
432 },
433};
434
fb54d268 435/* USB1 */
bb04e197 436static void usb1_host_port_power(int port, int power)
fb54d268
KM		 437{
438 if (!power) /* only power-on supported for now */
439 return;
440
441 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
0a4b04dc 442 __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008));
fb54d268
KM		 443}
444
445static struct r8a66597_platdata usb1_host_data = {
446 .on_chip = 1,
447 .port_power = usb1_host_port_power,
448};
449
450static struct resource usb1_host_resources[] = {
451 [0] = {
452 .name = "USBHS",
453 .start = 0xE68B0000,
454 .end = 0xE68B00E6 - 1,
455 .flags = IORESOURCE_MEM,
456 },
457 [1] = {
33c9607a 458 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
fb54d268
KM		 459 .flags = IORESOURCE_IRQ,
460 },
461};
462
463static struct platform_device usb1_host_device = {
464 .name = "r8a66597_hcd",
465 .id = 1,
466 .dev = {
467 .dma_mask = NULL, /* not use dma */
468 .coherent_dma_mask = 0xffffffff,
469 .platform_data = &usb1_host_data,
470 },
471 .num_resources = ARRAY_SIZE(usb1_host_resources),
472 .resource = usb1_host_resources,
473};
474
9fa1b7fe
KM		 475/*
476 * QHD display
477 */
478#ifdef CONFIG_AP4EVB_QHD
479
480/* KEYSC (Needs SW43 set to ON) */
481static struct sh_keysc_info keysc_info = {
482 .mode = SH_KEYSC_MODE_1,
483 .scan_timing = 3,
484 .delay = 2500,
485 .keycodes = {
486 KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
487 KEY_5, KEY_6, KEY_7, KEY_8, KEY_9,
488 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
489 KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
490 KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
491 },
492};
493
494static struct resource keysc_resources[] = {
495 [0] = {
496 .name = "KEYSC",
497 .start = 0xe61b0000,
498 .end = 0xe61b0063,
499 .flags = IORESOURCE_MEM,
500 },
501 [1] = {
502 .start = evt2irq(0x0be0), /* KEYSC_KEY */
503 .flags = IORESOURCE_IRQ,
504 },
505};
506
507static struct platform_device keysc_device = {
508 .name = "sh_keysc",
509 .id = 0, /* "keysc0" clock */
510 .num_resources = ARRAY_SIZE(keysc_resources),
511 .resource = keysc_resources,
512 .dev = {
513 .platform_data = &keysc_info,
514 },
515};
516
517/* MIPI-DSI */
5e47431a
KM		 518static int sh_mipi_set_dot_clock(struct platform_device *pdev,
519 void __iomem *base,
520 int enable)
521{
522 struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
5e47431a
KM		 523
524 if (IS_ERR(pck))
525 return PTR_ERR(pck);
526
527 if (enable) {
8f9c60f2
KM		 528 /*
529 * DSIPCLK = 24MHz
530 * D-PHY = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl)
531 * HsByteCLK = D-PHY/8 = 39MHz
532 *
533 * X * Y * FPS =
534 * (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz
535 */
5e47431a 536 clk_set_rate(pck, clk_round_rate(pck, 24000000));
5e47431a
KM		 537 clk_enable(pck);
538 } else {
539 clk_disable(pck);
540 }
541
542 clk_put(pck);
543
544 return 0;
545}
546
8eda2f21
GL		 547static struct resource mipidsi0_resources[] = {
548 [0] = {
549 .start = 0xffc60000,
5958d58a
MD		 550 .end = 0xffc63073,
551 .flags = IORESOURCE_MEM,
552 },
553 [1] = {
554 .start = 0xffc68000,
555 .end = 0xffc680ef,
8eda2f21
GL		 556 .flags = IORESOURCE_MEM,
557 },
558};
559
560static struct sh_mipi_dsi_info mipidsi0_info = {
561 .data_format = MIPI_RGB888,
772f5d1b 562 .channel = LCDC_CHAN_MAINLCD,
26c3d7ac 563 .lane = 2,
6fd46595 564 .vsynw_offset = 17,
8f9c60f2 565 .phyctrl = 0x6 << 8,
a2e62971
KM		 566 .flags = SH_MIPI_DSI_SYNC_PULSES_MODE |
567 SH_MIPI_DSI_HSbyteCLK,
5e47431a 568 .set_dot_clock = sh_mipi_set_dot_clock,
8eda2f21
GL		 569};
570
571static struct platform_device mipidsi0_device = {
572 .name = "sh-mipi-dsi",
573 .num_resources = ARRAY_SIZE(mipidsi0_resources),
574 .resource = mipidsi0_resources,
575 .id = 0,
576 .dev = {
577 .platform_data = &mipidsi0_info,
578 },
579};
580
9fa1b7fe
KM		 581static struct platform_device *qhd_devices[] __initdata = {
582 &mipidsi0_device,
583 &keysc_device,
584};
585#endif /* CONFIG_AP4EVB_QHD */
586
a1022adb
LP		 587/* LCDC0 */
588static const struct fb_videomode ap4evb_lcdc_modes[] = {
589 {
590#ifdef CONFIG_AP4EVB_QHD
591 .name = "R63302(QHD)",
592 .xres = 544,
593 .yres = 961,
594 .left_margin = 72,
595 .right_margin = 600,
596 .hsync_len = 16,
597 .upper_margin = 8,
598 .lower_margin = 8,
599 .vsync_len = 2,
600 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
601#else
602 .name = "WVGA Panel",
603 .xres = 800,
604 .yres = 480,
605 .left_margin = 220,
606 .right_margin = 110,
607 .hsync_len = 70,
608 .upper_margin = 20,
609 .lower_margin = 5,
610 .vsync_len = 5,
611 .sync = 0,
612#endif
613 },
614};
c241a0e0
LP		 615
616static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
a1022adb 617 .icb[0] = {
a1022adb
LP		 618 .meram_size = 0x40,
619 },
620 .icb[1] = {
a1022adb
LP		 621 .meram_size = 0x40,
622 },
623};
624
625static struct sh_mobile_lcdc_info lcdc_info = {
626 .meram_dev = &meram_info,
627 .ch[0] = {
628 .chan = LCDC_CHAN_MAINLCD,
629 .fourcc = V4L2_PIX_FMT_RGB565,
93ff2598
LP		 630 .lcd_modes = ap4evb_lcdc_modes,
631 .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes),
a1022adb
LP		 632 .meram_cfg = &lcd_meram_cfg,
633#ifdef CONFIG_AP4EVB_QHD
634 .tx_dev = &mipidsi0_device,
635#endif
636 }
637};
638
639static struct resource lcdc_resources[] = {
640 [0] = {
641 .name = "LCDC",
642 .start = 0xfe940000, /* P4-only space */
643 .end = 0xfe943fff,
644 .flags = IORESOURCE_MEM,
645 },
646 [1] = {
647 .start = intcs_evt2irq(0x580),
648 .flags = IORESOURCE_IRQ,
649 },
650};
651
652static struct platform_device lcdc_device = {
653 .name = "sh_mobile_lcdc_fb",
654 .num_resources = ARRAY_SIZE(lcdc_resources),
655 .resource = lcdc_resources,
656 .dev = {
657 .platform_data = &lcdc_info,
658 .coherent_dma_mask = ~0,
659 },
660};
661
cb9215e1
KM		 662/* FSI */
663#define IRQ_FSI evt2irq(0x1840)
bb04e197 664static struct sh_fsi_platform_info fsi_info = {
fec691e7 665 .port_b = {
abca7581 666 .flags = SH_FSI_CLK_CPG |
fec691e7 667 SH_FSI_FMT_SPDIF,
fec691e7 668 },
cb9215e1
KM		 669};
670
671static struct resource fsi_resources[] = {
672 [0] = {
673 .name = "FSI",
674 .start = 0xFE3C0000,
675 .end = 0xFE3C0400 - 1,
676 .flags = IORESOURCE_MEM,
677 },
678 [1] = {
679 .start = IRQ_FSI,
680 .flags = IORESOURCE_IRQ,
681 },
682};
683
684static struct platform_device fsi_device = {
685 .name = "sh_fsi2",
9f6f11b6 686 .id = -1,
cb9215e1
KM		 687 .num_resources = ARRAY_SIZE(fsi_resources),
688 .resource = fsi_resources,
689 .dev = {
690 .platform_data = &fsi_info,
691 },
692};
693
af8a2fe1 694static struct asoc_simple_card_info fsi2_ak4643_info = {
45f31216
KM		 695 .name = "AK4643",
696 .card = "FSI2A-AK4643",
45f31216
KM		 697 .codec = "ak4642-codec.0-0013",
698 .platform = "sh_fsi2",
a4a2992c
KM		 699 .daifmt = SND_SOC_DAIFMT_LEFT_J,
700 .cpu_dai = {
701 .name = "fsia-dai",
702 .fmt = SND_SOC_DAIFMT_CBS_CFS,
703 },
704 .codec_dai = {
705 .name = "ak4642-hifi",
706 .fmt = SND_SOC_DAIFMT_CBM_CFM,
707 .sysclk = 11289600,
708 },
45f31216
KM		 709};
710
c8d6bf9a 711static struct platform_device fsi_ak4643_device = {
af8a2fe1 712 .name = "asoc-simple-card",
45f31216 713 .dev = {
e49d603c 714 .platform_data = &fsi2_ak4643_info,
45f31216 715 },
c8d6bf9a 716};
45f31216 717
a1022adb 718/* LCDC1 */
640dcfa0
GL		 719static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
720 unsigned long *parent_freq);
721
dfbcdf64 722static struct sh_mobile_hdmi_info hdmi_info = {
2669efec 723 .flags = HDMI_SND_SRC_SPDIF,
640dcfa0 724 .clk_optimize_parent = ap4evb_clk_optimize,
dfbcdf64
GL		 725};
726
727static struct resource hdmi_resources[] = {
728 [0] = {
729 .name = "HDMI",
730 .start = 0xe6be0000,
731 .end = 0xe6be00ff,
732 .flags = IORESOURCE_MEM,
733 },
734 [1] = {
735 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
736 .start = evt2irq(0x17e0),
737 .flags = IORESOURCE_IRQ,
738 },
739};
740
741static struct platform_device hdmi_device = {
742 .name = "sh-mobile-hdmi",
743 .num_resources = ARRAY_SIZE(hdmi_resources),
744 .resource = hdmi_resources,
745 .id = -1,
746 .dev = {
747 .platform_data = &hdmi_info,
748 },
749};
750
640dcfa0
GL		 751static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
752 unsigned long *parent_freq)
753{
754 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
755 long error;
756
757 if (IS_ERR(hdmi_ick)) {
758 int ret = PTR_ERR(hdmi_ick);
759 pr_err("Cannot get HDMI ICK: %d\n", ret);
760 return ret;
761 }
762
763 error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
764
765 clk_put(hdmi_ick);
766
767 return error;
768}
769
c241a0e0 770static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
1c7fcbed 771 .icb[0] = {
1c7fcbed
D		 772 .meram_size = 0x100,
773 },
774 .icb[1] = {
1c7fcbed
D		 775 .meram_size = 0x100,
776 },
777};
c8d6bf9a 778
dfbcdf64
GL		 779static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
780 .clock_source = LCDC_CLK_EXTERNAL,
1c7fcbed 781 .meram_dev = &meram_info,
dfbcdf64
GL		 782 .ch[0] = {
783 .chan = LCDC_CHAN_MAINLCD,
edd153a3 784 .fourcc = V4L2_PIX_FMT_RGB565,
dfbcdf64
GL		 785 .interface_type = RGB24,
786 .clock_divider = 1,
787 .flags = LCDC_FLAGS_DWPOL,
1c7fcbed 788 .meram_cfg = &hdmi_meram_cfg,
a1022adb 789 .tx_dev = &hdmi_device,
dfbcdf64
GL		 790 }
791};
792
793static struct resource lcdc1_resources[] = {
794 [0] = {
795 .name = "LCDC1",
796 .start = 0xfe944000,
797 .end = 0xfe947fff,
798 .flags = IORESOURCE_MEM,
799 },
800 [1] = {
88c759a2 801 .start = intcs_evt2irq(0x1780),
dfbcdf64
GL		 802 .flags = IORESOURCE_IRQ,
803 },
804};
805
806static struct platform_device lcdc1_device = {
807 .name = "sh_mobile_lcdc_fb",
808 .num_resources = ARRAY_SIZE(lcdc1_resources),
809 .resource = lcdc1_resources,
810 .id = 1,
811 .dev = {
812 .platform_data = &sh_mobile_lcdc1_info,
813 .coherent_dma_mask = ~0,
814 },
815};
816
fa063b48
KM		 817static struct asoc_simple_card_info fsi2_hdmi_info = {
818 .name = "HDMI",
819 .card = "FSI2B-HDMI",
fa063b48
KM		 820 .codec = "sh-mobile-hdmi",
821 .platform = "sh_fsi2",
a4a2992c
KM		 822 .cpu_dai = {
823 .name = "fsib-dai",
824 .fmt = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF,
825 },
826 .codec_dai = {
827 .name = "sh_mobile_hdmi-hifi",
828 },
fa063b48
KM		 829};
830
3f25c9cc 831static struct platform_device fsi_hdmi_device = {
fa063b48
KM		 832 .name = "asoc-simple-card",
833 .id = 1,
834 .dev = {
835 .platform_data = &fsi2_hdmi_info,
836 },
3f25c9cc
KM		 837};
838
2863e935
AH		 839static struct gpio_led ap4evb_leds[] = {
840 {
841 .name = "led4",
be2edfcc 842 .gpio = 185,
2863e935
AH		 843 .default_state = LEDS_GPIO_DEFSTATE_ON,
844 },
845 {
846 .name = "led2",
be2edfcc 847 .gpio = 186,
2863e935
AH		 848 .default_state = LEDS_GPIO_DEFSTATE_ON,
849 },
850 {
851 .name = "led3",
be2edfcc 852 .gpio = 187,
2863e935
AH		 853 .default_state = LEDS_GPIO_DEFSTATE_ON,
854 },
855 {
856 .name = "led1",
be2edfcc 857 .gpio = 188,
2863e935
AH		 858 .default_state = LEDS_GPIO_DEFSTATE_ON,
859 }
860};
861
862static struct gpio_led_platform_data ap4evb_leds_pdata = {
863 .num_leds = ARRAY_SIZE(ap4evb_leds),
8050fbf2 864 .leds = ap4evb_leds,
2863e935
AH		 865};
866
867static struct platform_device leds_device = {
868 .name = "leds-gpio",
869 .id = 0,
870 .dev = {
871 .platform_data = &ap4evb_leds_pdata,
872 },
873};
874
1a0b1eac
GL		 875static struct i2c_board_info imx074_info = {
876 I2C_BOARD_INFO("imx074", 0x1a),
877};
878
4d4d6fbb 879static struct soc_camera_link imx074_link = {
1a0b1eac
GL		 880 .bus_id = 0,
881 .board_info = &imx074_info,
882 .i2c_adapter_id = 0,
883 .module_name = "imx074",
884};
885
886static struct platform_device ap4evb_camera = {
887 .name = "soc-camera-pdrv",
888 .id = 0,
889 .dev = {
890 .platform_data = &imx074_link,
891 },
892};
893
894static struct sh_csi2_client_config csi2_clients[] = {
895 {
896 .phy = SH_CSI2_PHY_MAIN,
19a1780b 897 .lanes = 0, /* default: 2 lanes */
1a0b1eac
GL		 898 .channel = 0,
899 .pdev = &ap4evb_camera,
900 },
901};
902
903static struct sh_csi2_pdata csi2_info = {
904 .type = SH_CSI2C,
905 .clients = csi2_clients,
906 .num_clients = ARRAY_SIZE(csi2_clients),
907 .flags = SH_CSI2_ECC | SH_CSI2_CRC,
908};
909
910static struct resource csi2_resources[] = {
911 [0] = {
912 .name = "CSI2",
913 .start = 0xffc90000,
914 .end = 0xffc90fff,
915 .flags = IORESOURCE_MEM,
916 },
917 [1] = {
918 .start = intcs_evt2irq(0x17a0),
919 .flags = IORESOURCE_IRQ,
920 },
921};
922
6b526fed
GL		 923static struct sh_mobile_ceu_companion csi2 = {
924 .id = 0,
1a0b1eac
GL		 925 .num_resources = ARRAY_SIZE(csi2_resources),
926 .resource = csi2_resources,
6b526fed 927 .platform_data = &csi2_info,
1a0b1eac
GL		 928};
929
930static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
931 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
ef8f41ff
GL		 932 .max_width = 8188,
933 .max_height = 8188,
6b526fed 934 .csi2 = &csi2,
1a0b1eac
GL		 935};
936
937static struct resource ceu_resources[] = {
938 [0] = {
939 .name = "CEU",
940 .start = 0xfe910000,
941 .end = 0xfe91009f,
942 .flags = IORESOURCE_MEM,
943 },
944 [1] = {
945 .start = intcs_evt2irq(0x880),
946 .flags = IORESOURCE_IRQ,
947 },
948 [2] = {
949 /* place holder for contiguous memory */
950 },
951};
952
953static struct platform_device ceu_device = {
954 .name = "sh_mobile_ceu",
955 .id = 0, /* "ceu0" clock */
956 .num_resources = ARRAY_SIZE(ceu_resources),
957 .resource = ceu_resources,
958 .dev = {
05a5f01c
GL		 959 .platform_data = &sh_mobile_ceu_info,
960 .coherent_dma_mask = 0xffffffff,
1a0b1eac
GL		 961 },
962};
963
2b7eda63 964static struct platform_device *ap4evb_devices[] __initdata = {
2863e935 965 &leds_device,
2b7eda63 966 &nor_flash_device,
1b7e0677 967 &smc911x_device,
3a14d039 968 &sdhi0_device,
341291a6 969 &sdhi1_device,
fb54d268 970 &usb1_host_device,
cb9215e1 971 &fsi_device,
c8d6bf9a 972 &fsi_ak4643_device,
3f25c9cc 973 &fsi_hdmi_device,
beccb12f 974 &sh_mmcif_device,
dfbcdf64 975 &hdmi_device,
a1022adb
LP		 976 &lcdc_device,
977 &lcdc1_device,
1a0b1eac
GL		 978 &ceu_device,
979 &ap4evb_camera,
1c7fcbed 980 &meram_device,
2b7eda63
MD		 981};
982
2ce51f8b 983static void __init hdmi_init_pm_clock(void)
dfbcdf64
GL		 984{
985 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
986 int ret;
987 long rate;
988
989 if (IS_ERR(hdmi_ick)) {
990 ret = PTR_ERR(hdmi_ick);
991 pr_err("Cannot get HDMI ICK: %d\n", ret);
992 goto out;
993 }
994
685e4080 995 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
dfbcdf64 996 if (ret < 0) {
685e4080 997 pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
dfbcdf64
GL		 998 goto out;
999 }
1000
685e4080 1001 pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
dfbcdf64 1002
685e4080 1003 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
dfbcdf64
GL		 1004 if (rate < 0) {
1005 pr_err("Cannot get suitable rate: %ld\n", rate);
1006 ret = rate;
1007 goto out;
1008 }
1009
685e4080 1010 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
dfbcdf64
GL		 1011 if (ret < 0) {
1012 pr_err("Cannot set rate %ld: %d\n", rate, ret);
1013 goto out;
1014 }
1015
1016 pr_debug("PLLC2 set frequency %lu\n", rate);
1017
685e4080 1018 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
2ce51f8b 1019 if (ret < 0)
dfbcdf64 1020 pr_err("Cannot set HDMI parent: %d\n", ret);
dfbcdf64
GL		 1021
1022out:
1023 if (!IS_ERR(hdmi_ick))
1024 clk_put(hdmi_ick);
dfbcdf64
GL		 1025}
1026
9fa1b7fe 1027/* TouchScreen */
52d5ac00
KM		 1028#ifdef CONFIG_AP4EVB_QHD
1029# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
be2edfcc 1030# define GPIO_TSC_PORT 123
52d5ac00
KM		 1031#else /* WVGA */
1032# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
be2edfcc 1033# define GPIO_TSC_PORT 40
52d5ac00
KM		 1034#endif
1035
33c9607a 1036#define IRQ28 evt2irq(0x3380) /* IRQ28A */
9fa1b7fe 1037#define IRQ7 evt2irq(0x02e0) /* IRQ7A */
71c3ba9a
KM		 1038static int ts_get_pendown_state(void)
1039{
4a666a78 1040 return !gpio_get_value(GPIO_TSC_PORT);
71c3ba9a
KM		 1041}
1042
71c3ba9a
KM		 1043static int ts_init(void)
1044{
52d5ac00 1045 gpio_request(GPIO_TSC_IRQ, NULL);
4a666a78 1046 gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
71c3ba9a
KM		 1047
1048 return 0;
1049}
1050
bb04e197 1051static struct tsc2007_platform_data tsc2007_info = {
91cf5082
KM		 1052 .model = 2007,
1053 .x_plate_ohms = 180,
71c3ba9a
KM		 1054 .get_pendown_state = ts_get_pendown_state,
1055 .init_platform_hw = ts_init,
91cf5082
KM		 1056};
1057
9fa1b7fe
KM		 1058static struct i2c_board_info tsc_device = {
1059 I2C_BOARD_INFO("tsc2007", 0x48),
1060 .type = "tsc2007",
1061 .platform_data = &tsc2007_info,
1062 /*.irq is selected on ap4evb_init */
1063};
1064
91cf5082 1065/* I2C */
cb9215e1
KM		 1066static struct i2c_board_info i2c0_devices[] = {
1067 {
1068 I2C_BOARD_INFO("ak4643", 0x13),
1069 },
1070};
1071
91cf5082 1072static struct i2c_board_info i2c1_devices[] = {
8fc883c2
KM		 1073 {
1074 I2C_BOARD_INFO("r2025sd", 0x32),
1075 },
91cf5082
KM		 1076};
1077
2b7eda63 1078
e6bd960e 1079static const struct pinctrl_map ap4evb_pinctrl_map[] = {
bdf439f1
LP		 1080 /* CEU */
1081 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
1082 "ceu_clk_0", "ceu"),
d2e0ca63
LP		 1083 /* FSIA (AK4643) */
1084 PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
1085 "fsia_sclk_in", "fsia"),
1086 PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
1087 "fsia_data_in", "fsia"),
1088 PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
1089 "fsia_data_out", "fsia"),
1090 /* FSIB (HDMI) */
1091 PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
1092 "fsib_mclk_in", "fsib"),
d9aa3005
LP		 1093 /* HDMI */
1094 PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
1095 "hdmi", "hdmi"),
6cd49f71
LP		 1096 /* KEYSC */
1097 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
1098 "keysc_in04_0", "keysc"),
1099 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
1100 "keysc_out5", "keysc"),
8b53e595
LP		 1101#ifndef CONFIG_AP4EVB_QHD
1102 /* LCDC */
1103 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
1104 "lcd_data18", "lcd"),
1105 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
1106 "lcd_sync", "lcd"),
1107#endif
e6bd960e
LP		 1108 /* MMCIF */
1109 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1110 "mmc0_data8_0", "mmc0"),
1111 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1112 "mmc0_ctrl_0", "mmc0"),
09f2780d
LP		 1113 /* SCIFA0 */
1114 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
1115 "scifa0_data", "scifa0"),
e6bd960e
LP		 1116 /* SDHI0 */
1117 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1118 "sdhi0_data4", "sdhi0"),
1119 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1120 "sdhi0_ctrl", "sdhi0"),
1121 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1122 "sdhi0_cd", "sdhi0"),
1123 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1124 "sdhi0_wp", "sdhi0"),
1125 /* SDHI1 */
1126 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1127 "sdhi1_data4", "sdhi1"),
1128 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1129 "sdhi1_ctrl", "sdhi1"),
5436c2b9
LP		 1130 /* SMSC911X */
1131 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
1132 "bsc_cs5a", "bsc"),
1133 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
1134 "intc_irq6_0", "intc"),
e6bd960e
LP		 1135};
1136
0a4b04dc
AB		 1137#define GPIO_PORT9CR IOMEM(0xE6051009)
1138#define GPIO_PORT10CR IOMEM(0xE605100A)
1139#define USCCR1 IOMEM(0xE6058144)
2b7eda63
MD		 1140static void __init ap4evb_init(void)
1141{
201dbd81
RW		 1142 struct pm_domain_device domain_devices[] = {
1143 { "A4LC", &lcdc1_device, },
1144 { "A4LC", &lcdc_device, },
1145 { "A4MP", &fsi_device, },
1146 { "A3SP", &sh_mmcif_device, },
1147 { "A3SP", &sdhi0_device, },
1148 { "A3SP", &sdhi1_device, },
1149 { "A4R", &ceu_device, },
1150 };
dfbcdf64 1151 u32 srcr4;
cb9215e1
KM		 1152 struct clk *clk;
1153
8778b8f4
GL		 1154 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
1155 ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
1156 regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
1157 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
1158 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
1159
e3b0161b
MD		 1160 /* External clock source */
1161 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1162
e6bd960e
LP		 1163 pinctrl_register_mappings(ap4evb_pinctrl_map,
1164 ARRAY_SIZE(ap4evb_pinctrl_map));
1b7e0677
KM		 1165 sh7372_pinmux_init();
1166
8cb3a2eb 1167 /* enable Debug switch (S6) */
be2edfcc
LP		 1168 gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
1169 gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
1170 gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
1171 gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
8cb3a2eb 1172
fb54d268
KM		 1173 /* USB enable */
1174 gpio_request(GPIO_FN_VBUS0_1, NULL);
1175 gpio_request(GPIO_FN_IDIN_1_18, NULL);
1176 gpio_request(GPIO_FN_PWEN_1_115, NULL);
1177 gpio_request(GPIO_FN_OVCN_1_114, NULL);
1178 gpio_request(GPIO_FN_EXTLP_1, NULL);
1179 gpio_request(GPIO_FN_OVCN2_1, NULL);
1180
1181 /* setup USB phy */
0a4b04dc 1182 __raw_writew(0x8a0a, IOMEM(0xE6058130)); /* USBCR4 */
fb54d268 1183
d2e0ca63 1184 /* FSI2 port A (ak4643) */
be2edfcc 1185 gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
cb9215e1 1186
be2edfcc
LP		 1187 gpio_request(9, NULL);
1188 gpio_request(10, NULL);
6a6196af
KM		 1189 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1190 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
cb9215e1 1191
68accd73 1192 /* card detect pin for MMC slot (CN7) */
be2edfcc 1193 gpio_request_one(41, GPIOF_IN, NULL);
68accd73 1194
d2e0ca63 1195 /* FSI2 port B (HDMI) */
2669efec
KM		 1196 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
1197
cb9215e1
KM		 1198 /* set SPU2 clock to 119.6 MHz */
1199 clk = clk_get(NULL, "spu_clk");
2ae2b766 1200 if (!IS_ERR(clk)) {
cb9215e1
KM		 1201 clk_set_rate(clk, clk_round_rate(clk, 119600000));
1202 clk_put(clk);
1203 }
1204
cb9215e1
KM		 1205 /*
1206 * set irq priority, to avoid sound chopping
1207 * when NFS rootfs is used
1208 * FSI(3) > SMSC911X(2)
1209 */
1210 intc_set_priority(IRQ_FSI, 3);
1211
1212 i2c_register_board_info(0, i2c0_devices,
1213 ARRAY_SIZE(i2c0_devices));
1214
1215 i2c_register_board_info(1, i2c1_devices,
1216 ARRAY_SIZE(i2c1_devices));
1217
9fa1b7fe 1218#ifdef CONFIG_AP4EVB_QHD
dd8a61a7 1219
9fa1b7fe 1220 /*
dd8a61a7
MD		 1221 * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
1222 * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
9fa1b7fe
KM		 1223 */
1224
9fa1b7fe 1225 /* enable TouchScreen */
6845664a 1226 irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
9fa1b7fe
KM		 1227
1228 tsc_device.irq = IRQ28;
1229 i2c_register_board_info(1, &tsc_device, 1);
1230
1231 /* LCDC0 */
1232 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
1233 lcdc_info.ch[0].interface_type = RGB24;
1234 lcdc_info.ch[0].clock_divider = 1;
1235 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
afaad83b
LP		 1236 lcdc_info.ch[0].panel_cfg.width = 44;
1237 lcdc_info.ch[0].panel_cfg.height = 79;
9fa1b7fe
KM		 1238
1239 platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
1240
1241#else
1242 /*
dd8a61a7
MD		 1243 * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
1244 * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
9fa1b7fe 1245 */
be2edfcc
LP		 1246 gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
1247 gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
9fa1b7fe
KM		 1248
1249 lcdc_info.clock_source = LCDC_CLK_BUS;
1250 lcdc_info.ch[0].interface_type = RGB18;
f60cb470 1251 lcdc_info.ch[0].clock_divider = 3;
9fa1b7fe 1252 lcdc_info.ch[0].flags = 0;
afaad83b
LP		 1253 lcdc_info.ch[0].panel_cfg.width = 152;
1254 lcdc_info.ch[0].panel_cfg.height = 91;
9fa1b7fe
KM		 1255
1256 /* enable TouchScreen */
6845664a 1257 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
9fa1b7fe
KM		 1258
1259 tsc_device.irq = IRQ7;
1260 i2c_register_board_info(0, &tsc_device, 1);
1261#endif /* CONFIG_AP4EVB_QHD */
341291a6 1262
1a0b1eac
GL		 1263 /* CEU */
1264
1265 /*
1266 * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
1267 * becomes available
1268 */
1269
1270 /* MIPI-CSI stuff */
1a0b1eac
GL		 1271 clk = clk_get(NULL, "vck1_clk");
1272 if (!IS_ERR(clk)) {
1273 clk_set_rate(clk, clk_round_rate(clk, 13000000));
1274 clk_enable(clk);
1275 clk_put(clk);
1276 }
1277
2b7eda63
MD		 1278 sh7372_add_standard_devices();
1279
dfbcdf64 1280 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
0a4b04dc 1281#define SRCR4 IOMEM(0xe61580bc)
dfbcdf64
GL		 1282 srcr4 = __raw_readl(SRCR4);
1283 __raw_writel(srcr4 | (1 << 13), SRCR4);
1284 udelay(50);
1285 __raw_writel(srcr4 & ~(1 << 13), SRCR4);
1286
2b7eda63 1287 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
2ce51f8b 1288
201dbd81
RW		 1289 rmobile_add_devices_to_domains(domain_devices,
1290 ARRAY_SIZE(domain_devices));
d93f5cde 1291
2ce51f8b 1292 hdmi_init_pm_clock();
97991657 1293 sh7372_pm_init();
a41b6466 1294 pm_clk_add(&fsi_device.dev, "spu2");
d0168fdc 1295 pm_clk_add(&lcdc1_device.dev, "hdmi");
2b7eda63
MD		 1296}
1297
1298MACHINE_START(AP4EVB, "ap4evb")
5d7220ec
MD		 1299 .map_io = sh7372_map_io,
1300 .init_early = sh7372_add_early_devices,
2b7eda63 1301 .init_irq = sh7372_init_irq,
863b1719 1302 .handle_irq = shmobile_handle_irq_intc,
2b7eda63 1303 .init_machine = ap4evb_init,
caaca999 1304 .init_late = sh7372_pm_init_late,
6bb27d73 1305 .init_time = sh7372_earlytimer_init,
2b7eda63 1306MACHINE_END
Linux kernel - Deliverables
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