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ARM: shmobile: Use names of power domains for adding devices to them
[deliverable/linux.git] / arch / arm / mach-shmobile / board-ap4evb.c
CommitLineData
2b7eda63
MD		 1/*
2 * AP4EVB board support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
8eda2f21 20#include <linux/clk.h>
2b7eda63
MD		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
410d878b 27#include <linux/mfd/tmio.h>
341291a6 28#include <linux/mmc/host.h>
17e75d82 29#include <linux/mmc/sh_mobile_sdhi.h>
2b7eda63
MD		 30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h>
32#include <linux/mtd/physmap.h>
c8ee3d4b 33#include <linux/mmc/sh_mmcif.h>
91cf5082
KM		 34#include <linux/i2c.h>
35#include <linux/i2c/tsc2007.h>
2b7eda63 36#include <linux/io.h>
8778b8f4
GL		 37#include <linux/regulator/fixed.h>
38#include <linux/regulator/machine.h>
1b7e0677 39#include <linux/smsc911x.h>
cb9215e1
KM		 40#include <linux/sh_intc.h>
41#include <linux/sh_clk.h>
1b7e0677 42#include <linux/gpio.h>
17ccb834 43#include <linux/input.h>
2863e935 44#include <linux/leds.h>
17ccb834 45#include <linux/input/sh_keysc.h>
fb54d268 46#include <linux/usb/r8a66597.h>
b5e8d269 47#include <linux/pm_clock.h>
9b742024 48#include <linux/dma-mapping.h>
8eda2f21 49
1a0b1eac
GL		 50#include <media/sh_mobile_ceu.h>
51#include <media/sh_mobile_csi2.h>
52#include <media/soc_camera.h>
53
cb9215e1 54#include <sound/sh_fsi.h>
af8a2fe1 55#include <sound/simple_card.h>
cb9215e1 56
dfbcdf64 57#include <video/sh_mobile_hdmi.h>
8eda2f21
GL		 58#include <video/sh_mobile_lcdc.h>
59#include <video/sh_mipi_dsi.h>
60
2b7eda63 61#include <mach/common.h>
8eda2f21 62#include <mach/irqs.h>
1b7e0677 63#include <mach/sh7372.h>
8eda2f21 64
2b7eda63
MD		 65#include <asm/mach-types.h>
66#include <asm/mach/arch.h>
3d09fbcd 67#include <asm/setup.h>
2b7eda63 68
02624a17
KM		 69/*
70 * Address Interface BusWidth note
71 * ------------------------------------------------------------------
72 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON
73 * 0x0800_0000 user area -
74 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF
75 * 0x1400_0000 Ether (LAN9220) 16bit
76 * 0x1600_0000 user area - cannot use with NAND
77 * 0x1800_0000 user area -
78 * 0x1A00_0000 -
79 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit
80 */
81
82/*
83 * NOR Flash ROM
84 *
85 * SW1 | SW2 | SW7 | NOR Flash ROM
86 * bit1 | bit1 bit2 | bit1 | Memory allocation
87 * ------+------------+------+------------------
88 * OFF | ON OFF | ON | Area 0
89 * OFF | ON OFF | OFF | Area 4
90 */
91
92/*
93 * NAND Flash ROM
94 *
95 * SW1 | SW2 | SW7 | NAND Flash ROM
96 * bit1 | bit1 bit2 | bit2 | Memory allocation
97 * ------+------------+------+------------------
98 * OFF | ON OFF | ON | FCE 0
99 * OFF | ON OFF | OFF | FCE 1
100 */
101
102/*
103 * SMSC 9220
104 *
105 * SW1 SMSC 9220
106 * -----------------------
107 * ON access disable
108 * OFF access enable
109 */
110
17ccb834 111/*
dda128dc 112 * LCD / IRQ / KEYSC / IrDA
17ccb834 113 *
9fa1b7fe
KM		 114 * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen)
115 * LCD = 2nd LCDC (WVGA)
dda128dc
KM		 116 *
117 * | SW43 |
118 * SW3 | ON | OFF |
119 * -------------+-----------------------+---------------+
120 * ON | KEY / IrDA | LCD |
121 * OFF | KEY / IrDA / IRQ | IRQ |
9fa1b7fe
KM		 122 *
123 *
124 * QHD / WVGA display
125 *
126 * You can choice display type on menuconfig.
127 * Then, check above dip-switch.
17ccb834
KM		 128 */
129
fb54d268
KM		 130/*
131 * USB
132 *
133 * J7 : 1-2 MAX3355E VBUS
134 * 2-3 DC 5.0V
135 *
136 * S39: bit2: off
137 */
138
cb9215e1
KM		 139/*
140 * FSI/FSMI
141 *
142 * SW41 : ON : SH-Mobile AP4 Audio Mode
143 * : OFF : Bluetooth Audio Mode
144 */
145
c8ee3d4b 146/*
d3d03e48 147 * MMC0/SDHI1 (CN7)
c8ee3d4b 148 *
d3d03e48
KM		 149 * J22 : select card voltage
150 * 1-2 pin : 1.8v
151 * 2-3 pin : 3.3v
152 *
153 * SW1 | SW33
154 * | bit1 | bit2 | bit3 | bit4
155 * ------------+------+------+------+-------
156 * MMC0 OFF | OFF | ON | ON | X
157 * SDHI1 OFF | ON | X | OFF | ON
158 *
159 * voltage lebel
160 * CN7 : 1.8v
161 * CN12: 3.3v
c8ee3d4b
KM		 162 */
163
8778b8f4
GL		 164/* Dummy supplies, where voltage doesn't matter */
165static struct regulator_consumer_supply fixed1v8_power_consumers[] =
166{
167 /* J22 default position: 1.8V */
168 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
169 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
170 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
171 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
172};
173
174static struct regulator_consumer_supply fixed3v3_power_consumers[] =
175{
176 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
177 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
178};
179
180static struct regulator_consumer_supply dummy_supplies[] = {
181 REGULATOR_SUPPLY("vddvario", "smsc911x"),
182 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
183};
184
1b7e0677 185/* MTD */
2b7eda63
MD		 186static struct mtd_partition nor_flash_partitions[] = {
187 {
188 .name = "loader",
189 .offset = 0x00000000,
190 .size = 512 * 1024,
2e351ec6 191 .mask_flags = MTD_WRITEABLE,
2b7eda63
MD		 192 },
193 {
194 .name = "bootenv",
195 .offset = MTDPART_OFS_APPEND,
196 .size = 512 * 1024,
2e351ec6 197 .mask_flags = MTD_WRITEABLE,
2b7eda63
MD		 198 },
199 {
200 .name = "kernel_ro",
201 .offset = MTDPART_OFS_APPEND,
202 .size = 8 * 1024 * 1024,
203 .mask_flags = MTD_WRITEABLE,
204 },
205 {
206 .name = "kernel",
207 .offset = MTDPART_OFS_APPEND,
208 .size = 8 * 1024 * 1024,
209 },
210 {
211 .name = "data",
212 .offset = MTDPART_OFS_APPEND,
213 .size = MTDPART_SIZ_FULL,
214 },
215};
216
217static struct physmap_flash_data nor_flash_data = {
218 .width = 2,
219 .parts = nor_flash_partitions,
220 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
221};
222
223static struct resource nor_flash_resources[] = {
224 [0] = {
832217da 225 .start = 0x20000000, /* CS0 shadow instead of regular CS0 */
8e6a4675 226 .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
2b7eda63
MD		 227 .flags = IORESOURCE_MEM,
228 }
229};
230
231static struct platform_device nor_flash_device = {
232 .name = "physmap-flash",
233 .dev = {
234 .platform_data = &nor_flash_data,
235 },
236 .num_resources = ARRAY_SIZE(nor_flash_resources),
237 .resource = nor_flash_resources,
238};
239
1b7e0677
KM		 240/* SMSC 9220 */
241static struct resource smc911x_resources[] = {
242 {
243 .start = 0x14000000,
244 .end = 0x16000000 - 1,
245 .flags = IORESOURCE_MEM,
246 }, {
33c9607a 247 .start = evt2irq(0x02c0) /* IRQ6A */,
1b7e0677
KM		 248 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
249 },
250};
251
252static struct smsc911x_platform_config smsc911x_info = {
253 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
254 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
255 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
256};
257
258static struct platform_device smc911x_device = {
259 .name = "smsc911x",
260 .id = -1,
261 .num_resources = ARRAY_SIZE(smc911x_resources),
262 .resource = smc911x_resources,
263 .dev = {
264 .platform_data = &smsc911x_info,
265 },
266};
2b7eda63 267
68accd73
AH		 268/*
269 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
270 * connected to GPIO A22 of SH7372 (GPIO_PORT41).
271 */
272static int slot_cn7_get_cd(struct platform_device *pdev)
273{
ceb50f33 274 return !gpio_get_value(GPIO_PORT41);
68accd73 275}
1c7fcbed
D		 276/* MERAM */
277static struct sh_mobile_meram_info meram_info = {
278 .addr_mode = SH_MOBILE_MERAM_MODE1,
279};
280
281static struct resource meram_resources[] = {
282 [0] = {
e71504d5
LP		 283 .name = "regs",
284 .start = 0xe8000000,
285 .end = 0xe807ffff,
286 .flags = IORESOURCE_MEM,
287 },
288 [1] = {
289 .name = "meram",
290 .start = 0xe8080000,
291 .end = 0xe81fffff,
292 .flags = IORESOURCE_MEM,
1c7fcbed
D		 293 },
294};
295
296static struct platform_device meram_device = {
297 .name = "sh_mobile_meram",
298 .id = 0,
299 .num_resources = ARRAY_SIZE(meram_resources),
300 .resource = meram_resources,
301 .dev = {
302 .platform_data = &meram_info,
303 },
304};
68accd73 305
c8ee3d4b
KM		 306/* SH_MMCIF */
307static struct resource sh_mmcif_resources[] = {
308 [0] = {
0fb0834b 309 .name = "MMCIF",
c8ee3d4b
KM		 310 .start = 0xE6BD0000,
311 .end = 0xE6BD00FF,
312 .flags = IORESOURCE_MEM,
313 },
314 [1] = {
315 /* MMC ERR */
8d569341 316 .start = evt2irq(0x1ac0),
c8ee3d4b
KM		 317 .flags = IORESOURCE_IRQ,
318 },
319 [2] = {
320 /* MMC NOR */
8d569341 321 .start = evt2irq(0x1ae0),
c8ee3d4b
KM		 322 .flags = IORESOURCE_IRQ,
323 },
324};
325
bb04e197 326static struct sh_mmcif_plat_data sh_mmcif_plat = {
c8ee3d4b
KM		 327 .sup_pclk = 0,
328 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
329 .caps = MMC_CAP_4_BIT_DATA |
330 MMC_CAP_8_BIT_DATA |
331 MMC_CAP_NEEDS_POLL,
68accd73 332 .get_cd = slot_cn7_get_cd,
d5bb386d
GL		 333 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
334 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
c8ee3d4b
KM		 335};
336
337static struct platform_device sh_mmcif_device = {
338 .name = "sh_mmcif",
339 .id = 0,
340 .dev = {
341 .dma_mask = NULL,
342 .coherent_dma_mask = 0xffffffff,
343 .platform_data = &sh_mmcif_plat,
344 },
345 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
346 .resource = sh_mmcif_resources,
347};
348
3a14d039 349/* SDHI0 */
69bf6f45 350static struct sh_mobile_sdhi_info sdhi0_info = {
341291a6
GL		 351 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
352 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
330e4e71 353 .tmio_caps = MMC_CAP_SDIO_IRQ,
69bf6f45
GL		 354};
355
3a14d039
MD		 356static struct resource sdhi0_resources[] = {
357 [0] = {
358 .name = "SDHI0",
359 .start = 0xe6850000,
31d31fe7 360 .end = 0xe68500ff,
3a14d039
MD		 361 .flags = IORESOURCE_MEM,
362 },
363 [1] = {
2007aea1
SH		 364 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
365 .flags = IORESOURCE_IRQ,
366 },
367 [2] = {
368 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
369 .flags = IORESOURCE_IRQ,
370 },
371 [3] = {
372 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
373 .flags = IORESOURCE_IRQ,
3a14d039
MD		 374 },
375};
376
377static struct platform_device sdhi0_device = {
378 .name = "sh_mobile_sdhi",
379 .num_resources = ARRAY_SIZE(sdhi0_resources),
380 .resource = sdhi0_resources,
381 .id = 0,
69bf6f45
GL		 382 .dev = {
383 .platform_data = &sdhi0_info,
384 },
3a14d039
MD		 385};
386
341291a6
GL		 387/* SDHI1 */
388static struct sh_mobile_sdhi_info sdhi1_info = {
389 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
390 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
391 .tmio_ocr_mask = MMC_VDD_165_195,
410d878b 392 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
330e4e71 393 .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
68accd73 394 .get_cd = slot_cn7_get_cd,
341291a6
GL		 395};
396
397static struct resource sdhi1_resources[] = {
398 [0] = {
399 .name = "SDHI1",
400 .start = 0xe6860000,
31d31fe7 401 .end = 0xe68600ff,
341291a6
GL		 402 .flags = IORESOURCE_MEM,
403 },
404 [1] = {
2007aea1
SH		 405 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
406 .flags = IORESOURCE_IRQ,
407 },
408 [2] = {
409 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
410 .flags = IORESOURCE_IRQ,
411 },
412 [3] = {
413 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
414 .flags = IORESOURCE_IRQ,
341291a6
GL		 415 },
416};
417
418static struct platform_device sdhi1_device = {
419 .name = "sh_mobile_sdhi",
420 .num_resources = ARRAY_SIZE(sdhi1_resources),
421 .resource = sdhi1_resources,
422 .id = 1,
423 .dev = {
424 .platform_data = &sdhi1_info,
425 },
426};
427
fb54d268 428/* USB1 */
bb04e197 429static void usb1_host_port_power(int port, int power)
fb54d268
KM		 430{
431 if (!power) /* only power-on supported for now */
432 return;
433
434 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
435 __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
436}
437
438static struct r8a66597_platdata usb1_host_data = {
439 .on_chip = 1,
440 .port_power = usb1_host_port_power,
441};
442
443static struct resource usb1_host_resources[] = {
444 [0] = {
445 .name = "USBHS",
446 .start = 0xE68B0000,
447 .end = 0xE68B00E6 - 1,
448 .flags = IORESOURCE_MEM,
449 },
450 [1] = {
33c9607a 451 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
fb54d268
KM		 452 .flags = IORESOURCE_IRQ,
453 },
454};
455
456static struct platform_device usb1_host_device = {
457 .name = "r8a66597_hcd",
458 .id = 1,
459 .dev = {
460 .dma_mask = NULL, /* not use dma */
461 .coherent_dma_mask = 0xffffffff,
462 .platform_data = &usb1_host_data,
463 },
464 .num_resources = ARRAY_SIZE(usb1_host_resources),
465 .resource = usb1_host_resources,
466};
467
9fa1b7fe
KM		 468/*
469 * QHD display
470 */
471#ifdef CONFIG_AP4EVB_QHD
472
473/* KEYSC (Needs SW43 set to ON) */
474static struct sh_keysc_info keysc_info = {
475 .mode = SH_KEYSC_MODE_1,
476 .scan_timing = 3,
477 .delay = 2500,
478 .keycodes = {
479 KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
480 KEY_5, KEY_6, KEY_7, KEY_8, KEY_9,
481 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
482 KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
483 KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
484 },
485};
486
487static struct resource keysc_resources[] = {
488 [0] = {
489 .name = "KEYSC",
490 .start = 0xe61b0000,
491 .end = 0xe61b0063,
492 .flags = IORESOURCE_MEM,
493 },
494 [1] = {
495 .start = evt2irq(0x0be0), /* KEYSC_KEY */
496 .flags = IORESOURCE_IRQ,
497 },
498};
499
500static struct platform_device keysc_device = {
501 .name = "sh_keysc",
502 .id = 0, /* "keysc0" clock */
503 .num_resources = ARRAY_SIZE(keysc_resources),
504 .resource = keysc_resources,
505 .dev = {
506 .platform_data = &keysc_info,
507 },
508};
509
510/* MIPI-DSI */
5e47431a
KM		 511static int sh_mipi_set_dot_clock(struct platform_device *pdev,
512 void __iomem *base,
513 int enable)
514{
515 struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
5e47431a
KM		 516
517 if (IS_ERR(pck))
518 return PTR_ERR(pck);
519
520 if (enable) {
8f9c60f2
KM		 521 /*
522 * DSIPCLK = 24MHz
523 * D-PHY = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl)
524 * HsByteCLK = D-PHY/8 = 39MHz
525 *
526 * X * Y * FPS =
527 * (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz
528 */
5e47431a 529 clk_set_rate(pck, clk_round_rate(pck, 24000000));
5e47431a
KM		 530 clk_enable(pck);
531 } else {
532 clk_disable(pck);
533 }
534
535 clk_put(pck);
536
537 return 0;
538}
539
8eda2f21
GL		 540static struct resource mipidsi0_resources[] = {
541 [0] = {
542 .start = 0xffc60000,
5958d58a
MD		 543 .end = 0xffc63073,
544 .flags = IORESOURCE_MEM,
545 },
546 [1] = {
547 .start = 0xffc68000,
548 .end = 0xffc680ef,
8eda2f21
GL		 549 .flags = IORESOURCE_MEM,
550 },
551};
552
a1022adb
LP		 553static struct sh_mobile_lcdc_info lcdc_info;
554
8eda2f21
GL		 555static struct sh_mipi_dsi_info mipidsi0_info = {
556 .data_format = MIPI_RGB888,
9fa1b7fe 557 .lcd_chan = &lcdc_info.ch[0],
26c3d7ac 558 .lane = 2,
6fd46595 559 .vsynw_offset = 17,
8f9c60f2 560 .phyctrl = 0x6 << 8,
a2e62971
KM		 561 .flags = SH_MIPI_DSI_SYNC_PULSES_MODE |
562 SH_MIPI_DSI_HSbyteCLK,
5e47431a 563 .set_dot_clock = sh_mipi_set_dot_clock,
8eda2f21
GL		 564};
565
566static struct platform_device mipidsi0_device = {
567 .name = "sh-mipi-dsi",
568 .num_resources = ARRAY_SIZE(mipidsi0_resources),
569 .resource = mipidsi0_resources,
570 .id = 0,
571 .dev = {
572 .platform_data = &mipidsi0_info,
573 },
574};
575
9fa1b7fe
KM		 576static struct platform_device *qhd_devices[] __initdata = {
577 &mipidsi0_device,
578 &keysc_device,
579};
580#endif /* CONFIG_AP4EVB_QHD */
581
a1022adb
LP		 582/* LCDC0 */
583static const struct fb_videomode ap4evb_lcdc_modes[] = {
584 {
585#ifdef CONFIG_AP4EVB_QHD
586 .name = "R63302(QHD)",
587 .xres = 544,
588 .yres = 961,
589 .left_margin = 72,
590 .right_margin = 600,
591 .hsync_len = 16,
592 .upper_margin = 8,
593 .lower_margin = 8,
594 .vsync_len = 2,
595 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
596#else
597 .name = "WVGA Panel",
598 .xres = 800,
599 .yres = 480,
600 .left_margin = 220,
601 .right_margin = 110,
602 .hsync_len = 70,
603 .upper_margin = 20,
604 .lower_margin = 5,
605 .vsync_len = 5,
606 .sync = 0,
607#endif
608 },
609};
c241a0e0
LP		 610
611static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
a1022adb 612 .icb[0] = {
a1022adb
LP		 613 .meram_size = 0x40,
614 },
615 .icb[1] = {
a1022adb
LP		 616 .meram_size = 0x40,
617 },
618};
619
620static struct sh_mobile_lcdc_info lcdc_info = {
621 .meram_dev = &meram_info,
622 .ch[0] = {
623 .chan = LCDC_CHAN_MAINLCD,
624 .fourcc = V4L2_PIX_FMT_RGB565,
93ff2598
LP		 625 .lcd_modes = ap4evb_lcdc_modes,
626 .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes),
a1022adb
LP		 627 .meram_cfg = &lcd_meram_cfg,
628#ifdef CONFIG_AP4EVB_QHD
629 .tx_dev = &mipidsi0_device,
630#endif
631 }
632};
633
634static struct resource lcdc_resources[] = {
635 [0] = {
636 .name = "LCDC",
637 .start = 0xfe940000, /* P4-only space */
638 .end = 0xfe943fff,
639 .flags = IORESOURCE_MEM,
640 },
641 [1] = {
642 .start = intcs_evt2irq(0x580),
643 .flags = IORESOURCE_IRQ,
644 },
645};
646
647static struct platform_device lcdc_device = {
648 .name = "sh_mobile_lcdc_fb",
649 .num_resources = ARRAY_SIZE(lcdc_resources),
650 .resource = lcdc_resources,
651 .dev = {
652 .platform_data = &lcdc_info,
653 .coherent_dma_mask = ~0,
654 },
655};
656
cb9215e1
KM		 657/* FSI */
658#define IRQ_FSI evt2irq(0x1840)
d4bc99b9
KM		 659static int __fsi_set_rate(struct clk *clk, long rate, int enable)
660{
661 int ret = 0;
662
663 if (rate <= 0)
664 return ret;
2669efec 665
d4bc99b9 666 if (enable) {
22de4e1f 667 ret = clk_set_rate(clk, rate);
d4bc99b9
KM		 668 if (0 == ret)
669 ret = clk_enable(clk);
670 } else {
671 clk_disable(clk);
672 }
673
674 return ret;
675}
676
22de4e1f
KM		 677static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
678{
679 return __fsi_set_rate(clk, clk_round_rate(clk, rate), enable);
680}
681
682static int fsi_ak4642_set_rate(struct device *dev, int rate, int enable)
683{
684 struct clk *fsia_ick;
685 struct clk *fsiack;
686 int ret = -EIO;
687
688 fsia_ick = clk_get(dev, "icka");
689 if (IS_ERR(fsia_ick))
690 return PTR_ERR(fsia_ick);
691
692 /*
693 * FSIACK is connected to AK4642,
694 * and use external clock pin from it.
695 * it is parent of fsia_ick now.
696 */
697 fsiack = clk_get_parent(fsia_ick);
698 if (!fsiack)
699 goto fsia_ick_out;
700
701 /*
702 * we get 1/1 divided clock by setting same rate to fsiack and fsia_ick
703 *
704 ** FIXME **
705 * Because the freq_table of external clk (fsiack) are all 0,
706 * the return value of clk_round_rate became 0.
707 * So, it use __fsi_set_rate here.
708 */
709 ret = __fsi_set_rate(fsiack, rate, enable);
710 if (ret < 0)
711 goto fsiack_out;
712
713 ret = __fsi_set_round_rate(fsia_ick, rate, enable);
714 if ((ret < 0) && enable)
715 __fsi_set_round_rate(fsiack, rate, 0); /* disable FSI ACK */
716
717fsiack_out:
718 clk_put(fsiack);
719
720fsia_ick_out:
721 clk_put(fsia_ick);
722
723 return 0;
724}
725
726static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
2669efec
KM		 727{
728 struct clk *fsib_clk;
729 struct clk *fdiv_clk = &sh7372_fsidivb_clk;
d4bc99b9
KM		 730 long fsib_rate = 0;
731 long fdiv_rate = 0;
732 int ackmd_bpfmd;
2669efec
KM		 733 int ret;
734
2669efec 735 switch (rate) {
574490e3 736 case 44100:
d4bc99b9
KM		 737 fsib_rate = rate * 256;
738 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
574490e3 739 break;
2669efec 740 case 48000:
d4bc99b9
KM		 741 fsib_rate = 85428000; /* around 48kHz x 256 x 7 */
742 fdiv_rate = rate * 256;
743 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
2669efec
KM		 744 break;
745 default:
746 pr_err("unsupported rate in FSI2 port B\n");
d4bc99b9 747 return -EINVAL;
2669efec
KM		 748 }
749
d4bc99b9
KM		 750 /* FSI B setting */
751 fsib_clk = clk_get(dev, "ickb");
752 if (IS_ERR(fsib_clk))
753 return -EIO;
754
22de4e1f 755 ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
d4bc99b9 756 if (ret < 0)
73674648 757 goto fsi_set_rate_end;
d4bc99b9
KM		 758
759 /* FSI DIV setting */
22de4e1f 760 ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
d4bc99b9
KM		 761 if (ret < 0) {
762 /* disable FSI B */
763 if (enable)
22de4e1f 764 __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
73674648 765 goto fsi_set_rate_end;
d4bc99b9 766 }
2669efec 767
73674648
KM		 768 ret = ackmd_bpfmd;
769
770fsi_set_rate_end:
771 clk_put(fsib_clk);
772 return ret;
2669efec
KM		 773}
774
bb04e197 775static struct sh_fsi_platform_info fsi_info = {
fec691e7
KM		 776 .port_a = {
777 .flags = SH_FSI_BRS_INV,
778 .set_rate = fsi_ak4642_set_rate,
779 },
780 .port_b = {
781 .flags = SH_FSI_BRS_INV |
782 SH_FSI_BRM_INV |
783 SH_FSI_LRS_INV |
784 SH_FSI_FMT_SPDIF,
785 .set_rate = fsi_hdmi_set_rate,
786 },
cb9215e1
KM		 787};
788
789static struct resource fsi_resources[] = {
790 [0] = {
791 .name = "FSI",
792 .start = 0xFE3C0000,
793 .end = 0xFE3C0400 - 1,
794 .flags = IORESOURCE_MEM,
795 },
796 [1] = {
797 .start = IRQ_FSI,
798 .flags = IORESOURCE_IRQ,
799 },
800};
801
802static struct platform_device fsi_device = {
803 .name = "sh_fsi2",
9f6f11b6 804 .id = -1,
cb9215e1
KM		 805 .num_resources = ARRAY_SIZE(fsi_resources),
806 .resource = fsi_resources,
807 .dev = {
808 .platform_data = &fsi_info,
809 },
810};
811
af8a2fe1
KM		 812static struct asoc_simple_dai_init_info fsi2_ak4643_init_info = {
813 .fmt = SND_SOC_DAIFMT_LEFT_J,
814 .codec_daifmt = SND_SOC_DAIFMT_CBM_CFM,
815 .cpu_daifmt = SND_SOC_DAIFMT_CBS_CFS,
816 .sysclk = 11289600,
817};
818
819static struct asoc_simple_card_info fsi2_ak4643_info = {
45f31216
KM		 820 .name = "AK4643",
821 .card = "FSI2A-AK4643",
822 .cpu_dai = "fsia-dai",
823 .codec = "ak4642-codec.0-0013",
824 .platform = "sh_fsi2",
af8a2fe1
KM		 825 .codec_dai = "ak4642-hifi",
826 .init = &fsi2_ak4643_init_info,
45f31216
KM		 827};
828
c8d6bf9a 829static struct platform_device fsi_ak4643_device = {
af8a2fe1 830 .name = "asoc-simple-card",
45f31216 831 .dev = {
e49d603c 832 .platform_data = &fsi2_ak4643_info,
45f31216 833 },
c8d6bf9a 834};
45f31216 835
a1022adb 836/* LCDC1 */
640dcfa0
GL		 837static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
838 unsigned long *parent_freq);
839
dfbcdf64 840static struct sh_mobile_hdmi_info hdmi_info = {
2669efec 841 .flags = HDMI_SND_SRC_SPDIF,
640dcfa0 842 .clk_optimize_parent = ap4evb_clk_optimize,
dfbcdf64
GL		 843};
844
845static struct resource hdmi_resources[] = {
846 [0] = {
847 .name = "HDMI",
848 .start = 0xe6be0000,
849 .end = 0xe6be00ff,
850 .flags = IORESOURCE_MEM,
851 },
852 [1] = {
853 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
854 .start = evt2irq(0x17e0),
855 .flags = IORESOURCE_IRQ,
856 },
857};
858
859static struct platform_device hdmi_device = {
860 .name = "sh-mobile-hdmi",
861 .num_resources = ARRAY_SIZE(hdmi_resources),
862 .resource = hdmi_resources,
863 .id = -1,
864 .dev = {
865 .platform_data = &hdmi_info,
866 },
867};
868
640dcfa0
GL		 869static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
870 unsigned long *parent_freq)
871{
872 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
873 long error;
874
875 if (IS_ERR(hdmi_ick)) {
876 int ret = PTR_ERR(hdmi_ick);
877 pr_err("Cannot get HDMI ICK: %d\n", ret);
878 return ret;
879 }
880
881 error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
882
883 clk_put(hdmi_ick);
884
885 return error;
886}
887
c241a0e0 888static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
1c7fcbed 889 .icb[0] = {
1c7fcbed
D		 890 .meram_size = 0x100,
891 },
892 .icb[1] = {
1c7fcbed
D		 893 .meram_size = 0x100,
894 },
895};
c8d6bf9a 896
dfbcdf64
GL		 897static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
898 .clock_source = LCDC_CLK_EXTERNAL,
1c7fcbed 899 .meram_dev = &meram_info,
dfbcdf64
GL		 900 .ch[0] = {
901 .chan = LCDC_CHAN_MAINLCD,
edd153a3 902 .fourcc = V4L2_PIX_FMT_RGB565,
dfbcdf64
GL		 903 .interface_type = RGB24,
904 .clock_divider = 1,
905 .flags = LCDC_FLAGS_DWPOL,
1c7fcbed 906 .meram_cfg = &hdmi_meram_cfg,
a1022adb 907 .tx_dev = &hdmi_device,
dfbcdf64
GL		 908 }
909};
910
911static struct resource lcdc1_resources[] = {
912 [0] = {
913 .name = "LCDC1",
914 .start = 0xfe944000,
915 .end = 0xfe947fff,
916 .flags = IORESOURCE_MEM,
917 },
918 [1] = {
88c759a2 919 .start = intcs_evt2irq(0x1780),
dfbcdf64
GL		 920 .flags = IORESOURCE_IRQ,
921 },
922};
923
924static struct platform_device lcdc1_device = {
925 .name = "sh_mobile_lcdc_fb",
926 .num_resources = ARRAY_SIZE(lcdc1_resources),
927 .resource = lcdc1_resources,
928 .id = 1,
929 .dev = {
930 .platform_data = &sh_mobile_lcdc1_info,
931 .coherent_dma_mask = ~0,
932 },
933};
934
fa063b48
KM		 935static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = {
936 .cpu_daifmt = SND_SOC_DAIFMT_CBM_CFM,
937};
938
939static struct asoc_simple_card_info fsi2_hdmi_info = {
940 .name = "HDMI",
941 .card = "FSI2B-HDMI",
942 .cpu_dai = "fsib-dai",
943 .codec = "sh-mobile-hdmi",
944 .platform = "sh_fsi2",
945 .codec_dai = "sh_mobile_hdmi-hifi",
946 .init = &fsi2_hdmi_init_info,
947};
948
3f25c9cc 949static struct platform_device fsi_hdmi_device = {
fa063b48
KM		 950 .name = "asoc-simple-card",
951 .id = 1,
952 .dev = {
953 .platform_data = &fsi2_hdmi_info,
954 },
3f25c9cc
KM		 955};
956
2863e935
AH		 957static struct gpio_led ap4evb_leds[] = {
958 {
959 .name = "led4",
960 .gpio = GPIO_PORT185,
961 .default_state = LEDS_GPIO_DEFSTATE_ON,
962 },
963 {
964 .name = "led2",
965 .gpio = GPIO_PORT186,
966 .default_state = LEDS_GPIO_DEFSTATE_ON,
967 },
968 {
969 .name = "led3",
970 .gpio = GPIO_PORT187,
971 .default_state = LEDS_GPIO_DEFSTATE_ON,
972 },
973 {
974 .name = "led1",
975 .gpio = GPIO_PORT188,
976 .default_state = LEDS_GPIO_DEFSTATE_ON,
977 }
978};
979
980static struct gpio_led_platform_data ap4evb_leds_pdata = {
981 .num_leds = ARRAY_SIZE(ap4evb_leds),
8050fbf2 982 .leds = ap4evb_leds,
2863e935
AH		 983};
984
985static struct platform_device leds_device = {
986 .name = "leds-gpio",
987 .id = 0,
988 .dev = {
989 .platform_data = &ap4evb_leds_pdata,
990 },
991};
992
1a0b1eac
GL		 993static struct i2c_board_info imx074_info = {
994 I2C_BOARD_INFO("imx074", 0x1a),
995};
996
4d4d6fbb 997static struct soc_camera_link imx074_link = {
1a0b1eac
GL		 998 .bus_id = 0,
999 .board_info = &imx074_info,
1000 .i2c_adapter_id = 0,
1001 .module_name = "imx074",
1002};
1003
1004static struct platform_device ap4evb_camera = {
1005 .name = "soc-camera-pdrv",
1006 .id = 0,
1007 .dev = {
1008 .platform_data = &imx074_link,
1009 },
1010};
1011
1012static struct sh_csi2_client_config csi2_clients[] = {
1013 {
1014 .phy = SH_CSI2_PHY_MAIN,
19a1780b 1015 .lanes = 0, /* default: 2 lanes */
1a0b1eac
GL		 1016 .channel = 0,
1017 .pdev = &ap4evb_camera,
1018 },
1019};
1020
1021static struct sh_csi2_pdata csi2_info = {
1022 .type = SH_CSI2C,
1023 .clients = csi2_clients,
1024 .num_clients = ARRAY_SIZE(csi2_clients),
1025 .flags = SH_CSI2_ECC | SH_CSI2_CRC,
1026};
1027
1028static struct resource csi2_resources[] = {
1029 [0] = {
1030 .name = "CSI2",
1031 .start = 0xffc90000,
1032 .end = 0xffc90fff,
1033 .flags = IORESOURCE_MEM,
1034 },
1035 [1] = {
1036 .start = intcs_evt2irq(0x17a0),
1037 .flags = IORESOURCE_IRQ,
1038 },
1039};
1040
6b526fed
GL		 1041static struct sh_mobile_ceu_companion csi2 = {
1042 .id = 0,
1a0b1eac
GL		 1043 .num_resources = ARRAY_SIZE(csi2_resources),
1044 .resource = csi2_resources,
6b526fed 1045 .platform_data = &csi2_info,
1a0b1eac
GL		 1046};
1047
1048static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
1049 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
ef8f41ff
GL		 1050 .max_width = 8188,
1051 .max_height = 8188,
6b526fed 1052 .csi2 = &csi2,
1a0b1eac
GL		 1053};
1054
1055static struct resource ceu_resources[] = {
1056 [0] = {
1057 .name = "CEU",
1058 .start = 0xfe910000,
1059 .end = 0xfe91009f,
1060 .flags = IORESOURCE_MEM,
1061 },
1062 [1] = {
1063 .start = intcs_evt2irq(0x880),
1064 .flags = IORESOURCE_IRQ,
1065 },
1066 [2] = {
1067 /* place holder for contiguous memory */
1068 },
1069};
1070
1071static struct platform_device ceu_device = {
1072 .name = "sh_mobile_ceu",
1073 .id = 0, /* "ceu0" clock */
1074 .num_resources = ARRAY_SIZE(ceu_resources),
1075 .resource = ceu_resources,
1076 .dev = {
05a5f01c
GL		 1077 .platform_data = &sh_mobile_ceu_info,
1078 .coherent_dma_mask = 0xffffffff,
1a0b1eac
GL		 1079 },
1080};
1081
2b7eda63 1082static struct platform_device *ap4evb_devices[] __initdata = {
2863e935 1083 &leds_device,
2b7eda63 1084 &nor_flash_device,
1b7e0677 1085 &smc911x_device,
3a14d039 1086 &sdhi0_device,
341291a6 1087 &sdhi1_device,
fb54d268 1088 &usb1_host_device,
cb9215e1 1089 &fsi_device,
c8d6bf9a 1090 &fsi_ak4643_device,
3f25c9cc 1091 &fsi_hdmi_device,
beccb12f 1092 &sh_mmcif_device,
dfbcdf64 1093 &hdmi_device,
a1022adb
LP		 1094 &lcdc_device,
1095 &lcdc1_device,
1a0b1eac
GL		 1096 &ceu_device,
1097 &ap4evb_camera,
1c7fcbed 1098 &meram_device,
2b7eda63
MD		 1099};
1100
2ce51f8b 1101static void __init hdmi_init_pm_clock(void)
dfbcdf64
GL		 1102{
1103 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
1104 int ret;
1105 long rate;
1106
1107 if (IS_ERR(hdmi_ick)) {
1108 ret = PTR_ERR(hdmi_ick);
1109 pr_err("Cannot get HDMI ICK: %d\n", ret);
1110 goto out;
1111 }
1112
685e4080 1113 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
dfbcdf64 1114 if (ret < 0) {
685e4080 1115 pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
dfbcdf64
GL		 1116 goto out;
1117 }
1118
685e4080 1119 pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
dfbcdf64 1120
685e4080 1121 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
dfbcdf64
GL		 1122 if (rate < 0) {
1123 pr_err("Cannot get suitable rate: %ld\n", rate);
1124 ret = rate;
1125 goto out;
1126 }
1127
685e4080 1128 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
dfbcdf64
GL		 1129 if (ret < 0) {
1130 pr_err("Cannot set rate %ld: %d\n", rate, ret);
1131 goto out;
1132 }
1133
1134 pr_debug("PLLC2 set frequency %lu\n", rate);
1135
685e4080 1136 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
2ce51f8b 1137 if (ret < 0)
dfbcdf64 1138 pr_err("Cannot set HDMI parent: %d\n", ret);
dfbcdf64
GL		 1139
1140out:
1141 if (!IS_ERR(hdmi_ick))
1142 clk_put(hdmi_ick);
dfbcdf64
GL		 1143}
1144
6084c81e 1145static void __init fsi_init_pm_clock(void)
69ce8aa4
KM		 1146{
1147 struct clk *fsia_ick;
1148 int ret;
1149
69ce8aa4
KM		 1150 fsia_ick = clk_get(&fsi_device.dev, "icka");
1151 if (IS_ERR(fsia_ick)) {
1152 ret = PTR_ERR(fsia_ick);
1153 pr_err("Cannot get FSI ICK: %d\n", ret);
6084c81e 1154 return;
69ce8aa4
KM		 1155 }
1156
1157 ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk);
69ce8aa4 1158 if (ret < 0)
22de4e1f 1159 pr_err("Cannot set FSI-A parent: %d\n", ret);
69ce8aa4 1160
69ce8aa4 1161 clk_put(fsia_ick);
69ce8aa4 1162}
69ce8aa4 1163
9fa1b7fe 1164/* TouchScreen */
52d5ac00
KM		 1165#ifdef CONFIG_AP4EVB_QHD
1166# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
1167# define GPIO_TSC_PORT GPIO_PORT123
1168#else /* WVGA */
1169# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
1170# define GPIO_TSC_PORT GPIO_PORT40
1171#endif
1172
33c9607a 1173#define IRQ28 evt2irq(0x3380) /* IRQ28A */
9fa1b7fe 1174#define IRQ7 evt2irq(0x02e0) /* IRQ7A */
71c3ba9a
KM		 1175static int ts_get_pendown_state(void)
1176{
52d5ac00 1177 int val;
71c3ba9a 1178
52d5ac00 1179 gpio_free(GPIO_TSC_IRQ);
71c3ba9a 1180
52d5ac00 1181 gpio_request(GPIO_TSC_PORT, NULL);
71c3ba9a 1182
52d5ac00 1183 gpio_direction_input(GPIO_TSC_PORT);
71c3ba9a 1184
52d5ac00 1185 val = gpio_get_value(GPIO_TSC_PORT);
71c3ba9a 1186
52d5ac00 1187 gpio_request(GPIO_TSC_IRQ, NULL);
71c3ba9a 1188
52d5ac00 1189 return !val;
71c3ba9a
KM		 1190}
1191
71c3ba9a
KM		 1192static int ts_init(void)
1193{
52d5ac00 1194 gpio_request(GPIO_TSC_IRQ, NULL);
71c3ba9a
KM		 1195
1196 return 0;
1197}
1198
bb04e197 1199static struct tsc2007_platform_data tsc2007_info = {
91cf5082
KM		 1200 .model = 2007,
1201 .x_plate_ohms = 180,
71c3ba9a
KM		 1202 .get_pendown_state = ts_get_pendown_state,
1203 .init_platform_hw = ts_init,
91cf5082
KM		 1204};
1205
9fa1b7fe
KM		 1206static struct i2c_board_info tsc_device = {
1207 I2C_BOARD_INFO("tsc2007", 0x48),
1208 .type = "tsc2007",
1209 .platform_data = &tsc2007_info,
1210 /*.irq is selected on ap4evb_init */
1211};
1212
91cf5082 1213/* I2C */
cb9215e1
KM		 1214static struct i2c_board_info i2c0_devices[] = {
1215 {
1216 I2C_BOARD_INFO("ak4643", 0x13),
1217 },
1218};
1219
91cf5082 1220static struct i2c_board_info i2c1_devices[] = {
8fc883c2
KM		 1221 {
1222 I2C_BOARD_INFO("r2025sd", 0x32),
1223 },
91cf5082
KM		 1224};
1225
2b7eda63 1226
cb9215e1
KM		 1227#define GPIO_PORT9CR 0xE6051009
1228#define GPIO_PORT10CR 0xE605100A
2669efec 1229#define USCCR1 0xE6058144
2b7eda63
MD		 1230static void __init ap4evb_init(void)
1231{
dfbcdf64 1232 u32 srcr4;
cb9215e1
KM		 1233 struct clk *clk;
1234
8778b8f4
GL		 1235 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
1236 ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
1237 regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
1238 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
1239 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
1240
e3b0161b
MD		 1241 /* External clock source */
1242 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1243
1b7e0677
KM		 1244 sh7372_pinmux_init();
1245
b228b48e
KM		 1246 /* enable SCIFA0 */
1247 gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
1248 gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
1249
1b7e0677
KM		 1250 /* enable SMSC911X */
1251 gpio_request(GPIO_FN_CS5A, NULL);
1252 gpio_request(GPIO_FN_IRQ6_39, NULL);
1253
8cb3a2eb
KM		 1254 /* enable Debug switch (S6) */
1255 gpio_request(GPIO_PORT32, NULL);
1256 gpio_request(GPIO_PORT33, NULL);
1257 gpio_request(GPIO_PORT34, NULL);
1258 gpio_request(GPIO_PORT35, NULL);
1259 gpio_direction_input(GPIO_PORT32);
1260 gpio_direction_input(GPIO_PORT33);
1261 gpio_direction_input(GPIO_PORT34);
1262 gpio_direction_input(GPIO_PORT35);
1263 gpio_export(GPIO_PORT32, 0);
1264 gpio_export(GPIO_PORT33, 0);
1265 gpio_export(GPIO_PORT34, 0);
1266 gpio_export(GPIO_PORT35, 0);
1267
3a14d039
MD		 1268 /* SDHI0 */
1269 gpio_request(GPIO_FN_SDHICD0, NULL);
1270 gpio_request(GPIO_FN_SDHIWP0, NULL);
1271 gpio_request(GPIO_FN_SDHICMD0, NULL);
1272 gpio_request(GPIO_FN_SDHICLK0, NULL);
1273 gpio_request(GPIO_FN_SDHID0_3, NULL);
1274 gpio_request(GPIO_FN_SDHID0_2, NULL);
1275 gpio_request(GPIO_FN_SDHID0_1, NULL);
1276 gpio_request(GPIO_FN_SDHID0_0, NULL);
1277
9fa1b7fe
KM		 1278 /* SDHI1 */
1279 gpio_request(GPIO_FN_SDHICMD1, NULL);
1280 gpio_request(GPIO_FN_SDHICLK1, NULL);
1281 gpio_request(GPIO_FN_SDHID1_3, NULL);
1282 gpio_request(GPIO_FN_SDHID1_2, NULL);
1283 gpio_request(GPIO_FN_SDHID1_1, NULL);
1284 gpio_request(GPIO_FN_SDHID1_0, NULL);
91cf5082 1285
c8ee3d4b
KM		 1286 /* MMCIF */
1287 gpio_request(GPIO_FN_MMCD0_0, NULL);
1288 gpio_request(GPIO_FN_MMCD0_1, NULL);
1289 gpio_request(GPIO_FN_MMCD0_2, NULL);
1290 gpio_request(GPIO_FN_MMCD0_3, NULL);
1291 gpio_request(GPIO_FN_MMCD0_4, NULL);
1292 gpio_request(GPIO_FN_MMCD0_5, NULL);
1293 gpio_request(GPIO_FN_MMCD0_6, NULL);
1294 gpio_request(GPIO_FN_MMCD0_7, NULL);
1295 gpio_request(GPIO_FN_MMCCMD0, NULL);
1296 gpio_request(GPIO_FN_MMCCLK0, NULL);
1297
fb54d268
KM		 1298 /* USB enable */
1299 gpio_request(GPIO_FN_VBUS0_1, NULL);
1300 gpio_request(GPIO_FN_IDIN_1_18, NULL);
1301 gpio_request(GPIO_FN_PWEN_1_115, NULL);
1302 gpio_request(GPIO_FN_OVCN_1_114, NULL);
1303 gpio_request(GPIO_FN_EXTLP_1, NULL);
1304 gpio_request(GPIO_FN_OVCN2_1, NULL);
1305
1306 /* setup USB phy */
d0fb0c4b 1307 __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */
fb54d268 1308
2669efec 1309 /* enable FSI2 port A (ak4643) */
cb9215e1
KM		 1310 gpio_request(GPIO_FN_FSIAIBT, NULL);
1311 gpio_request(GPIO_FN_FSIAILR, NULL);
1312 gpio_request(GPIO_FN_FSIAISLD, NULL);
1313 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1314 gpio_request(GPIO_PORT161, NULL);
1315 gpio_direction_output(GPIO_PORT161, 0); /* slave */
1316
1317 gpio_request(GPIO_PORT9, NULL);
1318 gpio_request(GPIO_PORT10, NULL);
6a6196af
KM		 1319 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1320 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
cb9215e1 1321
68accd73
AH		 1322 /* card detect pin for MMC slot (CN7) */
1323 gpio_request(GPIO_PORT41, NULL);
1324 gpio_direction_input(GPIO_PORT41);
1325
2669efec
KM		 1326 /* setup FSI2 port B (HDMI) */
1327 gpio_request(GPIO_FN_FSIBCK, NULL);
1328 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
1329
cb9215e1
KM		 1330 /* set SPU2 clock to 119.6 MHz */
1331 clk = clk_get(NULL, "spu_clk");
2ae2b766 1332 if (!IS_ERR(clk)) {
cb9215e1
KM		 1333 clk_set_rate(clk, clk_round_rate(clk, 119600000));
1334 clk_put(clk);
1335 }
1336
cb9215e1
KM		 1337 /*
1338 * set irq priority, to avoid sound chopping
1339 * when NFS rootfs is used
1340 * FSI(3) > SMSC911X(2)
1341 */
1342 intc_set_priority(IRQ_FSI, 3);
1343
1344 i2c_register_board_info(0, i2c0_devices,
1345 ARRAY_SIZE(i2c0_devices));
1346
1347 i2c_register_board_info(1, i2c1_devices,
1348 ARRAY_SIZE(i2c1_devices));
1349
9fa1b7fe 1350#ifdef CONFIG_AP4EVB_QHD
dd8a61a7 1351
9fa1b7fe 1352 /*
dd8a61a7
MD		 1353 * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
1354 * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
9fa1b7fe
KM		 1355 */
1356
1357 /* enable KEYSC */
1358 gpio_request(GPIO_FN_KEYOUT0, NULL);
1359 gpio_request(GPIO_FN_KEYOUT1, NULL);
1360 gpio_request(GPIO_FN_KEYOUT2, NULL);
1361 gpio_request(GPIO_FN_KEYOUT3, NULL);
1362 gpio_request(GPIO_FN_KEYOUT4, NULL);
1363 gpio_request(GPIO_FN_KEYIN0_136, NULL);
1364 gpio_request(GPIO_FN_KEYIN1_135, NULL);
1365 gpio_request(GPIO_FN_KEYIN2_134, NULL);
1366 gpio_request(GPIO_FN_KEYIN3_133, NULL);
1367 gpio_request(GPIO_FN_KEYIN4, NULL);
1368
1369 /* enable TouchScreen */
6845664a 1370 irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
9fa1b7fe
KM		 1371
1372 tsc_device.irq = IRQ28;
1373 i2c_register_board_info(1, &tsc_device, 1);
1374
1375 /* LCDC0 */
1376 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
1377 lcdc_info.ch[0].interface_type = RGB24;
1378 lcdc_info.ch[0].clock_divider = 1;
1379 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
afaad83b
LP		 1380 lcdc_info.ch[0].panel_cfg.width = 44;
1381 lcdc_info.ch[0].panel_cfg.height = 79;
9fa1b7fe
KM		 1382
1383 platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
1384
1385#else
1386 /*
dd8a61a7
MD		 1387 * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
1388 * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
9fa1b7fe 1389 */
dd8a61a7 1390
9fa1b7fe
KM		 1391 gpio_request(GPIO_FN_LCDD17, NULL);
1392 gpio_request(GPIO_FN_LCDD16, NULL);
1393 gpio_request(GPIO_FN_LCDD15, NULL);
1394 gpio_request(GPIO_FN_LCDD14, NULL);
1395 gpio_request(GPIO_FN_LCDD13, NULL);
1396 gpio_request(GPIO_FN_LCDD12, NULL);
1397 gpio_request(GPIO_FN_LCDD11, NULL);
1398 gpio_request(GPIO_FN_LCDD10, NULL);
1399 gpio_request(GPIO_FN_LCDD9, NULL);
1400 gpio_request(GPIO_FN_LCDD8, NULL);
1401 gpio_request(GPIO_FN_LCDD7, NULL);
1402 gpio_request(GPIO_FN_LCDD6, NULL);
1403 gpio_request(GPIO_FN_LCDD5, NULL);
1404 gpio_request(GPIO_FN_LCDD4, NULL);
1405 gpio_request(GPIO_FN_LCDD3, NULL);
1406 gpio_request(GPIO_FN_LCDD2, NULL);
1407 gpio_request(GPIO_FN_LCDD1, NULL);
1408 gpio_request(GPIO_FN_LCDD0, NULL);
1409 gpio_request(GPIO_FN_LCDDISP, NULL);
1410 gpio_request(GPIO_FN_LCDDCK, NULL);
1411
1412 gpio_request(GPIO_PORT189, NULL); /* backlight */
1413 gpio_direction_output(GPIO_PORT189, 1);
1414
1415 gpio_request(GPIO_PORT151, NULL); /* LCDDON */
1416 gpio_direction_output(GPIO_PORT151, 1);
1417
1418 lcdc_info.clock_source = LCDC_CLK_BUS;
1419 lcdc_info.ch[0].interface_type = RGB18;
f60cb470 1420 lcdc_info.ch[0].clock_divider = 3;
9fa1b7fe 1421 lcdc_info.ch[0].flags = 0;
afaad83b
LP		 1422 lcdc_info.ch[0].panel_cfg.width = 152;
1423 lcdc_info.ch[0].panel_cfg.height = 91;
9fa1b7fe
KM		 1424
1425 /* enable TouchScreen */
6845664a 1426 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
9fa1b7fe
KM		 1427
1428 tsc_device.irq = IRQ7;
1429 i2c_register_board_info(0, &tsc_device, 1);
1430#endif /* CONFIG_AP4EVB_QHD */
341291a6 1431
1a0b1eac
GL		 1432 /* CEU */
1433
1434 /*
1435 * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
1436 * becomes available
1437 */
1438
1439 /* MIPI-CSI stuff */
1440 gpio_request(GPIO_FN_VIO_CKO, NULL);
1441
1442 clk = clk_get(NULL, "vck1_clk");
1443 if (!IS_ERR(clk)) {
1444 clk_set_rate(clk, clk_round_rate(clk, 13000000));
1445 clk_enable(clk);
1446 clk_put(clk);
1447 }
1448
2b7eda63
MD		 1449 sh7372_add_standard_devices();
1450
dfbcdf64
GL		 1451 /* HDMI */
1452 gpio_request(GPIO_FN_HDMI_HPD, NULL);
1453 gpio_request(GPIO_FN_HDMI_CEC, NULL);
1454
1455 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
1456#define SRCR4 0xe61580bc
1457 srcr4 = __raw_readl(SRCR4);
1458 __raw_writel(srcr4 | (1 << 13), SRCR4);
1459 udelay(50);
1460 __raw_writel(srcr4 & ~(1 << 13), SRCR4);
1461
2b7eda63 1462 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
2ce51f8b 1463
8bdd9468
RW		 1464 rmobile_add_device_to_domain("A4LC", &lcdc1_device);
1465 rmobile_add_device_to_domain("A4LC", &lcdc_device);
1466 rmobile_add_device_to_domain("A4MP", &fsi_device);
1467
1468 rmobile_add_device_to_domain("A3SP", &sh_mmcif_device);
1469 rmobile_add_device_to_domain("A3SP", &sdhi0_device);
1470 rmobile_add_device_to_domain("A3SP", &sdhi1_device);
1471 rmobile_add_device_to_domain("A4R", &ceu_device);
d93f5cde 1472
2ce51f8b 1473 hdmi_init_pm_clock();
6084c81e 1474 fsi_init_pm_clock();
97991657 1475 sh7372_pm_init();
a41b6466 1476 pm_clk_add(&fsi_device.dev, "spu2");
d0168fdc 1477 pm_clk_add(&lcdc1_device.dev, "hdmi");
2b7eda63
MD		 1478}
1479
1480MACHINE_START(AP4EVB, "ap4evb")
5d7220ec
MD		 1481 .map_io = sh7372_map_io,
1482 .init_early = sh7372_add_early_devices,
2b7eda63 1483 .init_irq = sh7372_init_irq,
863b1719 1484 .handle_irq = shmobile_handle_irq_intc,
2b7eda63 1485 .init_machine = ap4evb_init,
21cc1b7e 1486 .init_late = shmobile_init_late,
17254bff 1487 .timer = &shmobile_timer,
2b7eda63 1488MACHINE_END
Linux kernel - Deliverables
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