projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] V4L: rj54n1cb0c: support the new mbus-config subdev ops
[deliverable/linux.git] / arch / arm / mach-shmobile / board-ap4evb.c
CommitLineData
2b7eda63
MD		 1/*
2 * AP4EVB board support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
8eda2f21 20#include <linux/clk.h>
2b7eda63
MD		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
410d878b 27#include <linux/mfd/tmio.h>
341291a6 28#include <linux/mmc/host.h>
17e75d82 29#include <linux/mmc/sh_mobile_sdhi.h>
2b7eda63
MD		 30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h>
32#include <linux/mtd/physmap.h>
c8ee3d4b 33#include <linux/mmc/sh_mmcif.h>
91cf5082
KM		 34#include <linux/i2c.h>
35#include <linux/i2c/tsc2007.h>
2b7eda63 36#include <linux/io.h>
1b7e0677 37#include <linux/smsc911x.h>
cb9215e1
KM		 38#include <linux/sh_intc.h>
39#include <linux/sh_clk.h>
1b7e0677 40#include <linux/gpio.h>
17ccb834 41#include <linux/input.h>
2863e935 42#include <linux/leds.h>
17ccb834 43#include <linux/input/sh_keysc.h>
fb54d268 44#include <linux/usb/r8a66597.h>
b5e8d269 45#include <linux/pm_clock.h>
9b742024 46#include <linux/dma-mapping.h>
8eda2f21 47
1a0b1eac
GL		 48#include <media/sh_mobile_ceu.h>
49#include <media/sh_mobile_csi2.h>
50#include <media/soc_camera.h>
51
cb9215e1
KM		 52#include <sound/sh_fsi.h>
53
dfbcdf64 54#include <video/sh_mobile_hdmi.h>
8eda2f21
GL		 55#include <video/sh_mobile_lcdc.h>
56#include <video/sh_mipi_dsi.h>
57
2b7eda63 58#include <mach/common.h>
8eda2f21 59#include <mach/irqs.h>
1b7e0677 60#include <mach/sh7372.h>
8eda2f21 61
2b7eda63
MD		 62#include <asm/mach-types.h>
63#include <asm/mach/arch.h>
64#include <asm/mach/map.h>
495b3cea 65#include <asm/mach/time.h>
3d09fbcd 66#include <asm/setup.h>
2b7eda63 67
02624a17
KM		 68/*
69 * Address Interface BusWidth note
70 * ------------------------------------------------------------------
71 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON
72 * 0x0800_0000 user area -
73 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF
74 * 0x1400_0000 Ether (LAN9220) 16bit
75 * 0x1600_0000 user area - cannot use with NAND
76 * 0x1800_0000 user area -
77 * 0x1A00_0000 -
78 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit
79 */
80
81/*
82 * NOR Flash ROM
83 *
84 * SW1 | SW2 | SW7 | NOR Flash ROM
85 * bit1 | bit1 bit2 | bit1 | Memory allocation
86 * ------+------------+------+------------------
87 * OFF | ON OFF | ON | Area 0
88 * OFF | ON OFF | OFF | Area 4
89 */
90
91/*
92 * NAND Flash ROM
93 *
94 * SW1 | SW2 | SW7 | NAND Flash ROM
95 * bit1 | bit1 bit2 | bit2 | Memory allocation
96 * ------+------------+------+------------------
97 * OFF | ON OFF | ON | FCE 0
98 * OFF | ON OFF | OFF | FCE 1
99 */
100
101/*
102 * SMSC 9220
103 *
104 * SW1 SMSC 9220
105 * -----------------------
106 * ON access disable
107 * OFF access enable
108 */
109
17ccb834 110/*
dda128dc 111 * LCD / IRQ / KEYSC / IrDA
17ccb834 112 *
9fa1b7fe
KM		 113 * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen)
114 * LCD = 2nd LCDC (WVGA)
dda128dc
KM		 115 *
116 * | SW43 |
117 * SW3 | ON | OFF |
118 * -------------+-----------------------+---------------+
119 * ON | KEY / IrDA | LCD |
120 * OFF | KEY / IrDA / IRQ | IRQ |
9fa1b7fe
KM		 121 *
122 *
123 * QHD / WVGA display
124 *
125 * You can choice display type on menuconfig.
126 * Then, check above dip-switch.
17ccb834
KM		 127 */
128
fb54d268
KM		 129/*
130 * USB
131 *
132 * J7 : 1-2 MAX3355E VBUS
133 * 2-3 DC 5.0V
134 *
135 * S39: bit2: off
136 */
137
cb9215e1
KM		 138/*
139 * FSI/FSMI
140 *
141 * SW41 : ON : SH-Mobile AP4 Audio Mode
142 * : OFF : Bluetooth Audio Mode
143 */
144
c8ee3d4b 145/*
d3d03e48 146 * MMC0/SDHI1 (CN7)
c8ee3d4b 147 *
d3d03e48
KM		 148 * J22 : select card voltage
149 * 1-2 pin : 1.8v
150 * 2-3 pin : 3.3v
151 *
152 * SW1 | SW33
153 * | bit1 | bit2 | bit3 | bit4
154 * ------------+------+------+------+-------
155 * MMC0 OFF | OFF | ON | ON | X
156 * SDHI1 OFF | ON | X | OFF | ON
157 *
158 * voltage lebel
159 * CN7 : 1.8v
160 * CN12: 3.3v
c8ee3d4b
KM		 161 */
162
1b7e0677 163/* MTD */
2b7eda63
MD		 164static struct mtd_partition nor_flash_partitions[] = {
165 {
166 .name = "loader",
167 .offset = 0x00000000,
168 .size = 512 * 1024,
2e351ec6 169 .mask_flags = MTD_WRITEABLE,
2b7eda63
MD		 170 },
171 {
172 .name = "bootenv",
173 .offset = MTDPART_OFS_APPEND,
174 .size = 512 * 1024,
2e351ec6 175 .mask_flags = MTD_WRITEABLE,
2b7eda63
MD		 176 },
177 {
178 .name = "kernel_ro",
179 .offset = MTDPART_OFS_APPEND,
180 .size = 8 * 1024 * 1024,
181 .mask_flags = MTD_WRITEABLE,
182 },
183 {
184 .name = "kernel",
185 .offset = MTDPART_OFS_APPEND,
186 .size = 8 * 1024 * 1024,
187 },
188 {
189 .name = "data",
190 .offset = MTDPART_OFS_APPEND,
191 .size = MTDPART_SIZ_FULL,
192 },
193};
194
195static struct physmap_flash_data nor_flash_data = {
196 .width = 2,
197 .parts = nor_flash_partitions,
198 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
199};
200
201static struct resource nor_flash_resources[] = {
202 [0] = {
203 .start = 0x00000000,
204 .end = 0x08000000 - 1,
205 .flags = IORESOURCE_MEM,
206 }
207};
208
209static struct platform_device nor_flash_device = {
210 .name = "physmap-flash",
211 .dev = {
212 .platform_data = &nor_flash_data,
213 },
214 .num_resources = ARRAY_SIZE(nor_flash_resources),
215 .resource = nor_flash_resources,
216};
217
1b7e0677
KM		 218/* SMSC 9220 */
219static struct resource smc911x_resources[] = {
220 {
221 .start = 0x14000000,
222 .end = 0x16000000 - 1,
223 .flags = IORESOURCE_MEM,
224 }, {
33c9607a 225 .start = evt2irq(0x02c0) /* IRQ6A */,
1b7e0677
KM		 226 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
227 },
228};
229
230static struct smsc911x_platform_config smsc911x_info = {
231 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
232 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
233 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
234};
235
236static struct platform_device smc911x_device = {
237 .name = "smsc911x",
238 .id = -1,
239 .num_resources = ARRAY_SIZE(smc911x_resources),
240 .resource = smc911x_resources,
241 .dev = {
242 .platform_data = &smsc911x_info,
243 },
244};
2b7eda63 245
68accd73
AH		 246/*
247 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
248 * connected to GPIO A22 of SH7372 (GPIO_PORT41).
249 */
250static int slot_cn7_get_cd(struct platform_device *pdev)
251{
ceb50f33 252 return !gpio_get_value(GPIO_PORT41);
68accd73 253}
1c7fcbed
D		 254/* MERAM */
255static struct sh_mobile_meram_info meram_info = {
256 .addr_mode = SH_MOBILE_MERAM_MODE1,
257};
258
259static struct resource meram_resources[] = {
260 [0] = {
261 .name = "MERAM",
262 .start = 0xe8000000,
263 .end = 0xe81fffff,
264 .flags = IORESOURCE_MEM,
265 },
266};
267
268static struct platform_device meram_device = {
269 .name = "sh_mobile_meram",
270 .id = 0,
271 .num_resources = ARRAY_SIZE(meram_resources),
272 .resource = meram_resources,
273 .dev = {
274 .platform_data = &meram_info,
275 },
276};
68accd73 277
c8ee3d4b
KM		 278/* SH_MMCIF */
279static struct resource sh_mmcif_resources[] = {
280 [0] = {
0fb0834b 281 .name = "MMCIF",
c8ee3d4b
KM		 282 .start = 0xE6BD0000,
283 .end = 0xE6BD00FF,
284 .flags = IORESOURCE_MEM,
285 },
286 [1] = {
287 /* MMC ERR */
8d569341 288 .start = evt2irq(0x1ac0),
c8ee3d4b
KM		 289 .flags = IORESOURCE_IRQ,
290 },
291 [2] = {
292 /* MMC NOR */
8d569341 293 .start = evt2irq(0x1ae0),
c8ee3d4b
KM		 294 .flags = IORESOURCE_IRQ,
295 },
296};
297
df73af86
GL		 298static struct sh_mmcif_dma sh_mmcif_dma = {
299 .chan_priv_rx = {
300 .slave_id = SHDMA_SLAVE_MMCIF_RX,
301 },
302 .chan_priv_tx = {
303 .slave_id = SHDMA_SLAVE_MMCIF_TX,
304 },
305};
306
bb04e197 307static struct sh_mmcif_plat_data sh_mmcif_plat = {
c8ee3d4b
KM		 308 .sup_pclk = 0,
309 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
310 .caps = MMC_CAP_4_BIT_DATA |
311 MMC_CAP_8_BIT_DATA |
312 MMC_CAP_NEEDS_POLL,
68accd73 313 .get_cd = slot_cn7_get_cd,
df73af86 314 .dma = &sh_mmcif_dma,
c8ee3d4b
KM		 315};
316
317static struct platform_device sh_mmcif_device = {
318 .name = "sh_mmcif",
319 .id = 0,
320 .dev = {
321 .dma_mask = NULL,
322 .coherent_dma_mask = 0xffffffff,
323 .platform_data = &sh_mmcif_plat,
324 },
325 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
326 .resource = sh_mmcif_resources,
327};
328
3a14d039 329/* SDHI0 */
69bf6f45 330static struct sh_mobile_sdhi_info sdhi0_info = {
341291a6
GL		 331 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
332 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
330e4e71 333 .tmio_caps = MMC_CAP_SDIO_IRQ,
69bf6f45
GL		 334};
335
3a14d039
MD		 336static struct resource sdhi0_resources[] = {
337 [0] = {
338 .name = "SDHI0",
339 .start = 0xe6850000,
31d31fe7 340 .end = 0xe68500ff,
3a14d039
MD		 341 .flags = IORESOURCE_MEM,
342 },
343 [1] = {
2007aea1
SH		 344 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
345 .flags = IORESOURCE_IRQ,
346 },
347 [2] = {
348 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
349 .flags = IORESOURCE_IRQ,
350 },
351 [3] = {
352 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
353 .flags = IORESOURCE_IRQ,
3a14d039
MD		 354 },
355};
356
357static struct platform_device sdhi0_device = {
358 .name = "sh_mobile_sdhi",
359 .num_resources = ARRAY_SIZE(sdhi0_resources),
360 .resource = sdhi0_resources,
361 .id = 0,
69bf6f45
GL		 362 .dev = {
363 .platform_data = &sdhi0_info,
364 },
3a14d039
MD		 365};
366
341291a6
GL		 367/* SDHI1 */
368static struct sh_mobile_sdhi_info sdhi1_info = {
369 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
370 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
371 .tmio_ocr_mask = MMC_VDD_165_195,
410d878b 372 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
330e4e71 373 .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
68accd73 374 .get_cd = slot_cn7_get_cd,
341291a6
GL		 375};
376
377static struct resource sdhi1_resources[] = {
378 [0] = {
379 .name = "SDHI1",
380 .start = 0xe6860000,
31d31fe7 381 .end = 0xe68600ff,
341291a6
GL		 382 .flags = IORESOURCE_MEM,
383 },
384 [1] = {
2007aea1
SH		 385 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
386 .flags = IORESOURCE_IRQ,
387 },
388 [2] = {
389 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
390 .flags = IORESOURCE_IRQ,
391 },
392 [3] = {
393 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
394 .flags = IORESOURCE_IRQ,
341291a6
GL		 395 },
396};
397
398static struct platform_device sdhi1_device = {
399 .name = "sh_mobile_sdhi",
400 .num_resources = ARRAY_SIZE(sdhi1_resources),
401 .resource = sdhi1_resources,
402 .id = 1,
403 .dev = {
404 .platform_data = &sdhi1_info,
405 },
406};
407
fb54d268 408/* USB1 */
bb04e197 409static void usb1_host_port_power(int port, int power)
fb54d268
KM		 410{
411 if (!power) /* only power-on supported for now */
412 return;
413
414 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
415 __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
416}
417
418static struct r8a66597_platdata usb1_host_data = {
419 .on_chip = 1,
420 .port_power = usb1_host_port_power,
421};
422
423static struct resource usb1_host_resources[] = {
424 [0] = {
425 .name = "USBHS",
426 .start = 0xE68B0000,
427 .end = 0xE68B00E6 - 1,
428 .flags = IORESOURCE_MEM,
429 },
430 [1] = {
33c9607a 431 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
fb54d268
KM		 432 .flags = IORESOURCE_IRQ,
433 },
434};
435
436static struct platform_device usb1_host_device = {
437 .name = "r8a66597_hcd",
438 .id = 1,
439 .dev = {
440 .dma_mask = NULL, /* not use dma */
441 .coherent_dma_mask = 0xffffffff,
442 .platform_data = &usb1_host_data,
443 },
444 .num_resources = ARRAY_SIZE(usb1_host_resources),
445 .resource = usb1_host_resources,
446};
447
82d508fa 448static const struct fb_videomode ap4evb_lcdc_modes[] = {
44432407
GL		 449 {
450#ifdef CONFIG_AP4EVB_QHD
451 .name = "R63302(QHD)",
452 .xres = 544,
453 .yres = 961,
454 .left_margin = 72,
455 .right_margin = 600,
456 .hsync_len = 16,
457 .upper_margin = 8,
458 .lower_margin = 8,
459 .vsync_len = 2,
460 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
461#else
462 .name = "WVGA Panel",
463 .xres = 800,
464 .yres = 480,
465 .left_margin = 220,
466 .right_margin = 110,
467 .hsync_len = 70,
468 .upper_margin = 20,
469 .lower_margin = 5,
470 .vsync_len = 5,
471 .sync = 0,
472#endif
473 },
474};
1c7fcbed
D		 475static struct sh_mobile_meram_cfg lcd_meram_cfg = {
476 .icb[0] = {
477 .marker_icb = 28,
478 .cache_icb = 24,
479 .meram_offset = 0x0,
480 .meram_size = 0x40,
481 },
482 .icb[1] = {
483 .marker_icb = 29,
484 .cache_icb = 25,
485 .meram_offset = 0x40,
486 .meram_size = 0x40,
487 },
488};
44432407 489
9fa1b7fe 490static struct sh_mobile_lcdc_info lcdc_info = {
1c7fcbed 491 .meram_dev = &meram_info,
8eda2f21
GL		 492 .ch[0] = {
493 .chan = LCDC_CHAN_MAINLCD,
494 .bpp = 16,
44432407
GL		 495 .lcd_cfg = ap4evb_lcdc_modes,
496 .num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
1c7fcbed 497 .meram_cfg = &lcd_meram_cfg,
8eda2f21
GL		 498 }
499};
500
501static struct resource lcdc_resources[] = {
502 [0] = {
503 .name = "LCDC",
504 .start = 0xfe940000, /* P4-only space */
505 .end = 0xfe943fff,
506 .flags = IORESOURCE_MEM,
507 },
508 [1] = {
509 .start = intcs_evt2irq(0x580),
510 .flags = IORESOURCE_IRQ,
511 },
512};
513
514static struct platform_device lcdc_device = {
515 .name = "sh_mobile_lcdc_fb",
516 .num_resources = ARRAY_SIZE(lcdc_resources),
517 .resource = lcdc_resources,
518 .dev = {
9fa1b7fe 519 .platform_data = &lcdc_info,
8eda2f21
GL		 520 .coherent_dma_mask = ~0,
521 },
522};
523
9fa1b7fe
KM		 524/*
525 * QHD display
526 */
527#ifdef CONFIG_AP4EVB_QHD
528
529/* KEYSC (Needs SW43 set to ON) */
530static struct sh_keysc_info keysc_info = {
531 .mode = SH_KEYSC_MODE_1,
532 .scan_timing = 3,
533 .delay = 2500,
534 .keycodes = {
535 KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
536 KEY_5, KEY_6, KEY_7, KEY_8, KEY_9,
537 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
538 KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
539 KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
540 },
541};
542
543static struct resource keysc_resources[] = {
544 [0] = {
545 .name = "KEYSC",
546 .start = 0xe61b0000,
547 .end = 0xe61b0063,
548 .flags = IORESOURCE_MEM,
549 },
550 [1] = {
551 .start = evt2irq(0x0be0), /* KEYSC_KEY */
552 .flags = IORESOURCE_IRQ,
553 },
554};
555
556static struct platform_device keysc_device = {
557 .name = "sh_keysc",
558 .id = 0, /* "keysc0" clock */
559 .num_resources = ARRAY_SIZE(keysc_resources),
560 .resource = keysc_resources,
561 .dev = {
562 .platform_data = &keysc_info,
563 },
564};
565
566/* MIPI-DSI */
8eda2f21
GL		 567static struct resource mipidsi0_resources[] = {
568 [0] = {
569 .start = 0xffc60000,
5958d58a
MD		 570 .end = 0xffc63073,
571 .flags = IORESOURCE_MEM,
572 },
573 [1] = {
574 .start = 0xffc68000,
575 .end = 0xffc680ef,
8eda2f21
GL		 576 .flags = IORESOURCE_MEM,
577 },
578};
579
580static struct sh_mipi_dsi_info mipidsi0_info = {
581 .data_format = MIPI_RGB888,
9fa1b7fe 582 .lcd_chan = &lcdc_info.ch[0],
6fd46595 583 .vsynw_offset = 17,
8eda2f21
GL		 584};
585
586static struct platform_device mipidsi0_device = {
587 .name = "sh-mipi-dsi",
588 .num_resources = ARRAY_SIZE(mipidsi0_resources),
589 .resource = mipidsi0_resources,
590 .id = 0,
591 .dev = {
592 .platform_data = &mipidsi0_info,
593 },
594};
595
9fa1b7fe
KM		 596static struct platform_device *qhd_devices[] __initdata = {
597 &mipidsi0_device,
598 &keysc_device,
599};
600#endif /* CONFIG_AP4EVB_QHD */
601
cb9215e1
KM		 602/* FSI */
603#define IRQ_FSI evt2irq(0x1840)
d4bc99b9
KM		 604static int __fsi_set_rate(struct clk *clk, long rate, int enable)
605{
606 int ret = 0;
607
608 if (rate <= 0)
609 return ret;
2669efec 610
d4bc99b9 611 if (enable) {
22de4e1f 612 ret = clk_set_rate(clk, rate);
d4bc99b9
KM		 613 if (0 == ret)
614 ret = clk_enable(clk);
615 } else {
616 clk_disable(clk);
617 }
618
619 return ret;
620}
621
22de4e1f
KM		 622static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
623{
624 return __fsi_set_rate(clk, clk_round_rate(clk, rate), enable);
625}
626
627static int fsi_ak4642_set_rate(struct device *dev, int rate, int enable)
628{
629 struct clk *fsia_ick;
630 struct clk *fsiack;
631 int ret = -EIO;
632
633 fsia_ick = clk_get(dev, "icka");
634 if (IS_ERR(fsia_ick))
635 return PTR_ERR(fsia_ick);
636
637 /*
638 * FSIACK is connected to AK4642,
639 * and use external clock pin from it.
640 * it is parent of fsia_ick now.
641 */
642 fsiack = clk_get_parent(fsia_ick);
643 if (!fsiack)
644 goto fsia_ick_out;
645
646 /*
647 * we get 1/1 divided clock by setting same rate to fsiack and fsia_ick
648 *
649 ** FIXME **
650 * Because the freq_table of external clk (fsiack) are all 0,
651 * the return value of clk_round_rate became 0.
652 * So, it use __fsi_set_rate here.
653 */
654 ret = __fsi_set_rate(fsiack, rate, enable);
655 if (ret < 0)
656 goto fsiack_out;
657
658 ret = __fsi_set_round_rate(fsia_ick, rate, enable);
659 if ((ret < 0) && enable)
660 __fsi_set_round_rate(fsiack, rate, 0); /* disable FSI ACK */
661
662fsiack_out:
663 clk_put(fsiack);
664
665fsia_ick_out:
666 clk_put(fsia_ick);
667
668 return 0;
669}
670
671static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
2669efec
KM		 672{
673 struct clk *fsib_clk;
674 struct clk *fdiv_clk = &sh7372_fsidivb_clk;
d4bc99b9
KM		 675 long fsib_rate = 0;
676 long fdiv_rate = 0;
677 int ackmd_bpfmd;
2669efec
KM		 678 int ret;
679
2669efec 680 switch (rate) {
574490e3 681 case 44100:
d4bc99b9
KM		 682 fsib_rate = rate * 256;
683 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
574490e3 684 break;
2669efec 685 case 48000:
d4bc99b9
KM		 686 fsib_rate = 85428000; /* around 48kHz x 256 x 7 */
687 fdiv_rate = rate * 256;
688 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
2669efec
KM		 689 break;
690 default:
691 pr_err("unsupported rate in FSI2 port B\n");
d4bc99b9 692 return -EINVAL;
2669efec
KM		 693 }
694
d4bc99b9
KM		 695 /* FSI B setting */
696 fsib_clk = clk_get(dev, "ickb");
697 if (IS_ERR(fsib_clk))
698 return -EIO;
699
22de4e1f 700 ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
d4bc99b9 701 if (ret < 0)
73674648 702 goto fsi_set_rate_end;
d4bc99b9
KM		 703
704 /* FSI DIV setting */
22de4e1f 705 ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
d4bc99b9
KM		 706 if (ret < 0) {
707 /* disable FSI B */
708 if (enable)
22de4e1f 709 __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
73674648 710 goto fsi_set_rate_end;
d4bc99b9 711 }
2669efec 712
73674648
KM		 713 ret = ackmd_bpfmd;
714
715fsi_set_rate_end:
716 clk_put(fsib_clk);
717 return ret;
2669efec
KM		 718}
719
22de4e1f
KM		 720static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
721{
722 int ret;
723
724 if (is_porta)
725 ret = fsi_ak4642_set_rate(dev, rate, enable);
726 else
727 ret = fsi_hdmi_set_rate(dev, rate, enable);
728
729 return ret;
730}
731
bb04e197 732static struct sh_fsi_platform_info fsi_info = {
f17c13ca 733 .porta_flags = SH_FSI_BRS_INV,
2669efec
KM		 734
735 .portb_flags = SH_FSI_BRS_INV |
736 SH_FSI_BRM_INV |
737 SH_FSI_LRS_INV |
f17c13ca 738 SH_FSI_FMT_SPDIF,
2669efec 739 .set_rate = fsi_set_rate,
cb9215e1
KM		 740};
741
742static struct resource fsi_resources[] = {
743 [0] = {
744 .name = "FSI",
745 .start = 0xFE3C0000,
746 .end = 0xFE3C0400 - 1,
747 .flags = IORESOURCE_MEM,
748 },
749 [1] = {
750 .start = IRQ_FSI,
751 .flags = IORESOURCE_IRQ,
752 },
753};
754
755static struct platform_device fsi_device = {
756 .name = "sh_fsi2",
9f6f11b6 757 .id = -1,
cb9215e1
KM		 758 .num_resources = ARRAY_SIZE(fsi_resources),
759 .resource = fsi_resources,
760 .dev = {
761 .platform_data = &fsi_info,
762 },
763};
764
c8d6bf9a
KM		 765static struct platform_device fsi_ak4643_device = {
766 .name = "sh_fsi2_a_ak4643",
767};
1c7fcbed
D		 768static struct sh_mobile_meram_cfg hdmi_meram_cfg = {
769 .icb[0] = {
770 .marker_icb = 30,
771 .cache_icb = 26,
772 .meram_offset = 0x80,
773 .meram_size = 0x100,
774 },
775 .icb[1] = {
776 .marker_icb = 31,
777 .cache_icb = 27,
778 .meram_offset = 0x180,
779 .meram_size = 0x100,
780 },
781};
c8d6bf9a 782
dfbcdf64
GL		 783static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
784 .clock_source = LCDC_CLK_EXTERNAL,
1c7fcbed 785 .meram_dev = &meram_info,
dfbcdf64
GL		 786 .ch[0] = {
787 .chan = LCDC_CHAN_MAINLCD,
788 .bpp = 16,
789 .interface_type = RGB24,
790 .clock_divider = 1,
791 .flags = LCDC_FLAGS_DWPOL,
1c7fcbed 792 .meram_cfg = &hdmi_meram_cfg,
dfbcdf64
GL		 793 }
794};
795
796static struct resource lcdc1_resources[] = {
797 [0] = {
798 .name = "LCDC1",
799 .start = 0xfe944000,
800 .end = 0xfe947fff,
801 .flags = IORESOURCE_MEM,
802 },
803 [1] = {
88c759a2 804 .start = intcs_evt2irq(0x1780),
dfbcdf64
GL		 805 .flags = IORESOURCE_IRQ,
806 },
807};
808
809static struct platform_device lcdc1_device = {
810 .name = "sh_mobile_lcdc_fb",
811 .num_resources = ARRAY_SIZE(lcdc1_resources),
812 .resource = lcdc1_resources,
813 .id = 1,
814 .dev = {
815 .platform_data = &sh_mobile_lcdc1_info,
816 .coherent_dma_mask = ~0,
817 },
818};
819
640dcfa0
GL		 820static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
821 unsigned long *parent_freq);
822
823
dfbcdf64
GL		 824static struct sh_mobile_hdmi_info hdmi_info = {
825 .lcd_chan = &sh_mobile_lcdc1_info.ch[0],
826 .lcd_dev = &lcdc1_device.dev,
2669efec 827 .flags = HDMI_SND_SRC_SPDIF,
640dcfa0 828 .clk_optimize_parent = ap4evb_clk_optimize,
dfbcdf64
GL		 829};
830
831static struct resource hdmi_resources[] = {
832 [0] = {
833 .name = "HDMI",
834 .start = 0xe6be0000,
835 .end = 0xe6be00ff,
836 .flags = IORESOURCE_MEM,
837 },
838 [1] = {
839 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
840 .start = evt2irq(0x17e0),
841 .flags = IORESOURCE_IRQ,
842 },
843};
844
845static struct platform_device hdmi_device = {
846 .name = "sh-mobile-hdmi",
847 .num_resources = ARRAY_SIZE(hdmi_resources),
848 .resource = hdmi_resources,
849 .id = -1,
850 .dev = {
851 .platform_data = &hdmi_info,
852 },
853};
854
3f25c9cc
KM		 855static struct platform_device fsi_hdmi_device = {
856 .name = "sh_fsi2_b_hdmi",
857};
858
640dcfa0
GL		 859static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
860 unsigned long *parent_freq)
861{
862 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
863 long error;
864
865 if (IS_ERR(hdmi_ick)) {
866 int ret = PTR_ERR(hdmi_ick);
867 pr_err("Cannot get HDMI ICK: %d\n", ret);
868 return ret;
869 }
870
871 error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
872
873 clk_put(hdmi_ick);
874
875 return error;
876}
877
2863e935
AH		 878static struct gpio_led ap4evb_leds[] = {
879 {
880 .name = "led4",
881 .gpio = GPIO_PORT185,
882 .default_state = LEDS_GPIO_DEFSTATE_ON,
883 },
884 {
885 .name = "led2",
886 .gpio = GPIO_PORT186,
887 .default_state = LEDS_GPIO_DEFSTATE_ON,
888 },
889 {
890 .name = "led3",
891 .gpio = GPIO_PORT187,
892 .default_state = LEDS_GPIO_DEFSTATE_ON,
893 },
894 {
895 .name = "led1",
896 .gpio = GPIO_PORT188,
897 .default_state = LEDS_GPIO_DEFSTATE_ON,
898 }
899};
900
901static struct gpio_led_platform_data ap4evb_leds_pdata = {
902 .num_leds = ARRAY_SIZE(ap4evb_leds),
8050fbf2 903 .leds = ap4evb_leds,
2863e935
AH		 904};
905
906static struct platform_device leds_device = {
907 .name = "leds-gpio",
908 .id = 0,
909 .dev = {
910 .platform_data = &ap4evb_leds_pdata,
911 },
912};
913
1a0b1eac
GL		 914static struct i2c_board_info imx074_info = {
915 I2C_BOARD_INFO("imx074", 0x1a),
916};
917
4d4d6fbb 918static struct soc_camera_link imx074_link = {
1a0b1eac
GL		 919 .bus_id = 0,
920 .board_info = &imx074_info,
921 .i2c_adapter_id = 0,
922 .module_name = "imx074",
923};
924
925static struct platform_device ap4evb_camera = {
926 .name = "soc-camera-pdrv",
927 .id = 0,
928 .dev = {
929 .platform_data = &imx074_link,
930 },
931};
932
933static struct sh_csi2_client_config csi2_clients[] = {
934 {
935 .phy = SH_CSI2_PHY_MAIN,
936 .lanes = 3,
937 .channel = 0,
938 .pdev = &ap4evb_camera,
939 },
940};
941
942static struct sh_csi2_pdata csi2_info = {
943 .type = SH_CSI2C,
944 .clients = csi2_clients,
945 .num_clients = ARRAY_SIZE(csi2_clients),
946 .flags = SH_CSI2_ECC | SH_CSI2_CRC,
947};
948
949static struct resource csi2_resources[] = {
950 [0] = {
951 .name = "CSI2",
952 .start = 0xffc90000,
953 .end = 0xffc90fff,
954 .flags = IORESOURCE_MEM,
955 },
956 [1] = {
957 .start = intcs_evt2irq(0x17a0),
958 .flags = IORESOURCE_IRQ,
959 },
960};
961
6b526fed
GL		 962static struct sh_mobile_ceu_companion csi2 = {
963 .id = 0,
1a0b1eac
GL		 964 .num_resources = ARRAY_SIZE(csi2_resources),
965 .resource = csi2_resources,
6b526fed 966 .platform_data = &csi2_info,
1a0b1eac
GL		 967};
968
969static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
970 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
6b526fed 971 .csi2 = &csi2,
1a0b1eac
GL		 972};
973
974static struct resource ceu_resources[] = {
975 [0] = {
976 .name = "CEU",
977 .start = 0xfe910000,
978 .end = 0xfe91009f,
979 .flags = IORESOURCE_MEM,
980 },
981 [1] = {
982 .start = intcs_evt2irq(0x880),
983 .flags = IORESOURCE_IRQ,
984 },
985 [2] = {
986 /* place holder for contiguous memory */
987 },
988};
989
990static struct platform_device ceu_device = {
991 .name = "sh_mobile_ceu",
992 .id = 0, /* "ceu0" clock */
993 .num_resources = ARRAY_SIZE(ceu_resources),
994 .resource = ceu_resources,
995 .dev = {
05a5f01c
GL		 996 .platform_data = &sh_mobile_ceu_info,
997 .coherent_dma_mask = 0xffffffff,
1a0b1eac
GL		 998 },
999};
1000
2b7eda63 1001static struct platform_device *ap4evb_devices[] __initdata = {
2863e935 1002 &leds_device,
2b7eda63 1003 &nor_flash_device,
1b7e0677 1004 &smc911x_device,
3a14d039 1005 &sdhi0_device,
341291a6 1006 &sdhi1_device,
fb54d268 1007 &usb1_host_device,
cb9215e1 1008 &fsi_device,
c8d6bf9a 1009 &fsi_ak4643_device,
3f25c9cc 1010 &fsi_hdmi_device,
beccb12f 1011 &sh_mmcif_device,
dfbcdf64
GL		 1012 &lcdc1_device,
1013 &lcdc_device,
1014 &hdmi_device,
1a0b1eac
GL		 1015 &ceu_device,
1016 &ap4evb_camera,
1c7fcbed 1017 &meram_device,
2b7eda63
MD		 1018};
1019
2ce51f8b 1020static void __init hdmi_init_pm_clock(void)
dfbcdf64
GL		 1021{
1022 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
1023 int ret;
1024 long rate;
1025
1026 if (IS_ERR(hdmi_ick)) {
1027 ret = PTR_ERR(hdmi_ick);
1028 pr_err("Cannot get HDMI ICK: %d\n", ret);
1029 goto out;
1030 }
1031
685e4080 1032 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
dfbcdf64 1033 if (ret < 0) {
685e4080 1034 pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
dfbcdf64
GL		 1035 goto out;
1036 }
1037
685e4080 1038 pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
dfbcdf64 1039
685e4080 1040 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
dfbcdf64
GL		 1041 if (rate < 0) {
1042 pr_err("Cannot get suitable rate: %ld\n", rate);
1043 ret = rate;
1044 goto out;
1045 }
1046
685e4080 1047 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
dfbcdf64
GL		 1048 if (ret < 0) {
1049 pr_err("Cannot set rate %ld: %d\n", rate, ret);
1050 goto out;
1051 }
1052
1053 pr_debug("PLLC2 set frequency %lu\n", rate);
1054
685e4080 1055 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
2ce51f8b 1056 if (ret < 0)
dfbcdf64 1057 pr_err("Cannot set HDMI parent: %d\n", ret);
dfbcdf64
GL		 1058
1059out:
1060 if (!IS_ERR(hdmi_ick))
1061 clk_put(hdmi_ick);
dfbcdf64
GL		 1062}
1063
6084c81e 1064static void __init fsi_init_pm_clock(void)
69ce8aa4
KM		 1065{
1066 struct clk *fsia_ick;
1067 int ret;
1068
69ce8aa4
KM		 1069 fsia_ick = clk_get(&fsi_device.dev, "icka");
1070 if (IS_ERR(fsia_ick)) {
1071 ret = PTR_ERR(fsia_ick);
1072 pr_err("Cannot get FSI ICK: %d\n", ret);
6084c81e 1073 return;
69ce8aa4
KM		 1074 }
1075
1076 ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk);
69ce8aa4 1077 if (ret < 0)
22de4e1f 1078 pr_err("Cannot set FSI-A parent: %d\n", ret);
69ce8aa4 1079
69ce8aa4 1080 clk_put(fsia_ick);
69ce8aa4 1081}
69ce8aa4 1082
71c3ba9a
KM		 1083/*
1084 * FIXME !!
1085 *
1086 * gpio_no_direction
71c3ba9a
KM		 1087 * are quick_hack.
1088 *
1089 * current gpio frame work doesn't have
1090 * the method to control only pull up/down/free.
1091 * this function should be replaced by correct gpio function
1092 */
1093static void __init gpio_no_direction(u32 addr)
1094{
1095 __raw_writeb(0x00, addr);
1096}
1097
9fa1b7fe 1098/* TouchScreen */
52d5ac00
KM		 1099#ifdef CONFIG_AP4EVB_QHD
1100# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
1101# define GPIO_TSC_PORT GPIO_PORT123
1102#else /* WVGA */
1103# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
1104# define GPIO_TSC_PORT GPIO_PORT40
1105#endif
1106
33c9607a 1107#define IRQ28 evt2irq(0x3380) /* IRQ28A */
9fa1b7fe 1108#define IRQ7 evt2irq(0x02e0) /* IRQ7A */
71c3ba9a
KM		 1109static int ts_get_pendown_state(void)
1110{
52d5ac00 1111 int val;
71c3ba9a 1112
52d5ac00 1113 gpio_free(GPIO_TSC_IRQ);
71c3ba9a 1114
52d5ac00 1115 gpio_request(GPIO_TSC_PORT, NULL);
71c3ba9a 1116
52d5ac00 1117 gpio_direction_input(GPIO_TSC_PORT);
71c3ba9a 1118
52d5ac00 1119 val = gpio_get_value(GPIO_TSC_PORT);
71c3ba9a 1120
52d5ac00 1121 gpio_request(GPIO_TSC_IRQ, NULL);
71c3ba9a 1122
52d5ac00 1123 return !val;
71c3ba9a
KM		 1124}
1125
71c3ba9a
KM		 1126static int ts_init(void)
1127{
52d5ac00 1128 gpio_request(GPIO_TSC_IRQ, NULL);
71c3ba9a
KM		 1129
1130 return 0;
1131}
1132
bb04e197 1133static struct tsc2007_platform_data tsc2007_info = {
91cf5082
KM		 1134 .model = 2007,
1135 .x_plate_ohms = 180,
71c3ba9a
KM		 1136 .get_pendown_state = ts_get_pendown_state,
1137 .init_platform_hw = ts_init,
91cf5082
KM		 1138};
1139
9fa1b7fe
KM		 1140static struct i2c_board_info tsc_device = {
1141 I2C_BOARD_INFO("tsc2007", 0x48),
1142 .type = "tsc2007",
1143 .platform_data = &tsc2007_info,
1144 /*.irq is selected on ap4evb_init */
1145};
1146
91cf5082 1147/* I2C */
cb9215e1
KM		 1148static struct i2c_board_info i2c0_devices[] = {
1149 {
1150 I2C_BOARD_INFO("ak4643", 0x13),
1151 },
1152};
1153
91cf5082 1154static struct i2c_board_info i2c1_devices[] = {
8fc883c2
KM		 1155 {
1156 I2C_BOARD_INFO("r2025sd", 0x32),
1157 },
91cf5082
KM		 1158};
1159
2b7eda63
MD		 1160static struct map_desc ap4evb_io_desc[] __initdata = {
1161 /* create a 1:1 entity map for 0xe6xxxxxx
1162 * used by CPGA, INTC and PFC.
1163 */
1164 {
1165 .virtual = 0xe6000000,
1166 .pfn = __phys_to_pfn(0xe6000000),
1167 .length = 256 << 20,
1168 .type = MT_DEVICE_NONSHARED
1169 },
1170};
1171
1172static void __init ap4evb_map_io(void)
1173{
1174 iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc));
9b742024
JM		 1175 /* DMA memory at 0xf6000000 - 0xffdfffff */
1176 init_consistent_dma_size(158 << 20);
2b7eda63 1177
495b3cea 1178 /* setup early devices and console here as well */
2b7eda63 1179 sh7372_add_early_devices();
4ae04acb 1180 shmobile_setup_console();
2b7eda63
MD		 1181}
1182
cb9215e1
KM		 1183#define GPIO_PORT9CR 0xE6051009
1184#define GPIO_PORT10CR 0xE605100A
2669efec 1185#define USCCR1 0xE6058144
2b7eda63
MD		 1186static void __init ap4evb_init(void)
1187{
dfbcdf64 1188 u32 srcr4;
cb9215e1
KM		 1189 struct clk *clk;
1190
1b7e0677
KM		 1191 sh7372_pinmux_init();
1192
b228b48e
KM		 1193 /* enable SCIFA0 */
1194 gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
1195 gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
1196
1b7e0677
KM		 1197 /* enable SMSC911X */
1198 gpio_request(GPIO_FN_CS5A, NULL);
1199 gpio_request(GPIO_FN_IRQ6_39, NULL);
1200
8cb3a2eb
KM		 1201 /* enable Debug switch (S6) */
1202 gpio_request(GPIO_PORT32, NULL);
1203 gpio_request(GPIO_PORT33, NULL);
1204 gpio_request(GPIO_PORT34, NULL);
1205 gpio_request(GPIO_PORT35, NULL);
1206 gpio_direction_input(GPIO_PORT32);
1207 gpio_direction_input(GPIO_PORT33);
1208 gpio_direction_input(GPIO_PORT34);
1209 gpio_direction_input(GPIO_PORT35);
1210 gpio_export(GPIO_PORT32, 0);
1211 gpio_export(GPIO_PORT33, 0);
1212 gpio_export(GPIO_PORT34, 0);
1213 gpio_export(GPIO_PORT35, 0);
1214
3a14d039
MD		 1215 /* SDHI0 */
1216 gpio_request(GPIO_FN_SDHICD0, NULL);
1217 gpio_request(GPIO_FN_SDHIWP0, NULL);
1218 gpio_request(GPIO_FN_SDHICMD0, NULL);
1219 gpio_request(GPIO_FN_SDHICLK0, NULL);
1220 gpio_request(GPIO_FN_SDHID0_3, NULL);
1221 gpio_request(GPIO_FN_SDHID0_2, NULL);
1222 gpio_request(GPIO_FN_SDHID0_1, NULL);
1223 gpio_request(GPIO_FN_SDHID0_0, NULL);
1224
9fa1b7fe
KM		 1225 /* SDHI1 */
1226 gpio_request(GPIO_FN_SDHICMD1, NULL);
1227 gpio_request(GPIO_FN_SDHICLK1, NULL);
1228 gpio_request(GPIO_FN_SDHID1_3, NULL);
1229 gpio_request(GPIO_FN_SDHID1_2, NULL);
1230 gpio_request(GPIO_FN_SDHID1_1, NULL);
1231 gpio_request(GPIO_FN_SDHID1_0, NULL);
91cf5082 1232
c8ee3d4b
KM		 1233 /* MMCIF */
1234 gpio_request(GPIO_FN_MMCD0_0, NULL);
1235 gpio_request(GPIO_FN_MMCD0_1, NULL);
1236 gpio_request(GPIO_FN_MMCD0_2, NULL);
1237 gpio_request(GPIO_FN_MMCD0_3, NULL);
1238 gpio_request(GPIO_FN_MMCD0_4, NULL);
1239 gpio_request(GPIO_FN_MMCD0_5, NULL);
1240 gpio_request(GPIO_FN_MMCD0_6, NULL);
1241 gpio_request(GPIO_FN_MMCD0_7, NULL);
1242 gpio_request(GPIO_FN_MMCCMD0, NULL);
1243 gpio_request(GPIO_FN_MMCCLK0, NULL);
1244
fb54d268
KM		 1245 /* USB enable */
1246 gpio_request(GPIO_FN_VBUS0_1, NULL);
1247 gpio_request(GPIO_FN_IDIN_1_18, NULL);
1248 gpio_request(GPIO_FN_PWEN_1_115, NULL);
1249 gpio_request(GPIO_FN_OVCN_1_114, NULL);
1250 gpio_request(GPIO_FN_EXTLP_1, NULL);
1251 gpio_request(GPIO_FN_OVCN2_1, NULL);
1252
1253 /* setup USB phy */
d0fb0c4b 1254 __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */
fb54d268 1255
2669efec 1256 /* enable FSI2 port A (ak4643) */
cb9215e1
KM		 1257 gpio_request(GPIO_FN_FSIAIBT, NULL);
1258 gpio_request(GPIO_FN_FSIAILR, NULL);
1259 gpio_request(GPIO_FN_FSIAISLD, NULL);
1260 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1261 gpio_request(GPIO_PORT161, NULL);
1262 gpio_direction_output(GPIO_PORT161, 0); /* slave */
1263
1264 gpio_request(GPIO_PORT9, NULL);
1265 gpio_request(GPIO_PORT10, NULL);
1266 gpio_no_direction(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1267 gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
1268
68accd73
AH		 1269 /* card detect pin for MMC slot (CN7) */
1270 gpio_request(GPIO_PORT41, NULL);
1271 gpio_direction_input(GPIO_PORT41);
1272
2669efec
KM		 1273 /* setup FSI2 port B (HDMI) */
1274 gpio_request(GPIO_FN_FSIBCK, NULL);
1275 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
1276
cb9215e1
KM		 1277 /* set SPU2 clock to 119.6 MHz */
1278 clk = clk_get(NULL, "spu_clk");
2ae2b766 1279 if (!IS_ERR(clk)) {
cb9215e1
KM		 1280 clk_set_rate(clk, clk_round_rate(clk, 119600000));
1281 clk_put(clk);
1282 }
1283
cb9215e1
KM		 1284 /*
1285 * set irq priority, to avoid sound chopping
1286 * when NFS rootfs is used
1287 * FSI(3) > SMSC911X(2)
1288 */
1289 intc_set_priority(IRQ_FSI, 3);
1290
1291 i2c_register_board_info(0, i2c0_devices,
1292 ARRAY_SIZE(i2c0_devices));
1293
1294 i2c_register_board_info(1, i2c1_devices,
1295 ARRAY_SIZE(i2c1_devices));
1296
9fa1b7fe 1297#ifdef CONFIG_AP4EVB_QHD
dd8a61a7 1298
9fa1b7fe 1299 /*
dd8a61a7
MD		 1300 * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
1301 * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
9fa1b7fe
KM		 1302 */
1303
1304 /* enable KEYSC */
1305 gpio_request(GPIO_FN_KEYOUT0, NULL);
1306 gpio_request(GPIO_FN_KEYOUT1, NULL);
1307 gpio_request(GPIO_FN_KEYOUT2, NULL);
1308 gpio_request(GPIO_FN_KEYOUT3, NULL);
1309 gpio_request(GPIO_FN_KEYOUT4, NULL);
1310 gpio_request(GPIO_FN_KEYIN0_136, NULL);
1311 gpio_request(GPIO_FN_KEYIN1_135, NULL);
1312 gpio_request(GPIO_FN_KEYIN2_134, NULL);
1313 gpio_request(GPIO_FN_KEYIN3_133, NULL);
1314 gpio_request(GPIO_FN_KEYIN4, NULL);
1315
1316 /* enable TouchScreen */
6845664a 1317 irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
9fa1b7fe
KM		 1318
1319 tsc_device.irq = IRQ28;
1320 i2c_register_board_info(1, &tsc_device, 1);
1321
1322 /* LCDC0 */
1323 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
1324 lcdc_info.ch[0].interface_type = RGB24;
1325 lcdc_info.ch[0].clock_divider = 1;
1326 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
9fa1b7fe
KM		 1327 lcdc_info.ch[0].lcd_size_cfg.width = 44;
1328 lcdc_info.ch[0].lcd_size_cfg.height = 79;
1329
1330 platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
1331
1332#else
1333 /*
dd8a61a7
MD		 1334 * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
1335 * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
9fa1b7fe 1336 */
dd8a61a7 1337
9fa1b7fe
KM		 1338 gpio_request(GPIO_FN_LCDD17, NULL);
1339 gpio_request(GPIO_FN_LCDD16, NULL);
1340 gpio_request(GPIO_FN_LCDD15, NULL);
1341 gpio_request(GPIO_FN_LCDD14, NULL);
1342 gpio_request(GPIO_FN_LCDD13, NULL);
1343 gpio_request(GPIO_FN_LCDD12, NULL);
1344 gpio_request(GPIO_FN_LCDD11, NULL);
1345 gpio_request(GPIO_FN_LCDD10, NULL);
1346 gpio_request(GPIO_FN_LCDD9, NULL);
1347 gpio_request(GPIO_FN_LCDD8, NULL);
1348 gpio_request(GPIO_FN_LCDD7, NULL);
1349 gpio_request(GPIO_FN_LCDD6, NULL);
1350 gpio_request(GPIO_FN_LCDD5, NULL);
1351 gpio_request(GPIO_FN_LCDD4, NULL);
1352 gpio_request(GPIO_FN_LCDD3, NULL);
1353 gpio_request(GPIO_FN_LCDD2, NULL);
1354 gpio_request(GPIO_FN_LCDD1, NULL);
1355 gpio_request(GPIO_FN_LCDD0, NULL);
1356 gpio_request(GPIO_FN_LCDDISP, NULL);
1357 gpio_request(GPIO_FN_LCDDCK, NULL);
1358
1359 gpio_request(GPIO_PORT189, NULL); /* backlight */
1360 gpio_direction_output(GPIO_PORT189, 1);
1361
1362 gpio_request(GPIO_PORT151, NULL); /* LCDDON */
1363 gpio_direction_output(GPIO_PORT151, 1);
1364
1365 lcdc_info.clock_source = LCDC_CLK_BUS;
1366 lcdc_info.ch[0].interface_type = RGB18;
f60cb470 1367 lcdc_info.ch[0].clock_divider = 3;
9fa1b7fe 1368 lcdc_info.ch[0].flags = 0;
9fa1b7fe
KM		 1369 lcdc_info.ch[0].lcd_size_cfg.width = 152;
1370 lcdc_info.ch[0].lcd_size_cfg.height = 91;
1371
1372 /* enable TouchScreen */
6845664a 1373 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
9fa1b7fe
KM		 1374
1375 tsc_device.irq = IRQ7;
1376 i2c_register_board_info(0, &tsc_device, 1);
1377#endif /* CONFIG_AP4EVB_QHD */
341291a6 1378
1a0b1eac
GL		 1379 /* CEU */
1380
1381 /*
1382 * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
1383 * becomes available
1384 */
1385
1386 /* MIPI-CSI stuff */
1387 gpio_request(GPIO_FN_VIO_CKO, NULL);
1388
1389 clk = clk_get(NULL, "vck1_clk");
1390 if (!IS_ERR(clk)) {
1391 clk_set_rate(clk, clk_round_rate(clk, 13000000));
1392 clk_enable(clk);
1393 clk_put(clk);
1394 }
1395
2b7eda63
MD		 1396 sh7372_add_standard_devices();
1397
dfbcdf64
GL		 1398 /* HDMI */
1399 gpio_request(GPIO_FN_HDMI_HPD, NULL);
1400 gpio_request(GPIO_FN_HDMI_CEC, NULL);
1401
1402 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
1403#define SRCR4 0xe61580bc
1404 srcr4 = __raw_readl(SRCR4);
1405 __raw_writel(srcr4 | (1 << 13), SRCR4);
1406 udelay(50);
1407 __raw_writel(srcr4 & ~(1 << 13), SRCR4);
1408
2b7eda63 1409 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
2ce51f8b 1410
96f7934e
MD		 1411 sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc1_device);
1412 sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
c1ba5bb5 1413 sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
96f7934e 1414
d93f5cde
MD		 1415 sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
1416 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
1417 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
382414b9 1418 sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
d93f5cde 1419
2ce51f8b 1420 hdmi_init_pm_clock();
6084c81e 1421 fsi_init_pm_clock();
97991657 1422 sh7372_pm_init();
a41b6466 1423 pm_clk_add(&fsi_device.dev, "spu2");
d0168fdc 1424 pm_clk_add(&lcdc1_device.dev, "hdmi");
2b7eda63
MD		 1425}
1426
495b3cea
MD		 1427static void __init ap4evb_timer_init(void)
1428{
1429 sh7372_clock_init();
1430 shmobile_timer.init();
dfbcdf64
GL		 1431
1432 /* External clock source */
685e4080 1433 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
495b3cea
MD		 1434}
1435
1436static struct sys_timer ap4evb_timer = {
1437 .init = ap4evb_timer_init,
1438};
1439
2b7eda63 1440MACHINE_START(AP4EVB, "ap4evb")
2b7eda63
MD		 1441 .map_io = ap4evb_map_io,
1442 .init_irq = sh7372_init_irq,
863b1719 1443 .handle_irq = shmobile_handle_irq_intc,
2b7eda63 1444 .init_machine = ap4evb_init,
495b3cea 1445 .timer = &ap4evb_timer,
2b7eda63 1446MACHINE_END
Linux kernel - Deliverables
This page took 0.164321 seconds and 5 git commands to generate.