[deliverable/linux.git] / arch / arm / mach-shmobile / board-bonito.c

/*
 * bonito board support
 *
 * Copyright (C) 2011 Renesas Solutions Corp.
 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 *
 */

#include <linux/kernel.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
#include <linux/videodev2.h>
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/r8a7740.h>
#include <mach/irqs.h>
#include <video/sh_mobile_lcdc.h>

/*
 * CS	Address		device			note
 *----------------------------------------------------------------
 * 0	0x0000_0000	NOR Flash (64MB)	SW12 : bit3 = OFF
 * 2	0x0800_0000	ExtNOR (64MB)		SW12 : bit3 = OFF
 * 4			-
 * 5A			-
 * 5B	0x1600_0000	SRAM (8MB)
 * 6	0x1800_0000	FPGA (64K)
 *	0x1801_0000	Ether (4KB)
 *	0x1801_1000	USB (4KB)
 */

/*
 * SW12
 *
 *	bit1			bit2			bit3
 *----------------------------------------------------------------------------
 * ON	NOR WriteProtect	NAND WriteProtect	CS0 ExtNOR / CS2 NOR
 * OFF	NOR Not WriteProtect	NAND Not WriteProtect	CS0 NOR    / CS2 ExtNOR
 */

/*
 * SCIFA5 (CN42)
 *
 * S38.3 = ON
 * S39.6 = ON
 * S43.1 = ON
 */

/*
 * LCDC0 (CN3/CN4/CN7)
 *
 * S38.1 = OFF
 * S38.2 = OFF
 */

/* Dummy supplies, where voltage doesn't matter */
static struct regulator_consumer_supply dummy_supplies[] = {
	REGULATOR_SUPPLY("vddvario", "smsc911x"),
	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
};

/*
 * FPGA
 */
#define IRQSR0		0x0020
#define IRQSR1		0x0022
#define IRQMR0		0x0030
#define IRQMR1		0x0032
#define BUSSWMR1	0x0070
#define BUSSWMR2	0x0072
#define BUSSWMR3	0x0074
#define BUSSWMR4	0x0076

#define LCDCR		0x10B4
#define DEVRSTCR1	0x10D0
#define DEVRSTCR2	0x10D2
#define A1MDSR		0x10E0
#define BVERR		0x1100

/* FPGA IRQ */
#define FPGA_IRQ_BASE		(512)
#define FPGA_IRQ0		(FPGA_IRQ_BASE)
#define FPGA_IRQ1		(FPGA_IRQ_BASE + 16)
#define FPGA_ETH_IRQ		(FPGA_IRQ0 + 15)
static u16 bonito_fpga_read(u32 offset)
{
	return __raw_readw(IOMEM(0xf0003000) + offset);
}

static void bonito_fpga_write(u32 offset, u16 val)
{
	__raw_writew(val, IOMEM(0xf0003000) + offset);
}

static void bonito_fpga_irq_disable(struct irq_data *data)
{
	unsigned int irq = data->irq;
	u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
	int shift = irq % 16;

	bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
}

static void bonito_fpga_irq_enable(struct irq_data *data)
{
	unsigned int irq = data->irq;
	u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
	int shift = irq % 16;

	bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
}

static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
	.name		= "bonito FPGA",
	.irq_mask	= bonito_fpga_irq_disable,
	.irq_unmask	= bonito_fpga_irq_enable,
};

static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	u32 val =  bonito_fpga_read(IRQSR1) << 16 |
		   bonito_fpga_read(IRQSR0);
	u32 mask = bonito_fpga_read(IRQMR1) << 16 |
		   bonito_fpga_read(IRQMR0);

	int i;

	val &= ~mask;

	for (i = 0; i < 32; i++) {
		if (!(val & (1 << i)))
			continue;

		generic_handle_irq(FPGA_IRQ_BASE + i);
	}
}

static void bonito_fpga_init(void)
{
	int i;

	bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
	bonito_fpga_write(IRQMR1, 0xffff); /* mask all */

	/* Device reset */
	bonito_fpga_write(DEVRSTCR1,
		   (1 << 2));	/* Eth */

	/* FPGA irq require special handling */
	for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
		irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
					      handle_level_irq, "level");
		set_irq_flags(i, IRQF_VALID); /* yuck */
	}

	irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
	irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
}

/*
* PMIC settings
*
* FIXME
*
* bonito board needs some settings by pmic which use i2c access.
* pmic settings use device_initcall() here for use it.
*/
static __u8 *pmic_settings = NULL;
static __u8 pmic_do_2A[] = {
	0x1C, 0x09,
	0x1A, 0x80,
	0xff, 0xff,
};

static int __init pmic_init(void)
{
	struct i2c_adapter *a = i2c_get_adapter(0);
	struct i2c_msg msg;
	__u8 buf[2];
	int i, ret;

	if (!pmic_settings)
		return 0;
	if (!a)
		return 0;

	msg.addr	= 0x46;
	msg.buf		= buf;
	msg.len		= 2;
	msg.flags	= 0;

	for (i = 0; ; i += 2) {
		buf[0] = pmic_settings[i + 0];
		buf[1] = pmic_settings[i + 1];

		if ((0xff == buf[0]) && (0xff == buf[1]))
			break;

		ret = i2c_transfer(a, &msg, 1);
		if (ret < 0) {
			pr_err("i2c transfer fail\n");
			break;
		}
	}

	return 0;
}
device_initcall(pmic_init);

/*
 * LCDC0
 */
static const struct fb_videomode lcdc0_mode = {
	.name		= "WVGA Panel",
	.xres		= 800,
	.yres		= 480,
	.left_margin	= 88,
	.right_margin	= 40,
	.hsync_len	= 128,
	.upper_margin	= 20,
	.lower_margin	= 5,
	.vsync_len	= 5,
	.sync		= 0,
};

static struct sh_mobile_lcdc_info lcdc0_info = {
	.clock_source	= LCDC_CLK_BUS,
	.ch[0] = {
		.chan			= LCDC_CHAN_MAINLCD,
		.fourcc = V4L2_PIX_FMT_RGB565,
		.interface_type		= RGB24,
		.clock_divider		= 5,
		.flags			= 0,
		.lcd_modes		= &lcdc0_mode,
		.num_modes		= 1,
		.panel_cfg = {
			.width	= 152,
			.height = 91,
		},
	},
};

static struct resource lcdc0_resources[] = {
	[0] = {
		.name	= "LCDC0",
		.start	= 0xfe940000,
		.end	= 0xfe943fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= intcs_evt2irq(0x0580),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device lcdc0_device = {
	.name		= "sh_mobile_lcdc_fb",
	.id		= 0,
	.resource	= lcdc0_resources,
	.num_resources	= ARRAY_SIZE(lcdc0_resources),
	.dev	= {
		.platform_data	= &lcdc0_info,
		.coherent_dma_mask = ~0,
	},
};

/*
 * SMSC 9221
 */
static struct resource smsc_resources[] = {
	[0] = {
		.start		= 0x18010000,
		.end		= 0x18011000 - 1,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
		.start		= FPGA_ETH_IRQ,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct smsc911x_platform_config smsc_platdata = {
	.flags		= SMSC911X_USE_16BIT,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
};

static struct platform_device smsc_device = {
	.name		= "smsc911x",
	.dev  = {
		.platform_data = &smsc_platdata,
	},
	.resource	= smsc_resources,
	.num_resources	= ARRAY_SIZE(smsc_resources),
};

/*
 * core board devices
 */
static struct platform_device *bonito_core_devices[] __initdata = {
};

/*
 * base board devices
 */
static struct platform_device *bonito_base_devices[] __initdata = {
	&lcdc0_device,
	&smsc_device,
};

/*
 * map I/O
 */
static struct map_desc bonito_io_desc[] __initdata = {
	/*
	 * for FPGA (0x1800000-0x19ffffff)
	 * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
	 */
	{
		.virtual	= 0xf0003000,
		.pfn		= __phys_to_pfn(0x18000000),
		.length		= PAGE_SIZE * 2,
		.type		= MT_DEVICE_NONSHARED
	}
};

static void __init bonito_map_io(void)
{
	r8a7740_map_io();
	iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
}

/*
 * board init
 */
#define BIT_ON(sw, bit)		(sw & (1 << bit))
#define BIT_OFF(sw, bit)	(!(sw & (1 << bit)))

#define VCCQ1CR		IOMEM(0xE6058140)
#define VCCQ1LCDCR	IOMEM(0xE6058186)

static void __init bonito_init(void)
{
	u16 val;

	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));

	r8a7740_pinmux_init();
	bonito_fpga_init();

	pmic_settings = pmic_do_2A;

	/*
	 * core board settings
	 */

#ifdef CONFIG_CACHE_L2X0
	/* Early BRESP enable, Shared attribute override enable, 32K*8way */
	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
#endif

	r8a7740_add_standard_devices();

	platform_add_devices(bonito_core_devices,
			     ARRAY_SIZE(bonito_core_devices));

	/*
	 * base board settings
	 */
	gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL);
	if (!gpio_get_value(GPIO_PORT176)) {
		u16 bsw2;
		u16 bsw3;
		u16 bsw4;

		/*
		 * FPGA
		 */
		gpio_request(GPIO_FN_CS5B,		NULL);
		gpio_request(GPIO_FN_CS6A,		NULL);
		gpio_request(GPIO_FN_CS5A_PORT105,	NULL);
		gpio_request(GPIO_FN_IRQ10,		NULL);

		val = bonito_fpga_read(BVERR);
		pr_info("bonito version: cpu %02x, base %02x\n",
			((val >> 8) & 0xFF),
			((val >> 0) & 0xFF));

		bsw2 = bonito_fpga_read(BUSSWMR2);
		bsw3 = bonito_fpga_read(BUSSWMR3);
		bsw4 = bonito_fpga_read(BUSSWMR4);

		/*
		 * SCIFA5 (CN42)
		 */
		if (BIT_OFF(bsw2, 1) &&	/* S38.3 = ON */
		    BIT_OFF(bsw3, 9) &&	/* S39.6 = ON */
		    BIT_OFF(bsw4, 4)) {	/* S43.1 = ON */
			gpio_request(GPIO_FN_SCIFA5_TXD_PORT91,	NULL);
			gpio_request(GPIO_FN_SCIFA5_RXD_PORT92,	NULL);
		}

		/*
		 * LCDC0 (CN3)
		 */
		if (BIT_ON(bsw2, 3) &&	/* S38.1 = OFF */
		    BIT_ON(bsw2, 2)) {	/* S38.2 = OFF */
			gpio_request(GPIO_FN_LCDC0_SELECT,	NULL);
			gpio_request(GPIO_FN_LCD0_D0,		NULL);
			gpio_request(GPIO_FN_LCD0_D1,		NULL);
			gpio_request(GPIO_FN_LCD0_D2,		NULL);
			gpio_request(GPIO_FN_LCD0_D3,		NULL);
			gpio_request(GPIO_FN_LCD0_D4,		NULL);
			gpio_request(GPIO_FN_LCD0_D5,		NULL);
			gpio_request(GPIO_FN_LCD0_D6,		NULL);
			gpio_request(GPIO_FN_LCD0_D7,		NULL);
			gpio_request(GPIO_FN_LCD0_D8,		NULL);
			gpio_request(GPIO_FN_LCD0_D9,		NULL);
			gpio_request(GPIO_FN_LCD0_D10,		NULL);
			gpio_request(GPIO_FN_LCD0_D11,		NULL);
			gpio_request(GPIO_FN_LCD0_D12,		NULL);
			gpio_request(GPIO_FN_LCD0_D13,		NULL);
			gpio_request(GPIO_FN_LCD0_D14,		NULL);
			gpio_request(GPIO_FN_LCD0_D15,		NULL);
			gpio_request(GPIO_FN_LCD0_D16,		NULL);
			gpio_request(GPIO_FN_LCD0_D17,		NULL);
			gpio_request(GPIO_FN_LCD0_D18_PORT163,	NULL);
			gpio_request(GPIO_FN_LCD0_D19_PORT162,	NULL);
			gpio_request(GPIO_FN_LCD0_D20_PORT161,	NULL);
			gpio_request(GPIO_FN_LCD0_D21_PORT158,	NULL);
			gpio_request(GPIO_FN_LCD0_D22_PORT160,	NULL);
			gpio_request(GPIO_FN_LCD0_D23_PORT159,	NULL);
			gpio_request(GPIO_FN_LCD0_DCK,		NULL);
			gpio_request(GPIO_FN_LCD0_VSYN,		NULL);
			gpio_request(GPIO_FN_LCD0_HSYN,		NULL);
			gpio_request(GPIO_FN_LCD0_DISP,		NULL);
			gpio_request(GPIO_FN_LCD0_LCLK_PORT165,	NULL);

			gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
					 NULL); /* LCDDON */

			/* backlight on */
			bonito_fpga_write(LCDCR, 1);

			/*  drivability Max */
			__raw_writew(0x00FF , VCCQ1LCDCR);
			__raw_writew(0xFFFF , VCCQ1CR);
		}

		platform_add_devices(bonito_base_devices,
				     ARRAY_SIZE(bonito_base_devices));
	}
}

static void __init bonito_earlytimer_init(void)
{
	u16 val;
	u8 md_ck = 0;

	/* read MD_CK value */
	val = bonito_fpga_read(A1MDSR);
	if (val & (1 << 10))
		md_ck |= MD_CK2;
	if (val & (1 << 9))
		md_ck |= MD_CK1;
	if (val & (1 << 8))
		md_ck |= MD_CK0;

	r8a7740_clock_init(md_ck);
	shmobile_earlytimer_init();
}

static void __init bonito_add_early_devices(void)
{
	r8a7740_add_early_devices();
}

MACHINE_START(BONITO, "bonito")
	.map_io		= bonito_map_io,
	.init_early	= bonito_add_early_devices,
	.init_irq	= r8a7740_init_irq,
	.handle_irq	= shmobile_handle_irq_intc,
	.init_machine	= bonito_init,
	.init_late	= shmobile_init_late,
	.init_time	= bonito_earlytimer_init,
MACHINE_END
Commit	Line	Data
d55c9a97 KM	1	/*
	2	* bonito board support
	3	*
	4	* Copyright (C) 2011 Renesas Solutions Corp.
	5	* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*
	20	*/
	21
	22	#include <linux/kernel.h>
e609b7cb	23	#include <linux/i2c.h>
d55c9a97 KM	24	#include <linux/init.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/irq.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/gpio.h>
d3ed18ea GL	29	#include <linux/regulator/fixed.h>
d3ed18ea GL	30	#include <linux/regulator/machine.h>
6bf2805d	31	#include <linux/smsc911x.h>
63d71126	32	#include <linux/videodev2.h>
d55c9a97 KM	33	#include <mach/common.h>
	34	#include <asm/mach-types.h>
	35	#include <asm/mach/arch.h>
	36	#include <asm/mach/map.h>
	37	#include <asm/mach/time.h>
	38	#include <asm/hardware/cache-l2x0.h>
	39	#include <mach/r8a7740.h>
250a2723	40	#include <mach/irqs.h>
665ccfa0	41	#include <video/sh_mobile_lcdc.h>
d55c9a97 KM	42
	43	/*
	44	* CS Address device note
	45	*----------------------------------------------------------------
	46	* 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
	47	* 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
	48	* 4 -
	49	* 5A -
	50	* 5B 0x1600_0000 SRAM (8MB)
	51	* 6 0x1800_0000 FPGA (64K)
	52	* 0x1801_0000 Ether (4KB)
	53	* 0x1801_1000 USB (4KB)
	54	*/
	55
	56	/*
	57	* SW12
	58	*
	59	* bit1 bit2 bit3
	60	*----------------------------------------------------------------------------
	61	* ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
	62	* OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
	63	*/
	64
b6b37e25 KM	65	/*
	66	* SCIFA5 (CN42)
	67	*
	68	* S38.3 = ON
	69	* S39.6 = ON
	70	* S43.1 = ON
	71	*/
	72
665ccfa0 KM	73	/*
	74	* LCDC0 (CN3/CN4/CN7)
	75	*
	76	* S38.1 = OFF
	77	* S38.2 = OFF
	78	*/
	79
d3ed18ea GL	80	/* Dummy supplies, where voltage doesn't matter */
	81	static struct regulator_consumer_supply dummy_supplies[] = {
	82	REGULATOR_SUPPLY("vddvario", "smsc911x"),
	83	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
	84	};
	85
d55c9a97 KM	86	/*
	87	* FPGA
	88	*/
6bf2805d KM	89	#define IRQSR0 0x0020
	90	#define IRQSR1 0x0022
	91	#define IRQMR0 0x0030
	92	#define IRQMR1 0x0032
b6b37e25 KM	93	#define BUSSWMR1 0x0070
	94	#define BUSSWMR2 0x0072
	95	#define BUSSWMR3 0x0074
	96	#define BUSSWMR4 0x0076
	97
665ccfa0	98	#define LCDCR 0x10B4
6bf2805d KM	99	#define DEVRSTCR1 0x10D0
6bf2805d KM	100	#define DEVRSTCR2 0x10D2
d55c9a97 KM	101	#define A1MDSR 0x10E0
d55c9a97 KM	102	#define BVERR 0x1100
6bf2805d KM	103
	104	/* FPGA IRQ */
	105	#define FPGA_IRQ_BASE (512)
	106	#define FPGA_IRQ0 (FPGA_IRQ_BASE)
	107	#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
8900df7a	108	#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
d55c9a97 KM	109	static u16 bonito_fpga_read(u32 offset)
d55c9a97 KM	110	{
0a4b04dc	111	return __raw_readw(IOMEM(0xf0003000) + offset);
d55c9a97 KM	112	}
	113
	114	static void bonito_fpga_write(u32 offset, u16 val)
	115	{
0a4b04dc	116	__raw_writew(val, IOMEM(0xf0003000) + offset);
d55c9a97 KM	117	}
d55c9a97 KM	118
6bf2805d KM	119	static void bonito_fpga_irq_disable(struct irq_data *data)
	120	{
	121	unsigned int irq = data->irq;
	122	u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
	123	int shift = irq % 16;
	124
	125	bonito_fpga_write(addr, bonito_fpga_read(addr) \| (1 << shift));
	126	}
	127
	128	static void bonito_fpga_irq_enable(struct irq_data *data)
	129	{
	130	unsigned int irq = data->irq;
	131	u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
	132	int shift = irq % 16;
	133
	134	bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
	135	}
	136
	137	static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
	138	.name = "bonito FPGA",
	139	.irq_mask = bonito_fpga_irq_disable,
	140	.irq_unmask = bonito_fpga_irq_enable,
	141	};
	142
	143	static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
	144	{
	145	u32 val = bonito_fpga_read(IRQSR1) << 16 \|
	146	bonito_fpga_read(IRQSR0);
	147	u32 mask = bonito_fpga_read(IRQMR1) << 16 \|
	148	bonito_fpga_read(IRQMR0);
	149
	150	int i;
	151
	152	val &= ~mask;
	153
	154	for (i = 0; i < 32; i++) {
	155	if (!(val & (1 << i)))
	156	continue;
	157
	158	generic_handle_irq(FPGA_IRQ_BASE + i);
	159	}
	160	}
	161
	162	static void bonito_fpga_init(void)
	163	{
	164	int i;
	165
	166	bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
	167	bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
	168
	169	/* Device reset */
	170	bonito_fpga_write(DEVRSTCR1,
	171	(1 << 2)); /* Eth */
	172
	173	/* FPGA irq require special handling */
	174	for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
	175	irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
	176	handle_level_irq, "level");
	177	set_irq_flags(i, IRQF_VALID); /* yuck */
	178	}
	179
	180	irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
	181	irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
	182	}
183
e609b7cb KM	184	/*
	185	* PMIC settings
	186	*
	187	* FIXME
	188	*
	189	* bonito board needs some settings by pmic which use i2c access.
	190	* pmic settings use device_initcall() here for use it.
	191	*/
	192	static __u8 *pmic_settings = NULL;
	193	static __u8 pmic_do_2A[] = {
	194	0x1C, 0x09,
	195	0x1A, 0x80,
	196	0xff, 0xff,
	197	};
	198
	199	static int __init pmic_init(void)
	200	{
	201	struct i2c_adapter *a = i2c_get_adapter(0);
	202	struct i2c_msg msg;
	203	__u8 buf[2];
	204	int i, ret;
	205
	206	if (!pmic_settings)
	207	return 0;
	208	if (!a)
	209	return 0;
	210
	211	msg.addr = 0x46;
	212	msg.buf = buf;
	213	msg.len = 2;
	214	msg.flags = 0;
	215
	216	for (i = 0; ; i += 2) {
	217	buf[0] = pmic_settings[i + 0];
	218	buf[1] = pmic_settings[i + 1];
	219
	220	if ((0xff == buf[0]) && (0xff == buf[1]))
	221	break;
	222
	223	ret = i2c_transfer(a, &msg, 1);
	224	if (ret < 0) {
	225	pr_err("i2c transfer fail\n");
	226	break;
	227	}
	228	}
	229
	230	return 0;
	231	}
	232	device_initcall(pmic_init);
	233
665ccfa0 KM	234	/*
	235	* LCDC0
	236	*/
	237	static const struct fb_videomode lcdc0_mode = {
	238	.name = "WVGA Panel",
	239	.xres = 800,
	240	.yres = 480,
	241	.left_margin = 88,
	242	.right_margin = 40,
	243	.hsync_len = 128,
	244	.upper_margin = 20,
	245	.lower_margin = 5,
	246	.vsync_len = 5,
	247	.sync = 0,
	248	};
	249
	250	static struct sh_mobile_lcdc_info lcdc0_info = {
	251	.clock_source = LCDC_CLK_BUS,
	252	.ch[0] = {
	253	.chan = LCDC_CHAN_MAINLCD,
63d71126	254	.fourcc = V4L2_PIX_FMT_RGB565,
665ccfa0 KM	255	.interface_type = RGB24,
	256	.clock_divider = 5,
	257	.flags = 0,
93ff2598 LP	258	.lcd_modes = &lcdc0_mode,
93ff2598 LP	259	.num_modes = 1,
afaad83b	260	.panel_cfg = {
665ccfa0 KM	261	.width = 152,
	262	.height = 91,
	263	},
	264	},
	265	};
	266
	267	static struct resource lcdc0_resources[] = {
	268	[0] = {
	269	.name = "LCDC0",
	270	.start = 0xfe940000,
	271	.end = 0xfe943fff,
	272	.flags = IORESOURCE_MEM,
	273	},
	274	[1] = {
	275	.start = intcs_evt2irq(0x0580),
	276	.flags = IORESOURCE_IRQ,
	277	},
	278	};
	279
	280	static struct platform_device lcdc0_device = {
	281	.name = "sh_mobile_lcdc_fb",
	282	.id = 0,
	283	.resource = lcdc0_resources,
	284	.num_resources = ARRAY_SIZE(lcdc0_resources),
	285	.dev = {
	286	.platform_data = &lcdc0_info,
	287	.coherent_dma_mask = ~0,
	288	},
	289	};
	290
8900df7a KM	291	/*
	292	* SMSC 9221
	293	*/
	294	static struct resource smsc_resources[] = {
	295	[0] = {
	296	.start = 0x18010000,
	297	.end = 0x18011000 - 1,
	298	.flags = IORESOURCE_MEM,
	299	},
	300	[1] = {
	301	.start = FPGA_ETH_IRQ,
	302	.flags = IORESOURCE_IRQ,
	303	},
	304	};
	305
	306	static struct smsc911x_platform_config smsc_platdata = {
	307	.flags = SMSC911X_USE_16BIT,
	308	.phy_interface = PHY_INTERFACE_MODE_MII,
	309	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	310	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	311	};
	312
	313	static struct platform_device smsc_device = {
	314	.name = "smsc911x",
	315	.dev = {
	316	.platform_data = &smsc_platdata,
	317	},
	318	.resource = smsc_resources,
	319	.num_resources = ARRAY_SIZE(smsc_resources),
	320	};
	321
d55c9a97	322	/*
b6b37e25	323	* core board devices
d55c9a97	324	*/
b6b37e25 KM	325	static struct platform_device *bonito_core_devices[] __initdata = {
	326	};
	327
	328	/*
	329	* base board devices
	330	*/
	331	static struct platform_device *bonito_base_devices[] __initdata = {
665ccfa0	332	&lcdc0_device,
8900df7a	333	&smsc_device,
d55c9a97 KM	334	};
	335
	336	/*
	337	* map I/O
	338	*/
	339	static struct map_desc bonito_io_desc[] __initdata = {
d55c9a97 KM	340	/*
	341	* for FPGA (0x1800000-0x19ffffff)
	342	* 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
	343	*/
	344	{
	345	.virtual = 0xf0003000,
	346	.pfn = __phys_to_pfn(0x18000000),
	347	.length = PAGE_SIZE * 2,
	348	.type = MT_DEVICE_NONSHARED
	349	}
	350	};
	351
	352	static void __init bonito_map_io(void)
	353	{
d3ab7221	354	r8a7740_map_io();
d55c9a97	355	iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
d55c9a97 KM	356	}
	357
	358	/*
	359	* board init
	360	*/
b6b37e25 KM	361	#define BIT_ON(sw, bit) (sw & (1 << bit))
	362	#define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
	363
0a4b04dc AB	364	#define VCCQ1CR IOMEM(0xE6058140)
0a4b04dc AB	365	#define VCCQ1LCDCR IOMEM(0xE6058186)
665ccfa0	366
d55c9a97 KM	367	static void __init bonito_init(void)
	368	{
	369	u16 val;
	370
d3ed18ea GL	371	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
d3ed18ea GL	372
d55c9a97	373	r8a7740_pinmux_init();
6bf2805d	374	bonito_fpga_init();
d55c9a97	375
e609b7cb KM	376	pmic_settings = pmic_do_2A;
e609b7cb KM	377
b6b37e25 KM	378	/*
	379	* core board settings
	380	*/
d55c9a97 KM	381
	382	#ifdef CONFIG_CACHE_L2X0
	383	/* Early BRESP enable, Shared attribute override enable, 32K8way /
a2a47ca3	384	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
d55c9a97 KM	385	#endif
	386
	387	r8a7740_add_standard_devices();
b6b37e25 KM	388
	389	platform_add_devices(bonito_core_devices,
	390	ARRAY_SIZE(bonito_core_devices));
	391
	392	/*
	393	* base board settings
	394	*/
89aaf5c0	395	gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL);
b6b37e25 KM	396	if (!gpio_get_value(GPIO_PORT176)) {
	397	u16 bsw2;
	398	u16 bsw3;
	399	u16 bsw4;
	400
	401	/*
	402	* FPGA
	403	*/
	404	gpio_request(GPIO_FN_CS5B, NULL);
	405	gpio_request(GPIO_FN_CS6A, NULL);
	406	gpio_request(GPIO_FN_CS5A_PORT105, NULL);
	407	gpio_request(GPIO_FN_IRQ10, NULL);
	408
	409	val = bonito_fpga_read(BVERR);
	410	pr_info("bonito version: cpu %02x, base %02x\n",
	411	((val >> 8) & 0xFF),
	412	((val >> 0) & 0xFF));
	413
	414	bsw2 = bonito_fpga_read(BUSSWMR2);
	415	bsw3 = bonito_fpga_read(BUSSWMR3);
	416	bsw4 = bonito_fpga_read(BUSSWMR4);
	417
	418	/*
	419	* SCIFA5 (CN42)
	420	*/
	421	if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
	422	BIT_OFF(bsw3, 9) && /* S39.6 = ON */
	423	BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
	424	gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
	425	gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
	426	}
	427
665ccfa0 KM	428	/*
	429	* LCDC0 (CN3)
	430	*/
	431	if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
	432	BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
	433	gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
	434	gpio_request(GPIO_FN_LCD0_D0, NULL);
	435	gpio_request(GPIO_FN_LCD0_D1, NULL);
	436	gpio_request(GPIO_FN_LCD0_D2, NULL);
	437	gpio_request(GPIO_FN_LCD0_D3, NULL);
	438	gpio_request(GPIO_FN_LCD0_D4, NULL);
	439	gpio_request(GPIO_FN_LCD0_D5, NULL);
	440	gpio_request(GPIO_FN_LCD0_D6, NULL);
	441	gpio_request(GPIO_FN_LCD0_D7, NULL);
	442	gpio_request(GPIO_FN_LCD0_D8, NULL);
	443	gpio_request(GPIO_FN_LCD0_D9, NULL);
	444	gpio_request(GPIO_FN_LCD0_D10, NULL);
	445	gpio_request(GPIO_FN_LCD0_D11, NULL);
	446	gpio_request(GPIO_FN_LCD0_D12, NULL);
	447	gpio_request(GPIO_FN_LCD0_D13, NULL);
	448	gpio_request(GPIO_FN_LCD0_D14, NULL);
	449	gpio_request(GPIO_FN_LCD0_D15, NULL);
	450	gpio_request(GPIO_FN_LCD0_D16, NULL);
	451	gpio_request(GPIO_FN_LCD0_D17, NULL);
	452	gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
	453	gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
	454	gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
	455	gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
	456	gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
	457	gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
	458	gpio_request(GPIO_FN_LCD0_DCK, NULL);
	459	gpio_request(GPIO_FN_LCD0_VSYN, NULL);
	460	gpio_request(GPIO_FN_LCD0_HSYN, NULL);
	461	gpio_request(GPIO_FN_LCD0_DISP, NULL);
	462	gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
	463
89aaf5c0 LP	464	gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
89aaf5c0 LP	465	NULL); /* LCDDON */
665ccfa0 KM	466
	467	/* backlight on */
	468	bonito_fpga_write(LCDCR, 1);
	469
	470	/* drivability Max */
	471	__raw_writew(0x00FF , VCCQ1LCDCR);
	472	__raw_writew(0xFFFF , VCCQ1CR);
	473	}
	474
b6b37e25 KM	475	platform_add_devices(bonito_base_devices,
	476	ARRAY_SIZE(bonito_base_devices));
	477	}
d55c9a97 KM	478	}
d55c9a97 KM	479
23e5bc03	480	static void __init bonito_earlytimer_init(void)
d55c9a97 KM	481	{
	482	u16 val;
	483	u8 md_ck = 0;
	484
	485	/* read MD_CK value */
	486	val = bonito_fpga_read(A1MDSR);
	487	if (val & (1 << 10))
	488	md_ck \|= MD_CK2;
	489	if (val & (1 << 9))
	490	md_ck \|= MD_CK1;
	491	if (val & (1 << 8))
	492	md_ck \|= MD_CK0;
	493
	494	r8a7740_clock_init(md_ck);
23e5bc03	495	shmobile_earlytimer_init();
d55c9a97 KM	496	}
d55c9a97 KM	497
8823e2b3	498	static void __init bonito_add_early_devices(void)
23e5bc03 MD	499	{
23e5bc03 MD	500	r8a7740_add_early_devices();
23e5bc03	501	}
d55c9a97 KM	502
	503	MACHINE_START(BONITO, "bonito")
	504	.map_io = bonito_map_io,
23e5bc03	505	.init_early = bonito_add_early_devices,
d55c9a97 KM	506	.init_irq = r8a7740_init_irq,
	507	.handle_irq = shmobile_handle_irq_intc,
	508	.init_machine = bonito_init,
21cc1b7e	509	.init_late = shmobile_init_late,
6bb27d73	510	.init_time = bonito_earlytimer_init,
d55c9a97	511	MACHINE_END