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Merge branch 'for-3.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj...
[deliverable/linux.git] / arch / arm / mach-shmobile / clock-sh7372.c
CommitLineData
495b3cea
MD		 1/*
2 * SH7372 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
495b3cea
MD		 21#include <linux/io.h>
22#include <linux/sh_clk.h>
6d803ba7 23#include <linux/clkdev.h>
99fb32b8 24#include <mach/clock.h>
495b3cea 25#include <mach/common.h>
495b3cea
MD		 26
27/* SH7372 registers */
0a4b04dc
AB		 28#define FRQCRA IOMEM(0xe6150000)
29#define FRQCRB IOMEM(0xe6150004)
30#define FRQCRC IOMEM(0xe61500e0)
31#define FRQCRD IOMEM(0xe61500e4)
32#define VCLKCR1 IOMEM(0xe6150008)
33#define VCLKCR2 IOMEM(0xe615000c)
34#define VCLKCR3 IOMEM(0xe615001c)
35#define FMSICKCR IOMEM(0xe6150010)
36#define FMSOCKCR IOMEM(0xe6150014)
37#define FSIACKCR IOMEM(0xe6150018)
38#define FSIBCKCR IOMEM(0xe6150090)
39#define SUBCKCR IOMEM(0xe6150080)
40#define SPUCKCR IOMEM(0xe6150084)
41#define VOUCKCR IOMEM(0xe6150088)
42#define HDMICKCR IOMEM(0xe6150094)
43#define DSITCKCR IOMEM(0xe6150060)
44#define DSI0PCKCR IOMEM(0xe6150064)
45#define DSI1PCKCR IOMEM(0xe6150098)
46#define PLLC01CR IOMEM(0xe6150028)
47#define PLLC2CR IOMEM(0xe615002c)
48#define RMSTPCR0 IOMEM(0xe6150110)
49#define RMSTPCR1 IOMEM(0xe6150114)
50#define RMSTPCR2 IOMEM(0xe6150118)
51#define RMSTPCR3 IOMEM(0xe615011c)
52#define RMSTPCR4 IOMEM(0xe6150120)
53#define SMSTPCR0 IOMEM(0xe6150130)
54#define SMSTPCR1 IOMEM(0xe6150134)
55#define SMSTPCR2 IOMEM(0xe6150138)
56#define SMSTPCR3 IOMEM(0xe615013c)
57#define SMSTPCR4 IOMEM(0xe6150140)
495b3cea 58
f2ace4a5
KM		 59#define FSIDIVA 0xFE1F8000
60#define FSIDIVB 0xFE1F8008
61
b90884c8 62/* Platforms must set frequency on their DV_CLKI pin */
685e4080 63struct clk sh7372_dv_clki_clk = {
b90884c8
GL		 64};
65
495b3cea
MD		 66/* Fixed 32 KHz root clock from EXTALR pin */
67static struct clk r_clk = {
68 .rate = 32768,
69};
70
71/*
72 * 26MHz default rate for the EXTAL1 root input clock.
73 * If needed, reset this with clk_set_rate() from the platform code.
74 */
83ca5c87 75struct clk sh7372_extal1_clk = {
3b79bece 76 .rate = 26000000,
495b3cea
MD		 77};
78
79/*
80 * 48MHz default rate for the EXTAL2 root input clock.
81 * If needed, reset this with clk_set_rate() from the platform code.
82 */
83ca5c87 83struct clk sh7372_extal2_clk = {
495b3cea
MD		 84 .rate = 48000000,
85};
86
99fb32b8 87SH_CLK_RATIO(div2, 1, 2);
495b3cea 88
99fb32b8
KM		 89SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2);
90SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2);
91SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2);
92SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2);
495b3cea
MD		 93
94/* PLLC0 and PLLC1 */
95static unsigned long pllc01_recalc(struct clk *clk)
96{
97 unsigned long mult = 1;
98
99 if (__raw_readl(PLLC01CR) & (1 << 14))
100 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
101
102 return clk->parent->rate * mult;
103}
104
628f4561 105static struct sh_clk_ops pllc01_clk_ops = {
495b3cea
MD		 106 .recalc = pllc01_recalc,
107};
108
109static struct clk pllc0_clk = {
110 .ops = &pllc01_clk_ops,
111 .flags = CLK_ENABLE_ON_INIT,
112 .parent = &extal1_div2_clk,
113 .enable_reg = (void __iomem *)FRQCRC,
114};
115
116static struct clk pllc1_clk = {
117 .ops = &pllc01_clk_ops,
118 .flags = CLK_ENABLE_ON_INIT,
119 .parent = &extal1_div2_clk,
120 .enable_reg = (void __iomem *)FRQCRA,
121};
122
123/* Divide PLLC1 by two */
99fb32b8 124SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
495b3cea
MD		 125
126/* PLLC2 */
b90884c8
GL		 127
128/* Indices are important - they are the actual src selecting values */
129static struct clk *pllc2_parent[] = {
130 [0] = &extal1_div2_clk,
131 [1] = &extal2_div2_clk,
685e4080 132 [2] = &sh7372_dv_clki_div2_clk,
b90884c8
GL		 133};
134
135/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
136static struct cpufreq_frequency_table pllc2_freq_table[29];
137
138static void pllc2_table_rebuild(struct clk *clk)
139{
140 int i;
141
142 /* Initialise PLLC2 frequency table */
143 for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
144 pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
50701588 145 pllc2_freq_table[i].driver_data = i;
b90884c8
GL		 146 }
147
148 /* This is a special entry - switching PLL off makes it a repeater */
149 pllc2_freq_table[i].frequency = clk->parent->rate;
50701588 150 pllc2_freq_table[i].driver_data = i;
b90884c8
GL		 151
152 pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
50701588 153 pllc2_freq_table[i].driver_data = i;
b90884c8
GL		 154}
155
495b3cea
MD		 156static unsigned long pllc2_recalc(struct clk *clk)
157{
158 unsigned long mult = 1;
159
b90884c8
GL		 160 pllc2_table_rebuild(clk);
161
162 /*
163 * If the PLL is off, mult == 1, clk->rate will be updated in
164 * pllc2_enable().
165 */
495b3cea
MD		 166 if (__raw_readl(PLLC2CR) & (1 << 31))
167 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
168
169 return clk->parent->rate * mult;
170}
171
b90884c8
GL		 172static long pllc2_round_rate(struct clk *clk, unsigned long rate)
173{
174 return clk_rate_table_round(clk, clk->freq_table, rate);
175}
176
177static int pllc2_enable(struct clk *clk)
178{
179 int i;
180
181 __raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR);
182
183 for (i = 0; i < 100; i++)
184 if (__raw_readl(PLLC2CR) & 0x80000000) {
185 clk->rate = pllc2_recalc(clk);
186 return 0;
187 }
188
189 pr_err("%s(): timeout!\n", __func__);
190
191 return -ETIMEDOUT;
192}
193
194static void pllc2_disable(struct clk *clk)
195{
196 __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
197}
198
35a96c73 199static int pllc2_set_rate(struct clk *clk, unsigned long rate)
b90884c8
GL		 200{
201 unsigned long value;
202 int idx;
203
204 idx = clk_rate_table_find(clk, clk->freq_table, rate);
205 if (idx < 0)
206 return idx;
207
421b446a
KM		 208 if (rate == clk->parent->rate)
209 return -EINVAL;
b90884c8
GL		 210
211 value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
212
ff9531ec
KM		 213 __raw_writel(value | ((idx + 19) << 24), PLLC2CR);
214
215 clk->rate = clk->freq_table[idx].frequency;
b90884c8 216
b90884c8
GL		 217 return 0;
218}
219
220static int pllc2_set_parent(struct clk *clk, struct clk *parent)
221{
222 u32 value;
223 int ret, i;
224
225 if (!clk->parent_table || !clk->parent_num)
226 return -EINVAL;
227
228 /* Search the parent */
229 for (i = 0; i < clk->parent_num; i++)
230 if (clk->parent_table[i] == parent)
231 break;
232
233 if (i == clk->parent_num)
234 return -ENODEV;
235
236 ret = clk_reparent(clk, parent);
237 if (ret < 0)
238 return ret;
239
240 value = __raw_readl(PLLC2CR) & ~(3 << 6);
241
242 __raw_writel(value | (i << 6), PLLC2CR);
243
244 /* Rebiuld the frequency table */
245 pllc2_table_rebuild(clk);
246
247 return 0;
248}
249
628f4561 250static struct sh_clk_ops pllc2_clk_ops = {
495b3cea 251 .recalc = pllc2_recalc,
b90884c8
GL		 252 .round_rate = pllc2_round_rate,
253 .set_rate = pllc2_set_rate,
254 .enable = pllc2_enable,
255 .disable = pllc2_disable,
256 .set_parent = pllc2_set_parent,
495b3cea
MD		 257};
258
685e4080 259struct clk sh7372_pllc2_clk = {
495b3cea 260 .ops = &pllc2_clk_ops,
495b3cea 261 .parent = &extal1_div2_clk,
b90884c8 262 .freq_table = pllc2_freq_table,
5c4e0f19 263 .nr_freqs = ARRAY_SIZE(pllc2_freq_table) - 1,
b90884c8
GL		 264 .parent_table = pllc2_parent,
265 .parent_num = ARRAY_SIZE(pllc2_parent),
495b3cea
MD		 266};
267
69ce8aa4 268/* External input clock (pin name: FSIACK/FSIBCK ) */
d5b68908 269static struct clk fsiack_clk = {
69ce8aa4
KM		 270};
271
d5b68908 272static struct clk fsibck_clk = {
69ce8aa4
KM		 273};
274
83ca5c87 275static struct clk *main_clks[] = {
685e4080 276 &sh7372_dv_clki_clk,
495b3cea 277 &r_clk,
83ca5c87
MD		 278 &sh7372_extal1_clk,
279 &sh7372_extal2_clk,
685e4080 280 &sh7372_dv_clki_div2_clk,
495b3cea
MD		 281 &extal1_div2_clk,
282 &extal2_div2_clk,
283 &extal2_div4_clk,
284 &pllc0_clk,
285 &pllc1_clk,
286 &pllc1_div2_clk,
685e4080 287 &sh7372_pllc2_clk,
d5b68908
KM		 288 &fsiack_clk,
289 &fsibck_clk,
495b3cea
MD		 290};
291
292static void div4_kick(struct clk *clk)
293{
294 unsigned long value;
295
296 /* set KICK bit in FRQCRB to update hardware setting */
297 value = __raw_readl(FRQCRB);
298 value |= (1 << 31);
299 __raw_writel(value, FRQCRB);
300}
301
302static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
303 24, 32, 36, 48, 0, 72, 96, 0 };
304
305static struct clk_div_mult_table div4_div_mult_table = {
306 .divisors = divisors,
307 .nr_divisors = ARRAY_SIZE(divisors),
308};
309
310static struct clk_div4_table div4_table = {
311 .div_mult_table = &div4_div_mult_table,
312 .kick = div4_kick,
313};
314
315enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
b3186c68 316 DIV4_ZX, DIV4_HP,
495b3cea
MD		 317 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
318 DIV4_DDRP, DIV4_NR };
319
320#define DIV4(_reg, _bit, _mask, _flags) \
321 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
322
83ca5c87 323static struct clk div4_clks[DIV4_NR] = {
495b3cea
MD		 324 [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
325 [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
326 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
327 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
328 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
495b3cea
MD		 329 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
330 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
331 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
332 [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
333 [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
334 [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
335 [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
336 [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
337};
338
339enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
69ce8aa4 340 DIV6_SUB, DIV6_SPU,
b90884c8 341 DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
495b3cea
MD		 342 DIV6_NR };
343
83ca5c87 344static struct clk div6_clks[DIV6_NR] = {
495b3cea
MD		 345 [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
346 [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
347 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
348 [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
349 [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
83ca5c87 350 [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
495b3cea
MD		 351 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
352 [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
495b3cea
MD		 353 [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
354 [DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
355 [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
356};
357
69ce8aa4 358enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR };
b90884c8
GL		 359
360/* Indices are important - they are the actual src selecting values */
361static struct clk *hdmi_parent[] = {
362 [0] = &pllc1_div2_clk,
685e4080
KM		 363 [1] = &sh7372_pllc2_clk,
364 [2] = &sh7372_dv_clki_clk,
b90884c8
GL		 365 [3] = NULL, /* pllc2_div4 not implemented yet */
366};
367
69ce8aa4
KM		 368static struct clk *fsiackcr_parent[] = {
369 [0] = &pllc1_div2_clk,
370 [1] = &sh7372_pllc2_clk,
d5b68908 371 [2] = &fsiack_clk, /* external input for FSI A */
69ce8aa4
KM		 372 [3] = NULL, /* setting prohibited */
373};
374
375static struct clk *fsibckcr_parent[] = {
376 [0] = &pllc1_div2_clk,
377 [1] = &sh7372_pllc2_clk,
d5b68908 378 [2] = &fsibck_clk, /* external input for FSI B */
69ce8aa4
KM		 379 [3] = NULL, /* setting prohibited */
380};
381
b90884c8 382static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
56242a1f 383 [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
b90884c8 384 hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
56242a1f 385 [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
69ce8aa4 386 fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
56242a1f 387 [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
69ce8aa4 388 fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
b90884c8
GL		 389};
390
f2ace4a5 391/* FSI DIV */
dc3cad82 392enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
f2ace4a5 393
dc3cad82
KM		 394static struct clk fsidivs[] = {
395 [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
396 [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
f2ace4a5
KM		 397};
398
7ceb6666 399enum { MSTP001, MSTP000,
d473e0a5 400 MSTP131, MSTP130,
c6c049ec 401 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
bca606a6 402 MSTP118, MSTP117, MSTP116, MSTP113,
d473e0a5 403 MSTP106, MSTP101, MSTP100,
495b3cea 404 MSTP223,
7ceb6666
MD		 405 MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207,
406 MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
2aab52e8 407 MSTP328, MSTP323, MSTP322, MSTP315, MSTP314, MSTP313, MSTP312,
6b4cb8ff 408 MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406,
a408baea 409 MSTP405, MSTP404, MSTP403, MSTP400,
495b3cea
MD		 410 MSTP_NR };
411
412#define MSTP(_parent, _reg, _bit, _flags) \
413 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
414
415static struct clk mstp_clks[MSTP_NR] = {
416 [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
7ceb6666 417 [MSTP000] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 0, 0), /* MSIOF0 */
495b3cea
MD		 418 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
419 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
420 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
421 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
a4909b52
GL		 422 [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
423 [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
c6c049ec 424 [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
6e86ccad
GL		 425 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
426 [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
495b3cea 427 [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
bca606a6 428 [MSTP113] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 13, 0), /* MERAM */
495b3cea
MD		 429 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
430 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
d473e0a5 431 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
495b3cea 432 [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
816af742
GL		 433 [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
434 [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
435 [MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
afe48049 436 [MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
7ceb6666 437 [MSTP208] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 8, 0), /* MSIOF1 */
495b3cea
MD		 438 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
439 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
7ceb6666 440 [MSTP205] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 5, 0), /* MSIOF2 */
495b3cea
MD		 441 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
442 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
443 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
444 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
445 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
69ce8aa4 446 [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
495b3cea
MD		 447 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
448 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
2aab52e8 449 [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL*/
495b3cea
MD		 450 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
451 [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
21a89344 452 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
0851d50d 453 [MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */
495b3cea 454 [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
b90884c8 455 [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
495b3cea
MD		 456 [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
457 [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
6b4cb8ff 458 [MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */
495b3cea 459 [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
a408baea
MD		 460 [MSTP405] = MSTP(&r_clk, SMSTPCR4, 5, 0), /* CMT4 */
461 [MSTP404] = MSTP(&r_clk, SMSTPCR4, 4, 0), /* CMT3 */
495b3cea 462 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
0ed61fc9 463 [MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */
495b3cea
MD		 464};
465
495b3cea
MD		 466static struct clk_lookup lookups[] = {
467 /* main clocks */
685e4080 468 CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
495b3cea 469 CLKDEV_CON_ID("r_clk", &r_clk),
83ca5c87
MD		 470 CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
471 CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
495b3cea
MD		 472 CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
473 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
474 CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
475 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
476 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
477 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
685e4080 478 CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
d5b68908
KM		 479 CLKDEV_CON_ID("fsiack", &fsiack_clk),
480 CLKDEV_CON_ID("fsibck", &fsibck_clk),
495b3cea
MD		 481
482 /* DIV4 clocks */
483 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
484 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
485 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
486 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
487 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
495b3cea
MD		 488 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
489 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
490 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
491 CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
492 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
493 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
494 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
495 CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
496
497 /* DIV6 clocks */
498 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
499 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
500 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
501 CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
502 CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
495b3cea
MD		 503 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
504 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
505 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
b90884c8 506 CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
0851d50d
GL		 507 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
508 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
9250741e
KM		 509 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
510 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
495b3cea
MD		 511
512 /* MSTP32 clocks */
513 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
529a7b32 514 CLKDEV_DEV_ID("fff30000.i2c", &mstp_clks[MSTP001]), /* IIC2 */
7ceb6666 515 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
83ca5c87
MD		 516 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
517 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
518 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
519 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
a4909b52
GL		 520 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
521 CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
c6c049ec
MD		 522 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
523 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
0851d50d 524 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
d473e0a5 525 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
495b3cea 526 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
529a7b32 527 CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), /* IIC0 */
bca606a6 528 CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */
495b3cea
MD		 529 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
530 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
d473e0a5 531 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
495b3cea
MD		 532 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
533 CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
816af742
GL		 534 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */
535 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */
536 CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */
afe48049 537 CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), /* USB-DMAC0 */
7ceb6666 538 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[MSTP208]), /* MSIOF1 */
495b3cea
MD		 539 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
540 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
7ceb6666 541 CLKDEV_DEV_ID("spi_sh_msiof.2", &mstp_clks[MSTP205]), /* MSIOF2 */
495b3cea
MD		 542 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
543 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
544 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
545 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
546 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
9848f2f3 547 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
495b3cea 548 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
529a7b32 549 CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), /* IIC1 */
4d048435
MD		 550 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
551 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
cc0a5a58 552 CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
2aab52e8 553 CLKDEV_DEV_ID("sh_flctl.0", &mstp_clks[MSTP315]), /* FLCTL */
495b3cea 554 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
529a7b32 555 CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
495b3cea 556 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
529a7b32 557 CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
21a89344 558 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
529a7b32 559 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMC */
0851d50d 560 CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */
495b3cea 561 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
529a7b32 562 CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), /* SDHI2 */
b90884c8 563 CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
495b3cea 564 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
529a7b32 565 CLKDEV_DEV_ID("e6d20000.i2c", &mstp_clks[MSTP411]), /* IIC3 */
495b3cea 566 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
529a7b32 567 CLKDEV_DEV_ID("e6d30000.i2c", &mstp_clks[MSTP410]), /* IIC4 */
6b4cb8ff 568 CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */
495b3cea
MD		 569 CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
570 CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
cc0a5a58 571 CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
a408baea
MD		 572 CLKDEV_DEV_ID("sh_cmt.4", &mstp_clks[MSTP405]), /* CMT4 */
573 CLKDEV_DEV_ID("sh_cmt.3", &mstp_clks[MSTP404]), /* CMT3 */
495b3cea 574 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
0ed61fc9 575 CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */
69ce8aa4 576
5c3f96b2
MD		 577 CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
578 &div6_reparent_clks[DIV6_HDMI]),
69ce8aa4
KM		 579 CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
580 CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
581 CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
a41b6466 582 CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
dc3cad82
KM		 583 CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
584 CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
d5b68908
KM		 585 CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk),
586 CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk),
495b3cea
MD		 587};
588
589void __init sh7372_clock_init(void)
590{
591 int k, ret = 0;
592
6776fba7
MD		 593 /* make sure MSTP bits on the RT/SH4AL-DSP side are off */
594 __raw_writel(0xe4ef8087, RMSTPCR0);
595 __raw_writel(0xffffffff, RMSTPCR1);
596 __raw_writel(0x37c7f7ff, RMSTPCR2);
597 __raw_writel(0xffffffff, RMSTPCR3);
598 __raw_writel(0xffe0fffd, RMSTPCR4);
599
495b3cea
MD		 600 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
601 ret = clk_register(main_clks[k]);
602
603 if (!ret)
604 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
605
606 if (!ret)
607 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
608
b90884c8 609 if (!ret)
5d8e3451 610 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
b90884c8 611
495b3cea 612 if (!ret)
64e9de2f 613 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
495b3cea 614
dc3cad82
KM		 615 if (!ret)
616 ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
f2ace4a5 617
495b3cea
MD		 618 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
619
620 if (!ret)
6b6a4c06 621 shmobile_clk_init();
495b3cea
MD		 622 else
623 panic("failed to setup sh7372 clocks\n");
495b3cea 624}
Linux kernel - Deliverables
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