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ARM: shmobile: sh73a0: add a TWD clock
[deliverable/linux.git] / arch / arm / mach-shmobile / clock-sh73a0.c
CommitLineData
6d9598e2
MD		 1/*
2 * sh73a0 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/sh_clk.h>
6ef9f6fd 23#include <linux/clkdev.h>
7653c318 24#include <asm/processor.h>
6d9598e2 25#include <mach/common.h>
6d9598e2 26
0a4b04dc
AB		 27#define FRQCRA IOMEM(0xe6150000)
28#define FRQCRB IOMEM(0xe6150004)
29#define FRQCRD IOMEM(0xe61500e4)
30#define VCLKCR1 IOMEM(0xe6150008)
31#define VCLKCR2 IOMEM(0xe615000C)
32#define VCLKCR3 IOMEM(0xe615001C)
33#define ZBCKCR IOMEM(0xe6150010)
34#define FLCKCR IOMEM(0xe6150014)
35#define SD0CKCR IOMEM(0xe6150074)
36#define SD1CKCR IOMEM(0xe6150078)
37#define SD2CKCR IOMEM(0xe615007C)
38#define FSIACKCR IOMEM(0xe6150018)
39#define FSIBCKCR IOMEM(0xe6150090)
40#define SUBCKCR IOMEM(0xe6150080)
41#define SPUACKCR IOMEM(0xe6150084)
42#define SPUVCKCR IOMEM(0xe6150094)
43#define MSUCKCR IOMEM(0xe6150088)
44#define HSICKCR IOMEM(0xe615008C)
45#define MFCK1CR IOMEM(0xe6150098)
46#define MFCK2CR IOMEM(0xe615009C)
47#define DSITCKCR IOMEM(0xe6150060)
48#define DSI0PCKCR IOMEM(0xe6150064)
49#define DSI1PCKCR IOMEM(0xe6150068)
f6d84f4a
MD		 50#define DSI0PHYCR 0xe615006C
51#define DSI1PHYCR 0xe6150070
0a4b04dc
AB		 52#define PLLECR IOMEM(0xe61500d0)
53#define PLL0CR IOMEM(0xe61500d8)
54#define PLL1CR IOMEM(0xe6150028)
55#define PLL2CR IOMEM(0xe615002c)
56#define PLL3CR IOMEM(0xe61500dc)
57#define SMSTPCR0 IOMEM(0xe6150130)
58#define SMSTPCR1 IOMEM(0xe6150134)
59#define SMSTPCR2 IOMEM(0xe6150138)
60#define SMSTPCR3 IOMEM(0xe615013c)
61#define SMSTPCR4 IOMEM(0xe6150140)
62#define SMSTPCR5 IOMEM(0xe6150144)
63#define CKSCR IOMEM(0xe61500c0)
6d9598e2
MD		 64
65/* Fixed 32 KHz root clock from EXTALR pin */
66static struct clk r_clk = {
67 .rate = 32768,
68};
69
f6d84f4a
MD		 70/*
71 * 26MHz default rate for the EXTAL1 root input clock.
72 * If needed, reset this with clk_set_rate() from the platform code.
73 */
74struct clk sh73a0_extal1_clk = {
75 .rate = 26000000,
76};
77
78/*
79 * 48MHz default rate for the EXTAL2 root input clock.
80 * If needed, reset this with clk_set_rate() from the platform code.
81 */
82struct clk sh73a0_extal2_clk = {
83 .rate = 48000000,
84};
85
86/* A fixed divide-by-2 block */
87static unsigned long div2_recalc(struct clk *clk)
88{
89 return clk->parent->rate / 2;
90}
91
7bcda508 92static struct sh_clk_ops div2_clk_ops = {
f6d84f4a
MD		 93 .recalc = div2_recalc,
94};
95
d4775356
KM		 96static unsigned long div7_recalc(struct clk *clk)
97{
98 return clk->parent->rate / 7;
99}
100
7bcda508 101static struct sh_clk_ops div7_clk_ops = {
d4775356
KM		 102 .recalc = div7_recalc,
103};
104
105static unsigned long div13_recalc(struct clk *clk)
106{
107 return clk->parent->rate / 13;
108}
109
7bcda508 110static struct sh_clk_ops div13_clk_ops = {
d4775356
KM		 111 .recalc = div13_recalc,
112};
113
f6d84f4a
MD		 114/* Divide extal1 by two */
115static struct clk extal1_div2_clk = {
116 .ops = &div2_clk_ops,
117 .parent = &sh73a0_extal1_clk,
118};
119
120/* Divide extal2 by two */
121static struct clk extal2_div2_clk = {
122 .ops = &div2_clk_ops,
123 .parent = &sh73a0_extal2_clk,
124};
125
7bcda508 126static struct sh_clk_ops main_clk_ops = {
f6d84f4a
MD		 127 .recalc = followparent_recalc,
128};
129
130/* Main clock */
131static struct clk main_clk = {
132 .ops = &main_clk_ops,
133};
134
33661c9e 135/* Divide Main clock by two */
d4775356
KM		 136static struct clk main_div2_clk = {
137 .ops = &div2_clk_ops,
138 .parent = &main_clk,
139};
140
f6d84f4a
MD		 141/* PLL0, PLL1, PLL2, PLL3 */
142static unsigned long pll_recalc(struct clk *clk)
143{
144 unsigned long mult = 1;
145
71fc5099 146 if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {
f6d84f4a 147 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
71fc5099
MD		 148 /* handle CFG bit for PLL1 and PLL2 */
149 switch (clk->enable_bit) {
150 case 1:
151 case 2:
152 if (__raw_readl(clk->enable_reg) & (1 << 20))
153 mult *= 2;
154 }
155 }
f6d84f4a
MD		 156
157 return clk->parent->rate * mult;
158}
159
7bcda508 160static struct sh_clk_ops pll_clk_ops = {
f6d84f4a
MD		 161 .recalc = pll_recalc,
162};
163
164static struct clk pll0_clk = {
165 .ops = &pll_clk_ops,
166 .flags = CLK_ENABLE_ON_INIT,
167 .parent = &main_clk,
168 .enable_reg = (void __iomem *)PLL0CR,
169 .enable_bit = 0,
6d9598e2
MD		 170};
171
f6d84f4a
MD		 172static struct clk pll1_clk = {
173 .ops = &pll_clk_ops,
174 .flags = CLK_ENABLE_ON_INIT,
175 .parent = &main_clk,
176 .enable_reg = (void __iomem *)PLL1CR,
177 .enable_bit = 1,
178};
179
180static struct clk pll2_clk = {
181 .ops = &pll_clk_ops,
182 .flags = CLK_ENABLE_ON_INIT,
183 .parent = &main_clk,
184 .enable_reg = (void __iomem *)PLL2CR,
185 .enable_bit = 2,
186};
187
188static struct clk pll3_clk = {
189 .ops = &pll_clk_ops,
190 .flags = CLK_ENABLE_ON_INIT,
191 .parent = &main_clk,
192 .enable_reg = (void __iomem *)PLL3CR,
193 .enable_bit = 3,
194};
195
d4775356 196/* Divide PLL */
f6d84f4a
MD		 197static struct clk pll1_div2_clk = {
198 .ops = &div2_clk_ops,
199 .parent = &pll1_clk,
b028f94b
YT		 200};
201
d4775356
KM		 202static struct clk pll1_div7_clk = {
203 .ops = &div7_clk_ops,
204 .parent = &pll1_clk,
205};
206
207static struct clk pll1_div13_clk = {
208 .ops = &div13_clk_ops,
209 .parent = &pll1_clk,
210};
211
212/* External input clock */
213struct clk sh73a0_extcki_clk = {
214};
215
216struct clk sh73a0_extalr_clk = {
217};
218
6d9598e2
MD		 219static struct clk *main_clks[] = {
220 &r_clk,
f6d84f4a
MD		 221 &sh73a0_extal1_clk,
222 &sh73a0_extal2_clk,
223 &extal1_div2_clk,
224 &extal2_div2_clk,
225 &main_clk,
d4775356 226 &main_div2_clk,
f6d84f4a
MD		 227 &pll0_clk,
228 &pll1_clk,
229 &pll2_clk,
230 &pll3_clk,
231 &pll1_div2_clk,
d4775356
KM		 232 &pll1_div7_clk,
233 &pll1_div13_clk,
234 &sh73a0_extcki_clk,
235 &sh73a0_extalr_clk,
f6d84f4a
MD		 236};
237
7653c318 238static int frqcr_kick(void)
f6d84f4a 239{
7653c318
GL		 240 int i;
241
242 /* set KICK bit in FRQCRB to update hardware setting, check success */
243 __raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB);
244 for (i = 1000; i; i--)
245 if (__raw_readl(FRQCRB) & (1 << 31))
246 cpu_relax();
247 else
248 return i;
249
250 return -ETIMEDOUT;
251}
f6d84f4a 252
7653c318
GL		 253static void div4_kick(struct clk *clk)
254{
255 frqcr_kick();
f6d84f4a
MD		 256}
257
258static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
c070c203 259 24, 0, 36, 48, 7 };
f6d84f4a
MD		 260
261static struct clk_div_mult_table div4_div_mult_table = {
262 .divisors = divisors,
263 .nr_divisors = ARRAY_SIZE(divisors),
264};
265
266static struct clk_div4_table div4_table = {
267 .div_mult_table = &div4_div_mult_table,
268 .kick = div4_kick,
269};
270
271enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
272 DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR };
273
274#define DIV4(_reg, _bit, _mask, _flags) \
275 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
276
277static struct clk div4_clks[DIV4_NR] = {
bf519bfb 278 [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
8a444474 279 [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
bf519bfb
KM		 280 [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
281 [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
282 [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
283 [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
8a444474 284 [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
bf519bfb
KM		 285 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
286 [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
287 [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
288 [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
f6d84f4a
MD		 289};
290
fe7aa82d
GL		 291static unsigned long twd_recalc(struct clk *clk)
292{
293 return clk_get_rate(clk->parent) / 4;
294}
295
296static struct sh_clk_ops twd_clk_ops = {
297 .recalc = twd_recalc,
298};
299
300static struct clk twd_clk = {
301 .parent = &div4_clks[DIV4_Z],
302 .ops = &twd_clk_ops,
303};
304
f6d84f4a
MD		 305enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
306 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
307 DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
308 DIV6_SPUA, DIV6_SPUV, DIV6_MSU,
309 DIV6_HSI, DIV6_MFG1, DIV6_MFG2,
310 DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
311 DIV6_NR };
312
d4775356
KM		 313static struct clk *vck_parent[8] = {
314 [0] = &pll1_div2_clk,
315 [1] = &pll2_clk,
316 [2] = &sh73a0_extcki_clk,
317 [3] = &sh73a0_extal2_clk,
318 [4] = &main_div2_clk,
319 [5] = &sh73a0_extalr_clk,
320 [6] = &main_clk,
321};
322
323static struct clk *pll_parent[4] = {
324 [0] = &pll1_div2_clk,
325 [1] = &pll2_clk,
326 [2] = &pll1_div13_clk,
327};
328
329static struct clk *hsi_parent[4] = {
330 [0] = &pll1_div2_clk,
331 [1] = &pll2_clk,
332 [2] = &pll1_div7_clk,
333};
334
335static struct clk *pll_extal2_parent[] = {
336 [0] = &pll1_div2_clk,
337 [1] = &pll2_clk,
338 [2] = &sh73a0_extal2_clk,
339 [3] = &sh73a0_extal2_clk,
340};
341
342static struct clk *dsi_parent[8] = {
343 [0] = &pll1_div2_clk,
344 [1] = &pll2_clk,
345 [2] = &main_clk,
346 [3] = &sh73a0_extal2_clk,
347 [4] = &sh73a0_extcki_clk,
348};
349
f6d84f4a 350static struct clk div6_clks[DIV6_NR] = {
d4775356
KM		 351 [DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
352 vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
353 [DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
354 vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
355 [DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0,
356 vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
ca371d28 357 [DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
d4775356
KM		 358 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
359 [DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0,
360 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
361 [DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0,
362 pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
363 [DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0,
364 pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
365 [DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0,
366 pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
367 [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
368 pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
369 [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
370 pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
371 [DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0,
372 pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
373 [DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0,
374 pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
375 [DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0,
376 pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
377 [DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0,
378 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
379 [DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0,
380 hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2),
381 [DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0,
382 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
383 [DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0,
384 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
385 [DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0,
386 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
387 [DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0,
388 dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
389 [DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0,
390 dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
6d9598e2
MD		 391};
392
f5948bac
KM		 393/* DSI DIV */
394static unsigned long dsiphy_recalc(struct clk *clk)
395{
396 u32 value;
397
398 value = __raw_readl(clk->mapping->base);
399
400 /* FIXME */
401 if (!(value & 0x000B8000))
402 return clk->parent->rate;
403
404 value &= 0x3f;
405 value += 1;
406
407 if ((value < 12) ||
408 (value > 33)) {
409 pr_err("DSIPHY has wrong value (%d)", value);
410 return 0;
411 }
412
413 return clk->parent->rate / value;
414}
415
416static long dsiphy_round_rate(struct clk *clk, unsigned long rate)
417{
418 return clk_rate_mult_range_round(clk, 12, 33, rate);
419}
420
421static void dsiphy_disable(struct clk *clk)
422{
423 u32 value;
424
425 value = __raw_readl(clk->mapping->base);
426 value &= ~0x000B8000;
427
428 __raw_writel(value , clk->mapping->base);
429}
430
431static int dsiphy_enable(struct clk *clk)
432{
433 u32 value;
434 int multi;
435
436 value = __raw_readl(clk->mapping->base);
437 multi = (value & 0x3f) + 1;
438
439 if ((multi < 12) || (multi > 33))
440 return -EIO;
441
442 __raw_writel(value | 0x000B8000, clk->mapping->base);
443
444 return 0;
445}
446
447static int dsiphy_set_rate(struct clk *clk, unsigned long rate)
448{
449 u32 value;
450 int idx;
451
452 idx = rate / clk->parent->rate;
453 if ((idx < 12) || (idx > 33))
454 return -EINVAL;
455
456 idx += -1;
457
458 value = __raw_readl(clk->mapping->base);
459 value = (value & ~0x3f) + idx;
460
461 __raw_writel(value, clk->mapping->base);
462
463 return 0;
464}
465
7bcda508 466static struct sh_clk_ops dsiphy_clk_ops = {
f5948bac
KM		 467 .recalc = dsiphy_recalc,
468 .round_rate = dsiphy_round_rate,
469 .set_rate = dsiphy_set_rate,
470 .enable = dsiphy_enable,
471 .disable = dsiphy_disable,
472};
473
474static struct clk_mapping dsi0phy_clk_mapping = {
475 .phys = DSI0PHYCR,
476 .len = 4,
477};
478
479static struct clk_mapping dsi1phy_clk_mapping = {
480 .phys = DSI1PHYCR,
481 .len = 4,
482};
483
484static struct clk dsi0phy_clk = {
485 .ops = &dsiphy_clk_ops,
486 .parent = &div6_clks[DIV6_DSI0P], /* late install */
487 .mapping = &dsi0phy_clk_mapping,
488};
489
490static struct clk dsi1phy_clk = {
491 .ops = &dsiphy_clk_ops,
492 .parent = &div6_clks[DIV6_DSI1P], /* late install */
493 .mapping = &dsi1phy_clk_mapping,
494};
495
496static struct clk *late_main_clks[] = {
497 &dsi0phy_clk,
498 &dsi1phy_clk,
fe7aa82d 499 &twd_clk,
f5948bac
KM		 500};
501
f6d84f4a 502enum { MSTP001,
ad054cbd 503 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
832290b2 504 MSTP219, MSTP218, MSTP217,
f6d84f4a 505 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
12a7cfef 506 MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
681e1b3e 507 MSTP314, MSTP313, MSTP312, MSTP311,
33661c9e 508 MSTP303, MSTP302, MSTP301, MSTP300,
696d6e17 509 MSTP411, MSTP410, MSTP403,
6d9598e2
MD		 510 MSTP_NR };
511
512#define MSTP(_parent, _reg, _bit, _flags) \
513 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
514
515static struct clk mstp_clks[MSTP_NR] = {
f6d84f4a 516 [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
ad054cbd
MD		 517 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* CEU1 */
518 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* CSI2-RX1 */
519 [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU0 */
520 [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2-RX0 */
5010f3db 521 [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
170c7ab5 522 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
f6d84f4a 523 [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
170c7ab5 524 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
f6d84f4a 525 [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
32103c7b 526 [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
832290b2 527 [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* MP-DMAC */
f6d84f4a
MD		 528 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
529 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
530 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
531 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
532 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
533 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
534 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
535 [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
6d9598e2 536 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
ea7e1a5a 537 [MSTP328] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /*FSI*/
5a1b70a4 538 [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
f6d84f4a 539 [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
12a7cfef 540 [MSTP322] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 22, 0), /* USB */
fb66c523
MD		 541 [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
542 [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
6bf45a10 543 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
fb66c523 544 [MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */
33661c9e
MD		 545 [MSTP303] = MSTP(&main_div2_clk, SMSTPCR3, 3, 0), /* TPU1 */
546 [MSTP302] = MSTP(&main_div2_clk, SMSTPCR3, 2, 0), /* TPU2 */
547 [MSTP301] = MSTP(&main_div2_clk, SMSTPCR3, 1, 0), /* TPU3 */
548 [MSTP300] = MSTP(&main_div2_clk, SMSTPCR3, 0, 0), /* TPU4 */
f6d84f4a
MD		 549 [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
550 [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
019c4ae3 551 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
6d9598e2
MD		 552};
553
48609533
SH		 554/* The lookups structure below includes duplicate entries for some clocks
555 * with alternate names.
556 * - The traditional name used when a device is initialised with platform data
557 * - The name used when a device is initialised using device tree
558 * The longer-term aim is to remove these duplicates, and indeed the
559 * lookups table entirely, by describing clocks using device tree.
560 */
6d9598e2 561static struct clk_lookup lookups[] = {
f6d84f4a
MD		 562 /* main clocks */
563 CLKDEV_CON_ID("r_clk", &r_clk),
fe7aa82d 564 CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
f6d84f4a 565
170c7ab5 566 /* DIV6 clocks */
ad054cbd
MD		 567 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
568 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
569 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
fb66c523
MD		 570 CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]),
571 CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]),
572 CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
170c7ab5
MD		 573 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
574 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
9250741e
KM		 575 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
576 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
f5948bac
KM		 577 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk),
578 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk),
170c7ab5 579
6d9598e2 580 /* MSTP32 clocks */
696d6e17 581 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
48609533 582 CLKDEV_DEV_ID("e6824000.i2c", &mstp_clks[MSTP001]), /* I2C2 */
ad054cbd
MD		 583 CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
584 CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
585 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
586 CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
5010f3db
MD		 587 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
588 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
170c7ab5 589 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
ad054cbd 590 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
48609533 591 CLKDEV_DEV_ID("e6820000.i2c", &mstp_clks[MSTP116]), /* I2C0 */
ad054cbd 592 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
6d9598e2 593 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
32103c7b 594 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */
832290b2 595 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* MP-DMAC */
6d9598e2
MD		 596 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
597 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
598 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
599 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
600 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
601 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
602 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
603 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
604 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
ea7e1a5a 605 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
a33bb8a2 606 CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
b028f94b 607 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
48609533 608 CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
12a7cfef 609 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
fb66c523 610 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
df2ddd7b 611 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
fb66c523 612 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
df2ddd7b 613 CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
6bf45a10 614 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
93301f5d 615 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
fb66c523 616 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
df2ddd7b 617 CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
33661c9e
MD		 618 CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
619 CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
620 CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
621 CLKDEV_DEV_ID("leds-renesas-tpu.41", &mstp_clks[MSTP300]), /* TPU4 */
b028f94b 622 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
48609533 623 CLKDEV_DEV_ID("e6826000.i2c", &mstp_clks[MSTP411]), /* I2C3 */
b028f94b 624 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
48609533 625 CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */
019c4ae3 626 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
6d9598e2
MD		 627};
628
629void __init sh73a0_clock_init(void)
630{
631 int k, ret = 0;
632
fb66c523
MD		 633 /* Set SDHI clocks to a known state */
634 __raw_writel(0x108, SD0CKCR);
635 __raw_writel(0x108, SD1CKCR);
636 __raw_writel(0x108, SD2CKCR);
637
f6d84f4a 638 /* detect main clock parent */
86d84083 639 switch ((__raw_readl(CKSCR) >> 28) & 0x03) {
f6d84f4a
MD		 640 case 0:
641 main_clk.parent = &sh73a0_extal1_clk;
642 break;
643 case 1:
644 main_clk.parent = &extal1_div2_clk;
645 break;
646 case 2:
647 main_clk.parent = &sh73a0_extal2_clk;
648 break;
649 case 3:
650 main_clk.parent = &extal2_div2_clk;
651 break;
652 }
653
6d9598e2
MD		 654 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
655 ret = clk_register(main_clks[k]);
656
f6d84f4a
MD		 657 if (!ret)
658 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
659
660 if (!ret)
d4775356 661 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
f6d84f4a 662
6d9598e2 663 if (!ret)
64e9de2f 664 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
6d9598e2 665
f5948bac
KM		 666 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
667 ret = clk_register(late_main_clks[k]);
668
6d9598e2
MD		 669 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
670
671 if (!ret)
6b6a4c06 672 shmobile_clk_init();
6d9598e2
MD		 673 else
674 panic("failed to setup sh73a0 clocks\n");
675}
Linux kernel - Deliverables
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