[deliverable/linux.git] / arch / arm / mach-shmobile / headsmp-scu.S

/*
 * Shared SCU setup for mach-shmobile
 *
 * Copyright (C) 2012 Bastian Hecht
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/memory.h>

	__CPUINIT
/*
 * Boot code for secondary CPUs.
 *
 * First we turn on L1 cache coherency for our CPU. Then we jump to
 * shmobile_invalidate_start that invalidates the cache and hands over control
 * to the common ARM startup code.
 */
ENTRY(shmobile_boot_scu)
					@ r0 = SCU base address
	mrc     p15, 0, r1, c0, c0, 5	@ read MIPDR
	and	r1, r1, #3		@ mask out cpu ID
	lsl	r1, r1, #3		@ we will shift by cpu_id * 8 bits
	ldr	r2, [r0, #8]		@ SCU Power Status Register
	mov	r3, #3
	bic	r2, r2, r3, lsl r1	@ Clear bits of our CPU (Run Mode)
	str	r2, [r0, #8]		@ write back

	b	shmobile_invalidate_start
ENDPROC(shmobile_boot_scu)

	.text
	.globl	shmobile_scu_base
shmobile_scu_base:
	.space	4
Commit	Line	Data
ec0d84a8 MD	1	/*
	2	* Shared SCU setup for mach-shmobile
	3	*
	4	* Copyright (C) 2012 Bastian Hecht
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#include <linux/linkage.h>
	23	#include <linux/init.h>
	24	#include <asm/memory.h>
	25
	26	__CPUINIT
	27	/*
4f6da36f	28	* Boot code for secondary CPUs.
ec0d84a8 MD	29	*
	30	* First we turn on L1 cache coherency for our CPU. Then we jump to
	31	* shmobile_invalidate_start that invalidates the cache and hands over control
	32	* to the common ARM startup code.
ec0d84a8	33	*/
bfabbcc6 MD	34	ENTRY(shmobile_boot_scu)
	35	@ r0 = SCU base address
	36	mrc p15, 0, r1, c0, c0, 5 @ read MIPDR
	37	and r1, r1, #3 @ mask out cpu ID
	38	lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
	39	ldr r2, [r0, #8] @ SCU Power Status Register
	40	mov r3, #3
	41	bic r2, r2, r3, lsl r1 @ Clear bits of our CPU (Run Mode)
	42	str r2, [r0, #8] @ write back
	43
	44	b shmobile_invalidate_start
	45	ENDPROC(shmobile_boot_scu)
	46
4c822845 MD	47	.text
	48	.globl shmobile_scu_base
	49	shmobile_scu_base:
	50	.space 4