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6c01ba44 KM |
1 | /* |
2 | * R8A7740 processor support | |
3 | * | |
4 | * Copyright (C) 2011 Renesas Solutions Corp. | |
5 | * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | */ | |
20 | ||
215d6cc9 | 21 | #include <linux/init.h> |
6c01ba44 | 22 | #include <linux/io.h> |
f9b4df4a | 23 | #include <linux/irqchip.h> |
0b7d7820 | 24 | #include <linux/irqchip/arm-gic.h> |
6c01ba44 | 25 | |
f9b4df4a | 26 | static void __init r8a7740_init_irq_common(void) |
6c01ba44 | 27 | { |
0b7d7820 BH |
28 | void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); |
29 | void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); | |
30 | void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); | |
31 | ||
0b7d7820 BH |
32 | /* route signals to GIC */ |
33 | iowrite32(0x0, pfc_inta_ctrl); | |
34 | ||
35 | /* | |
36 | * To mask the shared interrupt to SPI 149 we must ensure to set | |
37 | * PRIO *and* MASK. Else we run into IRQ floods when registering | |
38 | * the intc_irqpin devices | |
39 | */ | |
40 | iowrite32(0x0, intc_prio_base + 0x0); | |
41 | iowrite32(0x0, intc_prio_base + 0x4); | |
42 | iowrite32(0x0, intc_prio_base + 0x8); | |
43 | iowrite32(0x0, intc_prio_base + 0xc); | |
44 | iowrite8(0xff, intc_msk_base + 0x0); | |
45 | iowrite8(0xff, intc_msk_base + 0x4); | |
46 | iowrite8(0xff, intc_msk_base + 0x8); | |
47 | iowrite8(0xff, intc_msk_base + 0xc); | |
48 | ||
49 | iounmap(intc_prio_base); | |
50 | iounmap(intc_msk_base); | |
51 | iounmap(pfc_inta_ctrl); | |
6c01ba44 | 52 | } |
f9b4df4a BH |
53 | |
54 | void __init r8a7740_init_irq_of(void) | |
55 | { | |
56 | irqchip_init(); | |
57 | r8a7740_init_irq_common(); | |
58 | } | |
59 | ||
60 | void __init r8a7740_init_irq(void) | |
61 | { | |
62 | void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000); | |
63 | void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000); | |
64 | ||
65 | /* initialize the Generic Interrupt Controller PL390 r0p0 */ | |
66 | gic_init(0, 29, gic_dist_base, gic_cpu_base); | |
67 | r8a7740_init_irq_common(); | |
68 | } |