projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f411fade MD |
1 | /* |
| 2 | * r8a7779 processor support - INTC hardware block | |
| 3 | * | |
| 4 | * Copyright (C) 2011 Renesas Solutions Corp. | |
| 5 | * Copyright (C) 2011 Magnus Damm | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License as published by | |
| 9 | * the Free Software Foundation; version 2 of the License. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * GNU General Public License for more details. | |
| 15 | * | |
| 16 | * You should have received a copy of the GNU General Public License | |
| 17 | * along with this program; if not, write to the Free Software | |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
| 19 | */ | |
| 20 | #include <linux/kernel.h> | |
| 21 | #include <linux/init.h> | |
| 8e56e6d5 | 22 | #include <linux/platform_device.h> |
| f411fade MD |
23 | #include <linux/interrupt.h> |
| 24 | #include <linux/irq.h> | |
| 25 | #include <linux/io.h> | |
| 520f7bd7 | 26 | #include <linux/irqchip/arm-gic.h> |
| 8e56e6d5 | 27 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> |
| c58a1545 | 28 | #include <linux/irqchip.h> |
| 8e56e6d5 | 29 | #include <mach/common.h> |
| f411fade | 30 | #include <mach/intc.h> |
| 8e56e6d5 | 31 | #include <mach/irqs.h> |
| f411fade | 32 | #include <mach/r8a7779.h> |
| f411fade MD |
33 | #include <asm/mach-types.h> |
| 34 | #include <asm/mach/arch.h> | |
| 35 | ||
| 0a4b04dc AB |
36 | #define INT2SMSKCR0 IOMEM(0xfe7822a0) |
| 37 | #define INT2SMSKCR1 IOMEM(0xfe7822a4) | |
| 38 | #define INT2SMSKCR2 IOMEM(0xfe7822a8) | |
| 39 | #define INT2SMSKCR3 IOMEM(0xfe7822ac) | |
| 40 | #define INT2SMSKCR4 IOMEM(0xfe7822b0) | |
| f411fade | 41 | |
| 0a4b04dc AB |
42 | #define INT2NTSR0 IOMEM(0xfe700060) |
| 43 | #define INT2NTSR1 IOMEM(0xfe700064) | |
| 86f887c1 | 44 | |
| 7c9e3c7a | 45 | static struct renesas_intc_irqpin_config irqpin0_platform_data = { |
| 8e56e6d5 MD |
46 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ |
| 47 | .sense_bitfield_width = 2, | |
| 48 | }; | |
| 49 | ||
| 50 | static struct resource irqpin0_resources[] = { | |
| 51 | DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ | |
| 52 | DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ | |
| 53 | DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ | |
| 54 | DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ | |
| 55 | DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ | |
| 56 | DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ | |
| 57 | DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ | |
| 58 | DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ | |
| 59 | DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ | |
| 60 | }; | |
| 61 | ||
| 62 | static struct platform_device irqpin0_device = { | |
| 63 | .name = "renesas_intc_irqpin", | |
| 64 | .id = 0, | |
| 65 | .resource = irqpin0_resources, | |
| 66 | .num_resources = ARRAY_SIZE(irqpin0_resources), | |
| 67 | .dev = { | |
| 68 | .platform_data = &irqpin0_platform_data, | |
| 69 | }, | |
| 70 | }; | |
| 71 | ||
| 72 | void __init r8a7779_init_irq_extpin(int irlm) | |
| 73 | { | |
| 74 | void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); | |
| 75 | unsigned long tmp; | |
| 76 | ||
| 77 | if (icr0) { | |
| 78 | tmp = ioread32(icr0); | |
| 79 | if (irlm) | |
| 80 | tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ | |
| 81 | else | |
| 82 | tmp &= ~(1 << 23); /* IRL mode - not supported */ | |
| 83 | tmp |= (1 << 21); /* LVLMODE = 1 */ | |
| 84 | iowrite32(tmp, icr0); | |
| 85 | iounmap(icr0); | |
| 86 | ||
| 87 | if (irlm) | |
| 88 | platform_device_register(&irqpin0_device); | |
| 89 | } else | |
| 90 | pr_warn("r8a7779: unable to setup external irq pin mode\n"); | |
| 91 | } | |
| 92 | ||
| f411fade MD |
93 | static int r8a7779_set_wake(struct irq_data *data, unsigned int on) |
| 94 | { | |
| 95 | return 0; /* always allow wakeup */ | |
| 96 | } | |
| 97 | ||
| c58a1545 | 98 | static void __init r8a7779_init_irq_common(void) |
| f411fade | 99 | { |
| f411fade MD |
100 | gic_arch_extn.irq_set_wake = r8a7779_set_wake; |
| 101 | ||
| 86f887c1 PE |
102 | /* route all interrupts to ARM */ |
| 103 | __raw_writel(0xffffffff, INT2NTSR0); | |
| 104 | __raw_writel(0x3fffffff, INT2NTSR1); | |
| 105 | ||
| f411fade MD |
106 | /* unmask all known interrupts in INTCS2 */ |
| 107 | __raw_writel(0xfffffff0, INT2SMSKCR0); | |
| 108 | __raw_writel(0xfff7ffff, INT2SMSKCR1); | |
| 109 | __raw_writel(0xfffbffdf, INT2SMSKCR2); | |
| 110 | __raw_writel(0xbffffffc, INT2SMSKCR3); | |
| 111 | __raw_writel(0x003fee3f, INT2SMSKCR4); | |
| 112 | } | |
| c58a1545 SH |
113 | |
| 114 | void __init r8a7779_init_irq(void) | |
| 115 | { | |
| 116 | void __iomem *gic_dist_base = IOMEM(0xf0001000); | |
| 117 | void __iomem *gic_cpu_base = IOMEM(0xf0000100); | |
| 118 | ||
| 119 | /* use GIC to handle interrupts */ | |
| 120 | gic_init(0, 29, gic_dist_base, gic_cpu_base); | |
| 121 | ||
| 122 | r8a7779_init_irq_common(); | |
| 123 | } | |
| 124 | ||
| 125 | #ifdef CONFIG_OF | |
| 126 | void __init r8a7779_init_irq_dt(void) | |
| 127 | { | |
| 128 | irqchip_init(); | |
| 129 | r8a7779_init_irq_common(); | |
| 130 | } | |
| 131 | #endif |