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5f53a56a MD |
1 | /* |
2 | * sh73a0 processor support - INTC hardware block | |
3 | * | |
4 | * Copyright (C) 2010 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
5f53a56a MD |
14 | */ |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/interrupt.h> | |
e2c31b3f | 18 | #include <linux/module.h> |
5f53a56a MD |
19 | #include <linux/irq.h> |
20 | #include <linux/io.h> | |
a3f22db5 | 21 | #include <linux/irqchip.h> |
520f7bd7 | 22 | #include <linux/irqchip/arm-gic.h> |
ded59d6d | 23 | |
5f53a56a MD |
24 | #include <asm/mach-types.h> |
25 | #include <asm/mach/arch.h> | |
ded59d6d | 26 | |
6200e2c1 | 27 | #include "intc.h" |
b6bab126 | 28 | #include "irqs.h" |
ded59d6d | 29 | #include "sh73a0.h" |
5f53a56a MD |
30 | |
31 | enum { | |
32 | UNUSED = 0, | |
33 | ||
34 | /* interrupt sources INTCS */ | |
35 | PINTCS_PINT1, PINTCS_PINT2, | |
36 | RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3, | |
37 | CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0, | |
38 | RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR, | |
39 | KEYSC_KEY, VINT, MSIOF, | |
40 | TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02, | |
41 | CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2, | |
42 | CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC, | |
43 | RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9, | |
44 | RTDMAC_3_DEI10, RTDMAC_3_DEI11, | |
45 | FRC, GCU, LCDC1, CSIRX, | |
46 | DSITX0_DSITX00, DSITX0_DSITX01, | |
47 | SPU2_SPU0, SPU2_SPU1, FSI, | |
48 | TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, | |
49 | TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW, | |
50 | VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11, | |
51 | DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I, | |
52 | MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I, | |
53 | SPUV, | |
54 | ||
55 | /* interrupt groups INTCS */ | |
56 | RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3, | |
57 | DSITX0, SPU2, TMU1, MSU, | |
58 | }; | |
59 | ||
60 | static struct intc_vect intcs_vectors[] = { | |
61 | INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620), | |
62 | INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820), | |
63 | INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860), | |
64 | INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900), | |
65 | INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980), | |
66 | INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0), | |
67 | INTCS_VECT(_2DDMAC_2DDM0, 0x0a00), | |
68 | INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0), | |
69 | INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0), | |
70 | INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80), | |
71 | INTCS_VECT(MSIOF, 0x0d20), | |
72 | INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0), | |
73 | INTCS_VECT(TMU0_TUNI02, 0x0ec0), | |
74 | INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20), | |
75 | INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60), | |
76 | INTCS_VECT(MSUG, 0x0f80), | |
77 | INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0), | |
78 | INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440), | |
79 | INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0), | |
80 | INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560), | |
81 | INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0), | |
82 | INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320), | |
83 | INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360), | |
84 | INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0), | |
85 | INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760), | |
86 | INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0), | |
87 | INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0), | |
88 | INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820), | |
89 | INTCS_VECT(FSI, 0x1840), | |
90 | INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920), | |
91 | INTCS_VECT(TMU1_TUNI12, 0x1940), | |
92 | INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980), | |
93 | INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20), | |
94 | INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00), | |
95 | INTCS_VECT(SCUW, 0x1b40), | |
96 | INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80), | |
97 | INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0), | |
98 | INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20), | |
99 | INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60), | |
100 | INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0), | |
101 | INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0), | |
102 | INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20), | |
103 | INTCS_VECT(SPUV, 0x2300), | |
104 | }; | |
105 | ||
106 | static struct intc_group intcs_groups[] __initdata = { | |
107 | INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1, | |
108 | RTDMAC_0_DEI2, RTDMAC_0_DEI3), | |
109 | INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR), | |
110 | INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7, | |
111 | RTDMAC_2_DEI8, RTDMAC_2_DEI9), | |
112 | INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11), | |
113 | INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10), | |
114 | INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01), | |
115 | INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), | |
116 | INTC_GROUP(MSU, MSU_MSU, MSU_MSU2), | |
117 | }; | |
118 | ||
119 | static struct intc_mask_reg intcs_mask_registers[] = { | |
120 | { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */ | |
121 | { 0, 0, 0, CEU, | |
122 | 0, 0, 0, 0 } }, | |
123 | { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */ | |
124 | { 0, 0, 0, VPU, | |
125 | BBIF2, 0, 0, MFI } }, | |
126 | { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */ | |
127 | { 0, 0, 0, _2DDMAC_2DDM0, | |
128 | 0, ASA, PEP, ICB } }, | |
129 | { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */ | |
130 | { 0, 0, 0, CTI, | |
131 | JPU_JPEG, 0, LCRC, LCDC } }, | |
132 | { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */ | |
133 | { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4, | |
134 | RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } }, | |
135 | { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ | |
136 | { 0, 0, MSIOF, 0, | |
137 | _3DG_SGX543, 0, 0, 0 } }, | |
138 | { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ | |
139 | { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00, | |
140 | 0, 0, 0, 0 } }, | |
141 | { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */ | |
142 | { 0, 0, 0, 0, | |
143 | 0, MSU_MSU, MSU_MSU2, MSUG } }, | |
144 | { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */ | |
145 | { 0, RWDT0, CMT2, CMT0, | |
146 | 0, 0, 0, 0 } }, | |
147 | { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */ | |
148 | { 0, 0, 0, 0, | |
149 | 0, TSIF1, LMB, TSIF0 } }, | |
150 | { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */ | |
151 | { 0, 0, 0, 0, | |
152 | 0, 0, PINTCS_PINT2, PINTCS_PINT1 } }, | |
153 | { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */ | |
154 | { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9, | |
155 | RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } }, | |
156 | { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */ | |
157 | { FRC, 0, 0, GCU, | |
158 | LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } }, | |
159 | { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */ | |
160 | { SPU2_SPU0, SPU2_SPU1, FSI, 0, | |
161 | 0, 0, 0, 0 } }, | |
162 | { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */ | |
163 | { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0, | |
164 | TSIF2, CMT4, 0, 0 } }, | |
165 | { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */ | |
166 | { MFIS2, CPORTS2R, 0, 0, | |
167 | 0, 0, 0, TSG } }, | |
168 | { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */ | |
169 | { DMASCH1, 0, SCUW, VIO60, | |
170 | VIO61, CEU21, 0, CSI21 } }, | |
171 | { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */ | |
172 | { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV, | |
173 | EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } }, | |
174 | { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */ | |
175 | { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0, | |
176 | 0, 0, 0, 0 } }, | |
177 | { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */ | |
178 | { SPUV, 0, 0, 0, | |
179 | 0, 0, 0, 0 } }, | |
180 | }; | |
181 | ||
182 | /* Priority is needed for INTCA to receive the INTCS interrupt */ | |
183 | static struct intc_prio_reg intcs_prio_registers[] = { | |
184 | { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } }, | |
185 | { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } }, | |
186 | { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } }, | |
187 | { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2, | |
188 | 0, 0 } }, | |
189 | { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } }, | |
190 | { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1, | |
191 | CMT2, CMT0 } }, | |
192 | { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01, | |
193 | TMU0_TUNI02, TSIF1 } }, | |
194 | { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } }, | |
195 | { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } }, | |
196 | { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } }, | |
197 | { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } }, | |
198 | { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } }, | |
199 | { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } }, | |
200 | { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } }, | |
201 | { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } }, | |
202 | { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } }, | |
203 | { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } }, | |
204 | { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } }, | |
205 | { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } }, | |
206 | { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } }, | |
207 | { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } }, | |
208 | { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } }, | |
209 | { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11, | |
210 | DISP, DSRV } }, | |
211 | { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I, | |
212 | MSTIF0_MST00I, MSTIF0_MST01I } }, | |
213 | { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I, | |
214 | 0, 0 } }, | |
215 | { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } }, | |
216 | }; | |
217 | ||
218 | static struct resource intcs_resources[] __initdata = { | |
219 | [0] = { | |
220 | .start = 0xffd20000, | |
221 | .end = 0xffd201ff, | |
222 | .flags = IORESOURCE_MEM, | |
223 | }, | |
224 | [1] = { | |
225 | .start = 0xffd50000, | |
226 | .end = 0xffd501ff, | |
227 | .flags = IORESOURCE_MEM, | |
228 | }, | |
229 | [2] = { | |
230 | .start = 0xffd60000, | |
231 | .end = 0xffd601ff, | |
232 | .flags = IORESOURCE_MEM, | |
233 | } | |
234 | }; | |
235 | ||
236 | static struct intc_desc intcs_desc __initdata = { | |
237 | .name = "sh73a0-intcs", | |
238 | .resource = intcs_resources, | |
239 | .num_resources = ARRAY_SIZE(intcs_resources), | |
240 | .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, | |
241 | intcs_prio_registers, NULL, NULL), | |
242 | }; | |
243 | ||
244 | static struct irqaction sh73a0_intcs_cascade; | |
245 | ||
246 | static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id) | |
247 | { | |
248 | unsigned int evtcodeas = ioread32((void __iomem *)dev_id); | |
249 | ||
250 | generic_handle_irq(intcs_evt2irq(evtcodeas)); | |
251 | ||
252 | return IRQ_HANDLED; | |
253 | } | |
254 | ||
0a4b04dc AB |
255 | #define PINTER0_PHYS 0xe69000a0 |
256 | #define PINTER1_PHYS 0xe69000a4 | |
257 | #define PINTER0_VIRT IOMEM(0xe69000a0) | |
258 | #define PINTER1_VIRT IOMEM(0xe69000a4) | |
259 | #define PINTRR0 IOMEM(0xe69000d0) | |
260 | #define PINTRR1 IOMEM(0xe69000d4) | |
566aad39 MD |
261 | |
262 | #define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq)) | |
263 | #define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8)) | |
264 | #define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16)) | |
265 | #define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24)) | |
266 | #define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq)) | |
267 | ||
0a4b04dc | 268 | INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0", \ |
566aad39 MD |
269 | INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ |
270 | INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \ | |
271 | INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \ | |
272 | INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ | |
273 | INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D)); | |
274 | ||
0a4b04dc | 275 | INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1", \ |
566aad39 MD |
276 | INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \ |
277 | INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \ | |
278 | INTC_PINT_V_NONE, INTC_PINT_V_NONE, \ | |
279 | INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \ | |
280 | INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE); | |
281 | ||
282 | static struct irqaction sh73a0_pint0_cascade; | |
283 | static struct irqaction sh73a0_pint1_cascade; | |
284 | ||
0a4b04dc | 285 | static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq) |
566aad39 MD |
286 | { |
287 | unsigned long value = ioread32(rr) & ioread32(er); | |
288 | int k; | |
289 | ||
290 | for (k = 0; k < 32; k++) { | |
291 | if (value & (1 << (31 - k))) { | |
292 | generic_handle_irq(base_irq + k); | |
293 | iowrite32(~(1 << (31 - k)), rr); | |
294 | } | |
295 | } | |
296 | } | |
297 | ||
298 | static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id) | |
299 | { | |
0a4b04dc | 300 | pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0)); |
566aad39 MD |
301 | return IRQ_HANDLED; |
302 | } | |
303 | ||
304 | static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id) | |
305 | { | |
0a4b04dc | 306 | pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0)); |
566aad39 MD |
307 | return IRQ_HANDLED; |
308 | } | |
309 | ||
5f53a56a MD |
310 | void __init sh73a0_init_irq(void) |
311 | { | |
a2a47ca3 RH |
312 | void __iomem *gic_dist_base = IOMEM(0xf0001000); |
313 | void __iomem *gic_cpu_base = IOMEM(0xf0000100); | |
5f53a56a MD |
314 | void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); |
315 | ||
d04594c2 | 316 | gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE); |
bd1689cd | 317 | gic_init(0, 29, gic_dist_base, gic_cpu_base); |
5f53a56a MD |
318 | |
319 | register_intc_controller(&intcs_desc); | |
566aad39 MD |
320 | register_intc_controller(&intc_pint0_desc); |
321 | register_intc_controller(&intc_pint1_desc); | |
5f53a56a MD |
322 | |
323 | /* demux using INTEVTSA */ | |
324 | sh73a0_intcs_cascade.name = "INTCS cascade"; | |
325 | sh73a0_intcs_cascade.handler = sh73a0_intcs_demux; | |
326 | sh73a0_intcs_cascade.dev_id = intevtsa; | |
327 | setup_irq(gic_spi(50), &sh73a0_intcs_cascade); | |
a1993055 | 328 | |
566aad39 MD |
329 | /* PINT pins are sanely tied to the GIC as SPI */ |
330 | sh73a0_pint0_cascade.name = "PINT0 cascade"; | |
331 | sh73a0_pint0_cascade.handler = sh73a0_pint0_demux; | |
332 | setup_irq(gic_spi(33), &sh73a0_pint0_cascade); | |
333 | ||
334 | sh73a0_pint1_cascade.name = "PINT1 cascade"; | |
335 | sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; | |
336 | setup_irq(gic_spi(34), &sh73a0_pint1_cascade); | |
5f53a56a | 337 | } |