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a662c082 MD |
1 | /* |
2 | * r8a7779 Power management support | |
3 | * | |
4 | * Copyright (C) 2011 Renesas Solutions Corp. | |
5 | * Copyright (C) 2011 Magnus Damm | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
12 | #include <linux/pm.h> | |
13 | #include <linux/suspend.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/pm_clock.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/console.h> | |
21 | #include <asm/system.h> | |
22 | #include <asm/io.h> | |
23 | #include <mach/common.h> | |
24 | #include <mach/r8a7779.h> | |
25 | ||
26 | static void __iomem *r8a7779_sysc_base; | |
27 | ||
28 | /* SYSC */ | |
29 | #define SYSCSR 0x00 | |
30 | #define SYSCISR 0x04 | |
31 | #define SYSCISCR 0x08 | |
32 | #define SYSCIER 0x0c | |
33 | #define SYSCIMR 0x10 | |
34 | #define PWRSR0 0x40 | |
35 | #define PWRSR1 0x80 | |
36 | #define PWRSR2 0xc0 | |
37 | #define PWRSR3 0x100 | |
38 | #define PWRSR4 0x140 | |
39 | ||
40 | #define PWRSR_OFFS 0x00 | |
41 | #define PWROFFCR_OFFS 0x04 | |
42 | #define PWRONCR_OFFS 0x0c | |
43 | #define PWRER_OFFS 0x14 | |
44 | ||
45 | #define SYSCSR_RETRIES 100 | |
46 | #define SYSCSR_DELAY_US 1 | |
47 | ||
48 | #define SYSCISR_RETRIES 1000 | |
49 | #define SYSCISR_DELAY_US 1 | |
50 | ||
51 | #ifdef CONFIG_PM | |
52 | ||
53 | static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch, | |
54 | int sr_bit, int reg_offs) | |
55 | { | |
56 | int k; | |
57 | ||
58 | for (k = 0; k < SYSCSR_RETRIES; k++) { | |
59 | if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit)) | |
60 | break; | |
61 | udelay(SYSCSR_DELAY_US); | |
62 | } | |
63 | ||
64 | if (k == SYSCSR_RETRIES) | |
65 | return -EAGAIN; | |
66 | ||
67 | iowrite32(1 << r8a7779_ch->chan_bit, | |
68 | r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs); | |
69 | ||
70 | return 0; | |
71 | } | |
72 | ||
73 | static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch) | |
74 | { | |
75 | return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS); | |
76 | } | |
77 | ||
78 | static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch) | |
79 | { | |
80 | return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS); | |
81 | } | |
82 | ||
83 | static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch, | |
84 | int (*on_off_fn)(struct r8a7779_pm_ch *)) | |
85 | { | |
86 | unsigned int isr_mask = 1 << r8a7779_ch->isr_bit; | |
87 | unsigned int chan_mask = 1 << r8a7779_ch->chan_bit; | |
88 | unsigned int status; | |
89 | int ret = 0; | |
90 | int k; | |
91 | ||
92 | iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR); | |
93 | ||
94 | do { | |
95 | ret = on_off_fn(r8a7779_ch); | |
96 | if (ret) | |
97 | goto out; | |
98 | ||
99 | status = ioread32(r8a7779_sysc_base + | |
100 | r8a7779_ch->chan_offs + PWRER_OFFS); | |
101 | } while (status & chan_mask); | |
102 | ||
103 | for (k = 0; k < SYSCISR_RETRIES; k++) { | |
104 | if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask) | |
105 | break; | |
106 | udelay(SYSCISR_DELAY_US); | |
107 | } | |
108 | ||
109 | if (k == SYSCISR_RETRIES) | |
110 | ret = -EIO; | |
111 | ||
112 | iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR); | |
113 | ||
114 | out: | |
115 | pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n", | |
116 | r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0), | |
117 | ioread32(r8a7779_sysc_base + PWRSR1), | |
118 | ioread32(r8a7779_sysc_base + PWRSR2), | |
119 | ioread32(r8a7779_sysc_base + PWRSR3), | |
120 | ioread32(r8a7779_sysc_base + PWRSR4), ret); | |
121 | return ret; | |
122 | } | |
123 | ||
124 | static int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch) | |
125 | { | |
126 | return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off); | |
127 | } | |
128 | ||
129 | static int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch) | |
130 | { | |
131 | return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on); | |
132 | } | |
133 | ||
134 | static void __init r8a7779_sysc_init(void) | |
135 | { | |
136 | r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE); | |
137 | if (!r8a7779_sysc_base) | |
138 | panic("unable to ioremap r8a7779 SYSC hardware block\n"); | |
139 | ||
140 | /* enable all interrupt sources, but do not use interrupt handler */ | |
141 | iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER); | |
142 | iowrite32(0, r8a7779_sysc_base + SYSCIMR); | |
143 | } | |
144 | ||
145 | static int pd_power_down(struct generic_pm_domain *genpd) | |
146 | { | |
147 | return r8a7779_sysc_power_down(to_r8a7779_ch(genpd)); | |
148 | } | |
149 | ||
150 | static int pd_power_up(struct generic_pm_domain *genpd) | |
151 | { | |
152 | return r8a7779_sysc_power_up(to_r8a7779_ch(genpd)); | |
153 | } | |
154 | ||
155 | static bool pd_is_off(struct generic_pm_domain *genpd) | |
156 | { | |
157 | struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd); | |
158 | unsigned int st; | |
159 | ||
160 | st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS); | |
161 | if (st & (1 << r8a7779_ch->chan_bit)) | |
162 | return true; | |
163 | ||
164 | return false; | |
165 | } | |
166 | ||
167 | static bool pd_active_wakeup(struct device *dev) | |
168 | { | |
169 | return true; | |
170 | } | |
171 | ||
172 | void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd) | |
173 | { | |
174 | struct generic_pm_domain *genpd = &r8a7779_pd->genpd; | |
175 | ||
176 | pm_genpd_init(genpd, NULL, false); | |
177 | genpd->dev_ops.stop = pm_clk_suspend; | |
178 | genpd->dev_ops.start = pm_clk_resume; | |
179 | genpd->dev_ops.active_wakeup = pd_active_wakeup; | |
180 | genpd->dev_irq_safe = true; | |
181 | genpd->power_off = pd_power_down; | |
182 | genpd->power_on = pd_power_up; | |
183 | ||
184 | if (pd_is_off(&r8a7779_pd->genpd)) | |
185 | pd_power_up(&r8a7779_pd->genpd); | |
186 | } | |
187 | ||
188 | void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd, | |
189 | struct platform_device *pdev) | |
190 | { | |
191 | struct device *dev = &pdev->dev; | |
192 | ||
193 | pm_genpd_add_device(&r8a7779_pd->genpd, dev); | |
194 | if (pm_clk_no_clocks(dev)) | |
195 | pm_clk_add(dev, NULL); | |
196 | } | |
197 | ||
198 | struct r8a7779_pm_domain r8a7779_sh4a = { | |
199 | .ch = { | |
200 | .chan_offs = 0x80, /* PWRSR1 .. PWRER1 */ | |
201 | .isr_bit = 16, /* SH4A */ | |
202 | } | |
203 | }; | |
204 | ||
205 | struct r8a7779_pm_domain r8a7779_sgx = { | |
206 | .ch = { | |
207 | .chan_offs = 0xc0, /* PWRSR2 .. PWRER2 */ | |
208 | .isr_bit = 20, /* SGX */ | |
209 | } | |
210 | }; | |
211 | ||
212 | struct r8a7779_pm_domain r8a7779_vdp1 = { | |
213 | .ch = { | |
214 | .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */ | |
215 | .isr_bit = 21, /* VDP */ | |
216 | } | |
217 | }; | |
218 | ||
219 | struct r8a7779_pm_domain r8a7779_impx3 = { | |
220 | .ch = { | |
221 | .chan_offs = 0x140, /* PWRSR4 .. PWRER4 */ | |
222 | .isr_bit = 24, /* IMP */ | |
223 | } | |
224 | }; | |
225 | ||
226 | #else /* CONFIG_PM */ | |
227 | ||
228 | static inline void r8a7779_sysc_init(void) {} | |
229 | ||
230 | #endif /* CONFIG_PM */ | |
231 | ||
232 | void __init r8a7779_pm_init(void) | |
233 | { | |
234 | r8a7779_sysc_init(); | |
235 | } |