[deliverable/linux.git] / arch / arm / mach-shmobile / pm-rcar.c

/*
 * R-Car SYSC Power management support
 *
 * Copyright (C) 2014  Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/delay.h>
#include <linux/err.h>
#include <linux/mm.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include "pm-rcar.h"

/* SYSC Common */
#define SYSCSR			0x00	/* SYSC Status Register */
#define SYSCISR			0x04	/* Interrupt Status Register */
#define SYSCISCR		0x08	/* Interrupt Status Clear Register */
#define SYSCIER			0x0c	/* Interrupt Enable Register */
#define SYSCIMR			0x10	/* Interrupt Mask Register */

/* SYSC Status Register */
#define SYSCSR_PONENB		1	/* Ready for power resume requests */
#define SYSCSR_POFFENB		0	/* Ready for power shutoff requests */

/*
 * Power Control Register Offsets inside the register block for each domain
 * Note: The "CR" registers for ARM cores exist on H1 only
 *       Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
 */
#define PWRSR_OFFS		0x00	/* Power Status Register */
#define PWROFFCR_OFFS		0x04	/* Power Shutoff Control Register */
#define PWROFFSR_OFFS		0x08	/* Power Shutoff Status Register */
#define PWRONCR_OFFS		0x0c	/* Power Resume Control Register */
#define PWRONSR_OFFS		0x10	/* Power Resume Status Register */
#define PWRER_OFFS		0x14	/* Power Shutoff/Resume Error */


#define SYSCSR_RETRIES		100
#define SYSCSR_DELAY_US		1

#define PWRER_RETRIES		100
#define PWRER_DELAY_US		1

#define SYSCISR_RETRIES		1000
#define SYSCISR_DELAY_US	1

static void __iomem *rcar_sysc_base;
static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */

static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
{
	unsigned int sr_bit, reg_offs;
	int k;

	if (on) {
		sr_bit = SYSCSR_PONENB;
		reg_offs = PWRONCR_OFFS;
	} else {
		sr_bit = SYSCSR_POFFENB;
		reg_offs = PWROFFCR_OFFS;
	}

	/* Wait until SYSC is ready to accept a power request */
	for (k = 0; k < SYSCSR_RETRIES; k++) {
		if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
			break;
		udelay(SYSCSR_DELAY_US);
	}

	if (k == SYSCSR_RETRIES)
		return -EAGAIN;

	/* Submit power shutoff or power resume request */
	iowrite32(BIT(sysc_ch->chan_bit),
		  rcar_sysc_base + sysc_ch->chan_offs + reg_offs);

	return 0;
}

static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
{
	unsigned int isr_mask = BIT(sysc_ch->isr_bit);
	unsigned int chan_mask = BIT(sysc_ch->chan_bit);
	unsigned int status;
	unsigned long flags;
	int ret = 0;
	int k;

	spin_lock_irqsave(&rcar_sysc_lock, flags);

	iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);

	/* Submit power shutoff or resume request until it was accepted */
	for (k = 0; k < PWRER_RETRIES; k++) {
		ret = rcar_sysc_pwr_on_off(sysc_ch, on);
		if (ret)
			goto out;

		status = ioread32(rcar_sysc_base +
				  sysc_ch->chan_offs + PWRER_OFFS);
		if (!(status & chan_mask))
			break;

		udelay(PWRER_DELAY_US);
	}

	if (k == PWRER_RETRIES) {
		ret = -EIO;
		goto out;
	}

	/* Wait until the power shutoff or resume request has completed * */
	for (k = 0; k < SYSCISR_RETRIES; k++) {
		if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
			break;
		udelay(SYSCISR_DELAY_US);
	}

	if (k == SYSCISR_RETRIES)
		ret = -EIO;

	iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);

 out:
	spin_unlock_irqrestore(&rcar_sysc_lock, flags);

	pr_debug("sysc power domain %d: %08x -> %d\n",
		 sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
	return ret;
}

int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)
{
	return rcar_sysc_power(sysc_ch, false);
}

int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)
{
	return rcar_sysc_power(sysc_ch, true);
}

bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
{
	unsigned int st;

	st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
	if (st & BIT(sysc_ch->chan_bit))
		return true;

	return false;
}

void __iomem *rcar_sysc_init(phys_addr_t base)
{
	rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
	if (!rcar_sysc_base)
		panic("unable to ioremap R-Car SYSC hardware block\n");

	return rcar_sysc_base;
}
Commit	Line	Data
a6557eb7 MD	1	/*
	2	* R-Car SYSC Power management support
	3	*
	4	* Copyright (C) 2014 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#include <linux/delay.h>
	12	#include <linux/err.h>
	13	#include <linux/mm.h>
	14	#include <linux/spinlock.h>
2584cf83	15	#include <linux/io.h>
585c09df	16	#include "pm-rcar.h"
a6557eb7	17
577d104d GU	18	/* SYSC Common */
	19	#define SYSCSR 0x00 /* SYSC Status Register */
	20	#define SYSCISR 0x04 /* Interrupt Status Register */
	21	#define SYSCISCR 0x08 /* Interrupt Status Clear Register */
	22	#define SYSCIER 0x0c /* Interrupt Enable Register */
	23	#define SYSCIMR 0x10 /* Interrupt Mask Register */
a6557eb7	24
577d104d GU	25	/* SYSC Status Register */
	26	#define SYSCSR_PONENB 1 /* Ready for power resume requests */
	27	#define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
a6557eb7	28
577d104d GU	29	/*
	30	* Power Control Register Offsets inside the register block for each domain
	31	* Note: The "CR" registers for ARM cores exist on H1 only
	32	* Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
	33	*/
	34	#define PWRSR_OFFS 0x00 /* Power Status Register */
	35	#define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
	36	#define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
	37	#define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
	38	#define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
	39	#define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
	40
	41
	42	#define SYSCSR_RETRIES 100
	43	#define SYSCSR_DELAY_US 1
a6557eb7	44
2f575fcf GU	45	#define PWRER_RETRIES 100
	46	#define PWRER_DELAY_US 1
	47
577d104d GU	48	#define SYSCISR_RETRIES 1000
577d104d GU	49	#define SYSCISR_DELAY_US 1
a6557eb7	50
c4ca5d80	51	static void __iomem *rcar_sysc_base;
a6557eb7 MD	52	static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
a6557eb7 MD	53
bcb82437	54	static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
a6557eb7	55	{
bcb82437	56	unsigned int sr_bit, reg_offs;
a6557eb7 MD	57	int k;
a6557eb7 MD	58
bcb82437 GU	59	if (on) {
	60	sr_bit = SYSCSR_PONENB;
	61	reg_offs = PWRONCR_OFFS;
	62	} else {
	63	sr_bit = SYSCSR_POFFENB;
	64	reg_offs = PWROFFCR_OFFS;
	65	}
	66
577d104d	67	/* Wait until SYSC is ready to accept a power request */
a6557eb7	68	for (k = 0; k < SYSCSR_RETRIES; k++) {
21437c53	69	if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
a6557eb7 MD	70	break;
	71	udelay(SYSCSR_DELAY_US);
	72	}
	73
	74	if (k == SYSCSR_RETRIES)
	75	return -EAGAIN;
	76
577d104d	77	/* Submit power shutoff or power resume request */
21437c53	78	iowrite32(BIT(sysc_ch->chan_bit),
a6557eb7 MD	79	rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
	80
	81	return 0;
	82	}
	83
bcb82437	84	static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
a6557eb7	85	{
21437c53 GU	86	unsigned int isr_mask = BIT(sysc_ch->isr_bit);
21437c53 GU	87	unsigned int chan_mask = BIT(sysc_ch->chan_bit);
a6557eb7 MD	88	unsigned int status;
	89	unsigned long flags;
	90	int ret = 0;
	91	int k;
	92
	93	spin_lock_irqsave(&rcar_sysc_lock, flags);
	94
	95	iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
	96
577d104d	97	/* Submit power shutoff or resume request until it was accepted */
2f575fcf	98	for (k = 0; k < PWRER_RETRIES; k++) {
bcb82437	99	ret = rcar_sysc_pwr_on_off(sysc_ch, on);
a6557eb7 MD	100	if (ret)
	101	goto out;
	102
	103	status = ioread32(rcar_sysc_base +
	104	sysc_ch->chan_offs + PWRER_OFFS);
2f575fcf GU	105	if (!(status & chan_mask))
	106	break;
	107
	108	udelay(PWRER_DELAY_US);
	109	}
	110
	111	if (k == PWRER_RETRIES) {
	112	ret = -EIO;
	113	goto out;
	114	}
a6557eb7	115
577d104d	116	/* Wait until the power shutoff or resume request has completed * */
a6557eb7 MD	117	for (k = 0; k < SYSCISR_RETRIES; k++) {
	118	if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
	119	break;
	120	udelay(SYSCISR_DELAY_US);
	121	}
	122
	123	if (k == SYSCISR_RETRIES)
	124	ret = -EIO;
	125
	126	iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
	127
	128	out:
	129	spin_unlock_irqrestore(&rcar_sysc_lock, flags);
	130
	131	pr_debug("sysc power domain %d: %08x -> %d\n",
	132	sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
	133	return ret;
	134	}
	135
624deb39	136	int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)
a6557eb7	137	{
bcb82437	138	return rcar_sysc_power(sysc_ch, false);
a6557eb7 MD	139	}
a6557eb7 MD	140
624deb39	141	int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)
a6557eb7	142	{
bcb82437	143	return rcar_sysc_power(sysc_ch, true);
a6557eb7 MD	144	}
a6557eb7 MD	145
624deb39	146	bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
a6557eb7 MD	147	{
	148	unsigned int st;
	149
	150	st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
21437c53	151	if (st & BIT(sysc_ch->chan_bit))
a6557eb7 MD	152	return true;
	153
	154	return false;
	155	}
	156
	157	void __iomem *rcar_sysc_init(phys_addr_t base)
	158	{
	159	rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
	160	if (!rcar_sysc_base)
	161	panic("unable to ioremap R-Car SYSC hardware block\n");
	162
	163	return rcar_sysc_base;
	164	}