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ARM: shmobile: r8a7779: Cleanup header file
[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7740.c
CommitLineData
6c01ba44
KM		 1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
6c01ba44 15 */
3841e6f5 16#include <linux/dma-mapping.h>
6c01ba44
KM		 17#include <linux/kernel.h>
18#include <linux/init.h>
6831f3a9 19#include <linux/io.h>
70e3f3d4
KM		 20#include <linux/irqchip.h>
21#include <linux/irqchip/arm-gic.h>
0b7d7820 22#include <linux/platform_data/irq-renesas-intc-irqpin.h>
6c01ba44 23#include <linux/platform_device.h>
755d57b2 24#include <linux/of_platform.h>
6c01ba44 25#include <linux/serial_sci.h>
643c3307 26#include <linux/sh_dma.h>
6c01ba44 27#include <linux/sh_timer.h>
f671e022 28#include <linux/platform_data/sh_ipmmu.h>
9e38b84b 29
6c01ba44 30#include <asm/mach-types.h>
d3ab7221 31#include <asm/mach/map.h>
6c01ba44 32#include <asm/mach/arch.h>
23e5bc03 33#include <asm/mach/time.h>
c41215b7 34#include <asm/hardware/cache-l2x0.h>
9e38b84b 35
fd44aa5e 36#include "common.h"
74ac0de8 37#include "dma-register.h"
b6bab126 38#include "irqs.h"
6b8b0cb4 39#include "pm-rmobile.h"
9e38b84b 40#include "r8a7740.h"
6c01ba44 41
d3ab7221
MD		 42static struct map_desc r8a7740_io_desc[] __initdata = {
43 /*
44 * for CPGA/INTC/PFC
45 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
46 */
47 {
48 .virtual = 0xe6000000,
49 .pfn = __phys_to_pfn(0xe6000000),
50 .length = 160 << 20,
51 .type = MT_DEVICE_NONSHARED
52 },
53#ifdef CONFIG_CACHE_L2X0
54 /*
55 * for l2x0_init()
56 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
57 */
58 {
59 .virtual = 0xf0002000,
60 .pfn = __phys_to_pfn(0xf0100000),
61 .length = PAGE_SIZE,
62 .type = MT_DEVICE_NONSHARED
63 },
64#endif
65};
66
67void __init r8a7740_map_io(void)
68{
7a2071c5 69 debug_ll_io_init();
d3ab7221
MD		 70 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
71}
72
02b01adb 73/* PFC */
3404622a
MD		 74static const struct resource pfc_resources[] = {
75 DEFINE_RES_MEM(0xe6050000, 0x8000),
76 DEFINE_RES_MEM(0xe605800c, 0x0020),
02b01adb
LP		 77};
78
79void __init r8a7740_pinmux_init(void)
80{
3404622a
MD		 81 platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
82 ARRAY_SIZE(pfc_resources));
02b01adb
LP		 83}
84
0b7d7820
BH		 85static struct renesas_intc_irqpin_config irqpin0_platform_data = {
86 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
87};
88
89static struct resource irqpin0_resources[] = {
90 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
91 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
92 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
93 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
94 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
95 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
96 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
97 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
98 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
99 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
100 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
101 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
102 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
103};
104
105static struct platform_device irqpin0_device = {
106 .name = "renesas_intc_irqpin",
107 .id = 0,
108 .resource = irqpin0_resources,
109 .num_resources = ARRAY_SIZE(irqpin0_resources),
110 .dev = {
111 .platform_data = &irqpin0_platform_data,
112 },
113};
114
115static struct renesas_intc_irqpin_config irqpin1_platform_data = {
116 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
117};
118
119static struct resource irqpin1_resources[] = {
120 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
121 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
122 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
123 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
124 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
125 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
126 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
127 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
128 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
129 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
130 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
131 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
132 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
133};
134
135static struct platform_device irqpin1_device = {
136 .name = "renesas_intc_irqpin",
137 .id = 1,
138 .resource = irqpin1_resources,
139 .num_resources = ARRAY_SIZE(irqpin1_resources),
140 .dev = {
141 .platform_data = &irqpin1_platform_data,
142 },
143};
144
145static struct renesas_intc_irqpin_config irqpin2_platform_data = {
146 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
147};
148
149static struct resource irqpin2_resources[] = {
150 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
151 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
152 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
153 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
154 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
155 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
156 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
157 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
158 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
159 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
160 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
161 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
162 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
163};
164
165static struct platform_device irqpin2_device = {
166 .name = "renesas_intc_irqpin",
167 .id = 2,
168 .resource = irqpin2_resources,
169 .num_resources = ARRAY_SIZE(irqpin2_resources),
170 .dev = {
171 .platform_data = &irqpin2_platform_data,
172 },
173};
174
175static struct renesas_intc_irqpin_config irqpin3_platform_data = {
176 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
177};
178
179static struct resource irqpin3_resources[] = {
180 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
181 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
182 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
183 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
184 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
185 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
186 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
187 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
188 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
189 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
190 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
191 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
192 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
193};
194
195static struct platform_device irqpin3_device = {
196 .name = "renesas_intc_irqpin",
197 .id = 3,
198 .resource = irqpin3_resources,
199 .num_resources = ARRAY_SIZE(irqpin3_resources),
200 .dev = {
201 .platform_data = &irqpin3_platform_data,
202 },
203};
204
c9e06d8e
LP		 205/* SCIF */
206#define R8A7740_SCIF(scif_type, index, baseaddr, irq) \
207static struct plat_sci_port scif##index##_platform_data = { \
208 .type = scif_type, \
c9e06d8e 209 .flags = UPF_BOOT_AUTOCONF, \
c9e06d8e
LP		 210 .scscr = SCSCR_RE | SCSCR_TE, \
211}; \
212 \
8bf2f8c5
LP		 213static struct resource scif##index##_resources[] = { \
214 DEFINE_RES_MEM(baseaddr, 0x100), \
215 DEFINE_RES_IRQ(irq), \
216}; \
217 \
c9e06d8e
LP		 218static struct platform_device scif##index##_device = { \
219 .name = "sh-sci", \
220 .id = index, \
8bf2f8c5
LP		 221 .resource = scif##index##_resources, \
222 .num_resources = ARRAY_SIZE(scif##index##_resources), \
c9e06d8e
LP		 223 .dev = { \
224 .platform_data = &scif##index##_platform_data, \
225 }, \
226}
6c01ba44 227
c9e06d8e
LP		 228R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
229R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
230R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
231R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
232R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
233R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
234R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
235R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
236R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
6c01ba44
KM		 237
238/* CMT */
e0ad56a3
LP		 239static struct sh_timer_config cmt1_platform_data = {
240 .channels_mask = 0x3f,
6c01ba44
KM		 241};
242
e0ad56a3
LP		 243static struct resource cmt1_resources[] = {
244 DEFINE_RES_MEM(0xe6138000, 0x170),
245 DEFINE_RES_IRQ(gic_spi(58)),
6c01ba44
KM		 246};
247
e0ad56a3
LP		 248static struct platform_device cmt1_device = {
249 .name = "sh-cmt-48",
250 .id = 1,
6c01ba44 251 .dev = {
e0ad56a3 252 .platform_data = &cmt1_platform_data,
6c01ba44 253 },
e0ad56a3
LP		 254 .resource = cmt1_resources,
255 .num_resources = ARRAY_SIZE(cmt1_resources),
6c01ba44
KM		 256};
257
e67d7afc 258/* TMU */
8ec72e46
LP		 259static struct sh_timer_config tmu0_platform_data = {
260 .channels_mask = 7,
e67d7afc
KM		 261};
262
8ec72e46
LP		 263static struct resource tmu0_resources[] = {
264 DEFINE_RES_MEM(0xfff80000, 0x2c),
265 DEFINE_RES_IRQ(gic_spi(198)),
266 DEFINE_RES_IRQ(gic_spi(199)),
267 DEFINE_RES_IRQ(gic_spi(200)),
e67d7afc
KM		 268};
269
8ec72e46
LP		 270static struct platform_device tmu0_device = {
271 .name = "sh-tmu",
e67d7afc
KM		 272 .id = 0,
273 .dev = {
8ec72e46 274 .platform_data = &tmu0_platform_data,
e67d7afc 275 },
8ec72e46
LP		 276 .resource = tmu0_resources,
277 .num_resources = ARRAY_SIZE(tmu0_resources),
e67d7afc
KM		 278};
279
f671e022
HE		 280/* IPMMUI (an IPMMU module for ICB/LMB) */
281static struct resource ipmmu_resources[] = {
282 [0] = {
283 .name = "IPMMUI",
284 .start = 0xfe951000,
285 .end = 0xfe9510ff,
286 .flags = IORESOURCE_MEM,
287 },
288};
289
290static const char * const ipmmu_dev_names[] = {
291 "sh_mobile_lcdc_fb.0",
292 "sh_mobile_lcdc_fb.1",
293 "sh_mobile_ceu.0",
294};
295
296static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
297 .dev_names = ipmmu_dev_names,
298 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
299};
300
301static struct platform_device ipmmu_device = {
302 .name = "ipmmu",
303 .id = -1,
304 .dev = {
305 .platform_data = &ipmmu_platform_data,
306 },
307 .resource = ipmmu_resources,
308 .num_resources = ARRAY_SIZE(ipmmu_resources),
309};
310
c4fac6f2 311static struct platform_device *r8a7740_early_devices[] __initdata = {
6c01ba44
KM		 312 &scif0_device,
313 &scif1_device,
314 &scif2_device,
315 &scif3_device,
316 &scif4_device,
317 &scif5_device,
318 &scif6_device,
319 &scif7_device,
c9e06d8e 320 &scif8_device,
744fdc8d
BH		 321 &irqpin0_device,
322 &irqpin1_device,
323 &irqpin2_device,
324 &irqpin3_device,
8ec72e46 325 &tmu0_device,
f671e022 326 &ipmmu_device,
1145eaab 327 &cmt1_device,
6c01ba44
KM		 328};
329
643c3307 330/* DMA */
643c3307
KM		 331static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
332 {
cb76eb81
KM		 333 .slave_id = SHDMA_SLAVE_SDHI0_TX,
334 .addr = 0xe6850030,
335 .chcr = CHCR_TX(XMIT_SZ_16BIT),
336 .mid_rid = 0xc1,
337 }, {
338 .slave_id = SHDMA_SLAVE_SDHI0_RX,
339 .addr = 0xe6850030,
340 .chcr = CHCR_RX(XMIT_SZ_16BIT),
341 .mid_rid = 0xc2,
342 }, {
343 .slave_id = SHDMA_SLAVE_SDHI1_TX,
344 .addr = 0xe6860030,
345 .chcr = CHCR_TX(XMIT_SZ_16BIT),
346 .mid_rid = 0xc9,
347 }, {
348 .slave_id = SHDMA_SLAVE_SDHI1_RX,
349 .addr = 0xe6860030,
350 .chcr = CHCR_RX(XMIT_SZ_16BIT),
351 .mid_rid = 0xca,
352 }, {
353 .slave_id = SHDMA_SLAVE_SDHI2_TX,
354 .addr = 0xe6870030,
355 .chcr = CHCR_TX(XMIT_SZ_16BIT),
356 .mid_rid = 0xcd,
357 }, {
358 .slave_id = SHDMA_SLAVE_SDHI2_RX,
359 .addr = 0xe6870030,
360 .chcr = CHCR_RX(XMIT_SZ_16BIT),
361 .mid_rid = 0xce,
362 }, {
643c3307
KM		 363 .slave_id = SHDMA_SLAVE_FSIA_TX,
364 .addr = 0xfe1f0024,
365 .chcr = CHCR_TX(XMIT_SZ_32BIT),
366 .mid_rid = 0xb1,
367 }, {
368 .slave_id = SHDMA_SLAVE_FSIA_RX,
369 .addr = 0xfe1f0020,
370 .chcr = CHCR_RX(XMIT_SZ_32BIT),
371 .mid_rid = 0xb2,
372 }, {
373 .slave_id = SHDMA_SLAVE_FSIB_TX,
374 .addr = 0xfe1f0064,
375 .chcr = CHCR_TX(XMIT_SZ_32BIT),
376 .mid_rid = 0xb5,
9a145624
GL		 377 }, {
378 .slave_id = SHDMA_SLAVE_MMCIF_TX,
379 .addr = 0xe6bd0034,
380 .chcr = CHCR_TX(XMIT_SZ_32BIT),
381 .mid_rid = 0xd1,
382 }, {
383 .slave_id = SHDMA_SLAVE_MMCIF_RX,
384 .addr = 0xe6bd0034,
385 .chcr = CHCR_RX(XMIT_SZ_32BIT),
386 .mid_rid = 0xd2,
643c3307
KM		 387 },
388};
389
390#define DMA_CHANNEL(a, b, c) \
391{ \
392 .offset = a, \
393 .dmars = b, \
394 .dmars_bit = c, \
395 .chclr_offset = (0x220 - 0x20) + a \
396}
397
398static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
399 DMA_CHANNEL(0x00, 0, 0),
400 DMA_CHANNEL(0x10, 0, 8),
401 DMA_CHANNEL(0x20, 4, 0),
402 DMA_CHANNEL(0x30, 4, 8),
403 DMA_CHANNEL(0x50, 8, 0),
404 DMA_CHANNEL(0x60, 8, 8),
405};
406
643c3307
KM		 407static struct sh_dmae_pdata dma_platform_data = {
408 .slave = r8a7740_dmae_slaves,
409 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
410 .channel = r8a7740_dmae_channels,
411 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
d7de938f
KM		 412 .ts_low_shift = TS_LOW_SHIFT,
413 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
414 .ts_high_shift = TS_HI_SHIFT,
415 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
416 .ts_shift = dma_ts_shift,
417 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
643c3307
KM		 418 .dmaor_init = DMAOR_DME,
419 .chclr_present = 1,
420};
421
422/* Resource order important! */
423static struct resource r8a7740_dmae0_resources[] = {
424 {
425 /* Channel registers and DMAOR */
426 .start = 0xfe008020,
427 .end = 0xfe00828f,
428 .flags = IORESOURCE_MEM,
429 },
430 {
431 /* DMARSx */
432 .start = 0xfe009000,
433 .end = 0xfe00900b,
434 .flags = IORESOURCE_MEM,
435 },
436 {
437 .name = "error_irq",
0b7d7820
BH		 438 .start = gic_spi(34),
439 .end = gic_spi(34),
643c3307
KM		 440 .flags = IORESOURCE_IRQ,
441 },
442 {
443 /* IRQ for channels 0-5 */
0b7d7820
BH		 444 .start = gic_spi(28),
445 .end = gic_spi(33),
643c3307
KM		 446 .flags = IORESOURCE_IRQ,
447 },
448};
449
450/* Resource order important! */
451static struct resource r8a7740_dmae1_resources[] = {
452 {
453 /* Channel registers and DMAOR */
454 .start = 0xfe018020,
455 .end = 0xfe01828f,
456 .flags = IORESOURCE_MEM,
457 },
458 {
459 /* DMARSx */
460 .start = 0xfe019000,
461 .end = 0xfe01900b,
462 .flags = IORESOURCE_MEM,
463 },
464 {
465 .name = "error_irq",
0b7d7820
BH		 466 .start = gic_spi(41),
467 .end = gic_spi(41),
643c3307
KM		 468 .flags = IORESOURCE_IRQ,
469 },
470 {
471 /* IRQ for channels 0-5 */
0b7d7820
BH		 472 .start = gic_spi(35),
473 .end = gic_spi(40),
643c3307
KM		 474 .flags = IORESOURCE_IRQ,
475 },
476};
477
478/* Resource order important! */
479static struct resource r8a7740_dmae2_resources[] = {
480 {
481 /* Channel registers and DMAOR */
482 .start = 0xfe028020,
483 .end = 0xfe02828f,
484 .flags = IORESOURCE_MEM,
485 },
486 {
487 /* DMARSx */
488 .start = 0xfe029000,
489 .end = 0xfe02900b,
490 .flags = IORESOURCE_MEM,
491 },
492 {
493 .name = "error_irq",
0b7d7820
BH		 494 .start = gic_spi(48),
495 .end = gic_spi(48),
643c3307
KM		 496 .flags = IORESOURCE_IRQ,
497 },
498 {
499 /* IRQ for channels 0-5 */
0b7d7820
BH		 500 .start = gic_spi(42),
501 .end = gic_spi(47),
643c3307
KM		 502 .flags = IORESOURCE_IRQ,
503 },
504};
505
506static struct platform_device dma0_device = {
507 .name = "sh-dma-engine",
508 .id = 0,
509 .resource = r8a7740_dmae0_resources,
510 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
511 .dev = {
512 .platform_data = &dma_platform_data,
513 },
514};
515
516static struct platform_device dma1_device = {
517 .name = "sh-dma-engine",
518 .id = 1,
519 .resource = r8a7740_dmae1_resources,
520 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
521 .dev = {
522 .platform_data = &dma_platform_data,
523 },
524};
525
526static struct platform_device dma2_device = {
527 .name = "sh-dma-engine",
528 .id = 2,
529 .resource = r8a7740_dmae2_resources,
530 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
531 .dev = {
532 .platform_data = &dma_platform_data,
533 },
534};
535
dbf382e5 536/* USB-DMAC */
dbf382e5
KM		 537static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
538 {
539 .offset = 0,
540 }, {
541 .offset = 0x20,
542 },
543};
544
dbf382e5
KM		 545static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
546 {
547 .slave_id = SHDMA_SLAVE_USBHS_TX,
548 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
549 }, {
550 .slave_id = SHDMA_SLAVE_USBHS_RX,
551 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
552 },
553};
554
555static struct sh_dmae_pdata usb_dma_platform_data = {
556 .slave = r8a7740_usb_dma_slaves,
557 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
558 .channel = r8a7740_usb_dma_channels,
559 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
d7de938f
KM		 560 .ts_low_shift = USBTS_LOW_SHIFT,
561 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
562 .ts_high_shift = USBTS_HI_SHIFT,
563 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
dbf382e5
KM		 564 .ts_shift = dma_usbts_shift,
565 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
566 .dmaor_init = DMAOR_DME,
567 .chcr_offset = 0x14,
568 .chcr_ie_bit = 1 << 5,
569 .dmaor_is_32bit = 1,
570 .needs_tend_set = 1,
571 .no_dmars = 1,
572 .slave_only = 1,
573};
574
575static struct resource r8a7740_usb_dma_resources[] = {
576 {
577 /* Channel registers and DMAOR */
578 .start = 0xe68a0020,
579 .end = 0xe68a0064 - 1,
580 .flags = IORESOURCE_MEM,
581 },
582 {
583 /* VCR/SWR/DMICR */
584 .start = 0xe68a0000,
585 .end = 0xe68a0014 - 1,
586 .flags = IORESOURCE_MEM,
587 },
588 {
589 /* IRQ for channels */
0b7d7820
BH		 590 .start = gic_spi(49),
591 .end = gic_spi(49),
dbf382e5
KM		 592 .flags = IORESOURCE_IRQ,
593 },
594};
595
596static struct platform_device usb_dma_device = {
597 .name = "sh-dma-engine",
598 .id = 3,
599 .resource = r8a7740_usb_dma_resources,
600 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
601 .dev = {
602 .platform_data = &usb_dma_platform_data,
603 },
604};
605
6831f3a9
KM		 606/* I2C */
607static struct resource i2c0_resources[] = {
608 [0] = {
609 .name = "IIC0",
610 .start = 0xfff20000,
611 .end = 0xfff20425 - 1,
612 .flags = IORESOURCE_MEM,
613 },
614 [1] = {
0b7d7820
BH		 615 .start = gic_spi(201),
616 .end = gic_spi(204),
6831f3a9
KM		 617 .flags = IORESOURCE_IRQ,
618 },
619};
620
621static struct resource i2c1_resources[] = {
622 [0] = {
623 .name = "IIC1",
624 .start = 0xe6c20000,
625 .end = 0xe6c20425 - 1,
626 .flags = IORESOURCE_MEM,
627 },
628 [1] = {
0b7d7820
BH		 629 .start = gic_spi(70), /* IIC1_ALI1 */
630 .end = gic_spi(73), /* IIC1_DTEI1 */
6831f3a9
KM		 631 .flags = IORESOURCE_IRQ,
632 },
633};
634
635static struct platform_device i2c0_device = {
636 .name = "i2c-sh_mobile",
637 .id = 0,
638 .resource = i2c0_resources,
639 .num_resources = ARRAY_SIZE(i2c0_resources),
640};
641
642static struct platform_device i2c1_device = {
643 .name = "i2c-sh_mobile",
644 .id = 1,
645 .resource = i2c1_resources,
646 .num_resources = ARRAY_SIZE(i2c1_resources),
647};
648
86bc52ef
NI		 649static struct resource pmu_resources[] = {
650 [0] = {
0b7d7820
BH		 651 .start = gic_spi(83),
652 .end = gic_spi(83),
86bc52ef
NI		 653 .flags = IORESOURCE_IRQ,
654 },
655};
656
657static struct platform_device pmu_device = {
744503b3 658 .name = "armv7-pmu",
86bc52ef
NI		 659 .id = -1,
660 .num_resources = ARRAY_SIZE(pmu_resources),
661 .resource = pmu_resources,
662};
663
6831f3a9
KM		 664static struct platform_device *r8a7740_late_devices[] __initdata = {
665 &i2c0_device,
666 &i2c1_device,
643c3307
KM		 667 &dma0_device,
668 &dma1_device,
669 &dma2_device,
dbf382e5 670 &usb_dma_device,
86bc52ef 671 &pmu_device,
6831f3a9
KM		 672};
673
d49679e5
KM		 674/*
675 * r8a7740 chip has lasting errata on MERAM buffer.
676 * this is work-around for it.
677 * see
678 * "Media RAM (MERAM)" on r8a7740 documentation
679 */
680#define MEBUFCNTR 0xFE950098
bb6c3d58 681void __init r8a7740_meram_workaround(void)
d49679e5
KM		 682{
683 void __iomem *reg;
684
685 reg = ioremap_nocache(MEBUFCNTR, 4);
686 if (reg) {
687 iowrite32(0x01600164, reg);
688 iounmap(reg);
689 }
690}
691
6c01ba44
KM		 692void __init r8a7740_add_standard_devices(void)
693{
c839f93b 694 static struct pm_domain_device domain_devices[] __initdata = {
1618a677
GU		 695 { "A4R", &tmu0_device },
696 { "A4R", &i2c0_device },
3b358cb8
GU		 697 { "A4S", &irqpin0_device },
698 { "A4S", &irqpin1_device },
699 { "A4S", &irqpin2_device },
700 { "A4S", &irqpin3_device },
c839f93b
GU		 701 { "A3SP", &scif0_device },
702 { "A3SP", &scif1_device },
703 { "A3SP", &scif2_device },
704 { "A3SP", &scif3_device },
705 { "A3SP", &scif4_device },
706 { "A3SP", &scif5_device },
707 { "A3SP", &scif6_device },
708 { "A3SP", &scif7_device },
709 { "A3SP", &scif8_device },
710 { "A3SP", &i2c1_device },
80f643b3
GU		 711 { "A3SP", &ipmmu_device },
712 { "A3SP", &dma0_device },
713 { "A3SP", &dma1_device },
714 { "A3SP", &dma2_device },
715 { "A3SP", &usb_dma_device },
c839f93b
GU		 716 };
717
7b567407 718 r8a7740_init_pm_domains();
8459293c
KM		 719
720 /* add devices */
6c01ba44
KM		 721 platform_add_devices(r8a7740_early_devices,
722 ARRAY_SIZE(r8a7740_early_devices));
6831f3a9
KM		 723 platform_add_devices(r8a7740_late_devices,
724 ARRAY_SIZE(r8a7740_late_devices));
802a5639
KM		 725
726 /* add devices to PM domain */
c839f93b
GU		 727 rmobile_add_devices_to_domains(domain_devices,
728 ARRAY_SIZE(domain_devices));
6c01ba44
KM		 729}
730
731void __init r8a7740_add_early_devices(void)
732{
733 early_platform_add_devices(r8a7740_early_devices,
734 ARRAY_SIZE(r8a7740_early_devices));
d3ab7221
MD		 735
736 /* setup early console here as well */
737 shmobile_setup_console();
6c01ba44 738}
755d57b2
MD		 739
740#ifdef CONFIG_USE_OF
741
70e3f3d4
KM		 742void __init r8a7740_init_irq_of(void)
743{
744 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
745 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
746 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
747
d034f53c
GU		 748#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
749 void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
750 void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
751
752 gic_init(0, 29, gic_dist_base, gic_cpu_base);
753#else
70e3f3d4 754 irqchip_init();
d034f53c 755#endif
70e3f3d4
KM		 756
757 /* route signals to GIC */
758 iowrite32(0x0, pfc_inta_ctrl);
759
760 /*
761 * To mask the shared interrupt to SPI 149 we must ensure to set
762 * PRIO *and* MASK. Else we run into IRQ floods when registering
763 * the intc_irqpin devices
764 */
765 iowrite32(0x0, intc_prio_base + 0x0);
766 iowrite32(0x0, intc_prio_base + 0x4);
767 iowrite32(0x0, intc_prio_base + 0x8);
768 iowrite32(0x0, intc_prio_base + 0xc);
769 iowrite8(0xff, intc_msk_base + 0x0);
770 iowrite8(0xff, intc_msk_base + 0x4);
771 iowrite8(0xff, intc_msk_base + 0x8);
772 iowrite8(0xff, intc_msk_base + 0xc);
773
774 iounmap(intc_prio_base);
775 iounmap(intc_msk_base);
776 iounmap(pfc_inta_ctrl);
777}
778
744fdc8d
BH		 779static void __init r8a7740_generic_init(void)
780{
c41215b7
MD		 781 r8a7740_meram_workaround();
782
783#ifdef CONFIG_CACHE_L2X0
784 /* Shared attribute override enable, 32K*8way */
785 l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
786#endif
43330674 787 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
744fdc8d
BH		 788}
789
755d57b2
MD		 790static const char *r8a7740_boards_compat_dt[] __initdata = {
791 "renesas,r8a7740",
792 NULL,
793};
794
a41acc4a 795DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
755d57b2 796 .map_io = r8a7740_map_io,
a0c1fb0c 797 .init_early = shmobile_init_delay,
744fdc8d
BH		 798 .init_irq = r8a7740_init_irq_of,
799 .init_machine = r8a7740_generic_init,
34b9fa40 800 .init_late = shmobile_init_late,
755d57b2
MD		 801 .dt_compat = r8a7740_boards_compat_dt,
802MACHINE_END
803
804#endif /* CONFIG_USE_OF */
Linux kernel - Deliverables
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