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Merge tag 'ecryptfs-3.11-rc1-cleanup' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7740.c
CommitLineData
6c01ba44
KM		 1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
6831f3a9 20#include <linux/delay.h>
3841e6f5 21#include <linux/dma-mapping.h>
6c01ba44
KM		 22#include <linux/kernel.h>
23#include <linux/init.h>
6831f3a9 24#include <linux/io.h>
0b7d7820 25#include <linux/platform_data/irq-renesas-intc-irqpin.h>
6c01ba44 26#include <linux/platform_device.h>
755d57b2 27#include <linux/of_platform.h>
6c01ba44 28#include <linux/serial_sci.h>
643c3307 29#include <linux/sh_dma.h>
6c01ba44 30#include <linux/sh_timer.h>
f671e022 31#include <linux/platform_data/sh_ipmmu.h>
d7de938f 32#include <mach/dma-register.h>
6c01ba44 33#include <mach/r8a7740.h>
8459293c 34#include <mach/pm-rmobile.h>
d3ab7221 35#include <mach/common.h>
250a2723 36#include <mach/irqs.h>
6c01ba44 37#include <asm/mach-types.h>
d3ab7221 38#include <asm/mach/map.h>
6c01ba44 39#include <asm/mach/arch.h>
23e5bc03 40#include <asm/mach/time.h>
6c01ba44 41
d3ab7221
MD		 42static struct map_desc r8a7740_io_desc[] __initdata = {
43 /*
44 * for CPGA/INTC/PFC
45 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
46 */
47 {
48 .virtual = 0xe6000000,
49 .pfn = __phys_to_pfn(0xe6000000),
50 .length = 160 << 20,
51 .type = MT_DEVICE_NONSHARED
52 },
53#ifdef CONFIG_CACHE_L2X0
54 /*
55 * for l2x0_init()
56 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
57 */
58 {
59 .virtual = 0xf0002000,
60 .pfn = __phys_to_pfn(0xf0100000),
61 .length = PAGE_SIZE,
62 .type = MT_DEVICE_NONSHARED
63 },
64#endif
65};
66
67void __init r8a7740_map_io(void)
68{
69 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
70}
71
02b01adb 72/* PFC */
3404622a
MD		 73static const struct resource pfc_resources[] = {
74 DEFINE_RES_MEM(0xe6050000, 0x8000),
75 DEFINE_RES_MEM(0xe605800c, 0x0020),
02b01adb
LP		 76};
77
78void __init r8a7740_pinmux_init(void)
79{
3404622a
MD		 80 platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
81 ARRAY_SIZE(pfc_resources));
02b01adb
LP		 82}
83
0b7d7820
BH		 84static struct renesas_intc_irqpin_config irqpin0_platform_data = {
85 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
86};
87
88static struct resource irqpin0_resources[] = {
89 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
90 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
91 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
92 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
93 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
94 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
95 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
96 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
97 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
98 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
99 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
100 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
101 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
102};
103
104static struct platform_device irqpin0_device = {
105 .name = "renesas_intc_irqpin",
106 .id = 0,
107 .resource = irqpin0_resources,
108 .num_resources = ARRAY_SIZE(irqpin0_resources),
109 .dev = {
110 .platform_data = &irqpin0_platform_data,
111 },
112};
113
114static struct renesas_intc_irqpin_config irqpin1_platform_data = {
115 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
116};
117
118static struct resource irqpin1_resources[] = {
119 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
120 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
121 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
122 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
123 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
124 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
125 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
126 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
127 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
128 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
129 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
130 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
131 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
132};
133
134static struct platform_device irqpin1_device = {
135 .name = "renesas_intc_irqpin",
136 .id = 1,
137 .resource = irqpin1_resources,
138 .num_resources = ARRAY_SIZE(irqpin1_resources),
139 .dev = {
140 .platform_data = &irqpin1_platform_data,
141 },
142};
143
144static struct renesas_intc_irqpin_config irqpin2_platform_data = {
145 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
146};
147
148static struct resource irqpin2_resources[] = {
149 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
150 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
151 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
152 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
153 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
154 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
155 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
156 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
157 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
158 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
159 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
160 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
161 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
162};
163
164static struct platform_device irqpin2_device = {
165 .name = "renesas_intc_irqpin",
166 .id = 2,
167 .resource = irqpin2_resources,
168 .num_resources = ARRAY_SIZE(irqpin2_resources),
169 .dev = {
170 .platform_data = &irqpin2_platform_data,
171 },
172};
173
174static struct renesas_intc_irqpin_config irqpin3_platform_data = {
175 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
176};
177
178static struct resource irqpin3_resources[] = {
179 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
180 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
181 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
182 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
183 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
184 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
185 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
186 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
187 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
188 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
189 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
190 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
191 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
192};
193
194static struct platform_device irqpin3_device = {
195 .name = "renesas_intc_irqpin",
196 .id = 3,
197 .resource = irqpin3_resources,
198 .num_resources = ARRAY_SIZE(irqpin3_resources),
199 .dev = {
200 .platform_data = &irqpin3_platform_data,
201 },
202};
203
6c01ba44
KM		 204/* SCIFA0 */
205static struct plat_sci_port scif0_platform_data = {
206 .mapbase = 0xe6c40000,
207 .flags = UPF_BOOT_AUTOCONF,
208 .scscr = SCSCR_RE | SCSCR_TE,
209 .scbrr_algo_id = SCBRR_ALGO_4,
210 .type = PORT_SCIFA,
0b7d7820 211 .irqs = SCIx_IRQ_MUXED(gic_spi(100)),
6c01ba44
KM		 212};
213
214static struct platform_device scif0_device = {
215 .name = "sh-sci",
216 .id = 0,
217 .dev = {
218 .platform_data = &scif0_platform_data,
219 },
220};
221
222/* SCIFA1 */
223static struct plat_sci_port scif1_platform_data = {
224 .mapbase = 0xe6c50000,
225 .flags = UPF_BOOT_AUTOCONF,
226 .scscr = SCSCR_RE | SCSCR_TE,
227 .scbrr_algo_id = SCBRR_ALGO_4,
228 .type = PORT_SCIFA,
0b7d7820 229 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
6c01ba44
KM		 230};
231
232static struct platform_device scif1_device = {
233 .name = "sh-sci",
234 .id = 1,
235 .dev = {
236 .platform_data = &scif1_platform_data,
237 },
238};
239
240/* SCIFA2 */
241static struct plat_sci_port scif2_platform_data = {
242 .mapbase = 0xe6c60000,
243 .flags = UPF_BOOT_AUTOCONF,
244 .scscr = SCSCR_RE | SCSCR_TE,
245 .scbrr_algo_id = SCBRR_ALGO_4,
246 .type = PORT_SCIFA,
0b7d7820 247 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
6c01ba44
KM		 248};
249
250static struct platform_device scif2_device = {
251 .name = "sh-sci",
252 .id = 2,
253 .dev = {
254 .platform_data = &scif2_platform_data,
255 },
256};
257
258/* SCIFA3 */
259static struct plat_sci_port scif3_platform_data = {
260 .mapbase = 0xe6c70000,
261 .flags = UPF_BOOT_AUTOCONF,
262 .scscr = SCSCR_RE | SCSCR_TE,
263 .scbrr_algo_id = SCBRR_ALGO_4,
264 .type = PORT_SCIFA,
0b7d7820 265 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
6c01ba44
KM		 266};
267
268static struct platform_device scif3_device = {
269 .name = "sh-sci",
270 .id = 3,
271 .dev = {
272 .platform_data = &scif3_platform_data,
273 },
274};
275
276/* SCIFA4 */
277static struct plat_sci_port scif4_platform_data = {
278 .mapbase = 0xe6c80000,
279 .flags = UPF_BOOT_AUTOCONF,
280 .scscr = SCSCR_RE | SCSCR_TE,
281 .scbrr_algo_id = SCBRR_ALGO_4,
282 .type = PORT_SCIFA,
0b7d7820 283 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
6c01ba44
KM		 284};
285
286static struct platform_device scif4_device = {
287 .name = "sh-sci",
288 .id = 4,
289 .dev = {
290 .platform_data = &scif4_platform_data,
291 },
292};
293
294/* SCIFA5 */
295static struct plat_sci_port scif5_platform_data = {
296 .mapbase = 0xe6cb0000,
297 .flags = UPF_BOOT_AUTOCONF,
298 .scscr = SCSCR_RE | SCSCR_TE,
299 .scbrr_algo_id = SCBRR_ALGO_4,
300 .type = PORT_SCIFA,
0b7d7820 301 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
6c01ba44
KM		 302};
303
304static struct platform_device scif5_device = {
305 .name = "sh-sci",
306 .id = 5,
307 .dev = {
308 .platform_data = &scif5_platform_data,
309 },
310};
311
312/* SCIFA6 */
313static struct plat_sci_port scif6_platform_data = {
314 .mapbase = 0xe6cc0000,
315 .flags = UPF_BOOT_AUTOCONF,
316 .scscr = SCSCR_RE | SCSCR_TE,
317 .scbrr_algo_id = SCBRR_ALGO_4,
318 .type = PORT_SCIFA,
0b7d7820 319 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
6c01ba44
KM		 320};
321
322static struct platform_device scif6_device = {
323 .name = "sh-sci",
324 .id = 6,
325 .dev = {
326 .platform_data = &scif6_platform_data,
327 },
328};
329
330/* SCIFA7 */
331static struct plat_sci_port scif7_platform_data = {
332 .mapbase = 0xe6cd0000,
333 .flags = UPF_BOOT_AUTOCONF,
334 .scscr = SCSCR_RE | SCSCR_TE,
335 .scbrr_algo_id = SCBRR_ALGO_4,
336 .type = PORT_SCIFA,
0b7d7820 337 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
6c01ba44
KM		 338};
339
340static struct platform_device scif7_device = {
341 .name = "sh-sci",
342 .id = 7,
343 .dev = {
344 .platform_data = &scif7_platform_data,
345 },
346};
347
348/* SCIFB */
349static struct plat_sci_port scifb_platform_data = {
350 .mapbase = 0xe6c30000,
351 .flags = UPF_BOOT_AUTOCONF,
352 .scscr = SCSCR_RE | SCSCR_TE,
353 .scbrr_algo_id = SCBRR_ALGO_4,
354 .type = PORT_SCIFB,
0b7d7820 355 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
6c01ba44
KM		 356};
357
358static struct platform_device scifb_device = {
359 .name = "sh-sci",
360 .id = 8,
361 .dev = {
362 .platform_data = &scifb_platform_data,
363 },
364};
365
366/* CMT */
367static struct sh_timer_config cmt10_platform_data = {
368 .name = "CMT10",
369 .channel_offset = 0x10,
370 .timer_bit = 0,
371 .clockevent_rating = 125,
372 .clocksource_rating = 125,
373};
374
375static struct resource cmt10_resources[] = {
376 [0] = {
377 .name = "CMT10",
378 .start = 0xe6138010,
379 .end = 0xe613801b,
380 .flags = IORESOURCE_MEM,
381 },
382 [1] = {
0b7d7820 383 .start = gic_spi(58),
6c01ba44
KM		 384 .flags = IORESOURCE_IRQ,
385 },
386};
387
388static struct platform_device cmt10_device = {
389 .name = "sh_cmt",
390 .id = 10,
391 .dev = {
392 .platform_data = &cmt10_platform_data,
393 },
394 .resource = cmt10_resources,
395 .num_resources = ARRAY_SIZE(cmt10_resources),
396};
397
e67d7afc
KM		 398/* TMU */
399static struct sh_timer_config tmu00_platform_data = {
400 .name = "TMU00",
401 .channel_offset = 0x4,
402 .timer_bit = 0,
403 .clockevent_rating = 200,
404};
405
406static struct resource tmu00_resources[] = {
407 [0] = {
408 .name = "TMU00",
409 .start = 0xfff80008,
410 .end = 0xfff80014 - 1,
411 .flags = IORESOURCE_MEM,
412 },
413 [1] = {
0b7d7820 414 .start = gic_spi(198),
e67d7afc
KM		 415 .flags = IORESOURCE_IRQ,
416 },
417};
418
419static struct platform_device tmu00_device = {
420 .name = "sh_tmu",
421 .id = 0,
422 .dev = {
423 .platform_data = &tmu00_platform_data,
424 },
425 .resource = tmu00_resources,
426 .num_resources = ARRAY_SIZE(tmu00_resources),
427};
428
429static struct sh_timer_config tmu01_platform_data = {
430 .name = "TMU01",
431 .channel_offset = 0x10,
432 .timer_bit = 1,
433 .clocksource_rating = 200,
434};
435
436static struct resource tmu01_resources[] = {
437 [0] = {
438 .name = "TMU01",
439 .start = 0xfff80014,
440 .end = 0xfff80020 - 1,
441 .flags = IORESOURCE_MEM,
442 },
443 [1] = {
0b7d7820 444 .start = gic_spi(199),
e67d7afc
KM		 445 .flags = IORESOURCE_IRQ,
446 },
447};
448
449static struct platform_device tmu01_device = {
450 .name = "sh_tmu",
451 .id = 1,
452 .dev = {
453 .platform_data = &tmu01_platform_data,
454 },
455 .resource = tmu01_resources,
456 .num_resources = ARRAY_SIZE(tmu01_resources),
457};
458
459static struct sh_timer_config tmu02_platform_data = {
460 .name = "TMU02",
461 .channel_offset = 0x1C,
462 .timer_bit = 2,
463 .clocksource_rating = 200,
464};
465
466static struct resource tmu02_resources[] = {
467 [0] = {
468 .name = "TMU02",
469 .start = 0xfff80020,
470 .end = 0xfff8002C - 1,
471 .flags = IORESOURCE_MEM,
472 },
473 [1] = {
0b7d7820 474 .start = gic_spi(200),
e67d7afc
KM		 475 .flags = IORESOURCE_IRQ,
476 },
477};
478
479static struct platform_device tmu02_device = {
480 .name = "sh_tmu",
481 .id = 2,
482 .dev = {
483 .platform_data = &tmu02_platform_data,
484 },
485 .resource = tmu02_resources,
486 .num_resources = ARRAY_SIZE(tmu02_resources),
487};
488
f671e022
HE		 489/* IPMMUI (an IPMMU module for ICB/LMB) */
490static struct resource ipmmu_resources[] = {
491 [0] = {
492 .name = "IPMMUI",
493 .start = 0xfe951000,
494 .end = 0xfe9510ff,
495 .flags = IORESOURCE_MEM,
496 },
497};
498
499static const char * const ipmmu_dev_names[] = {
500 "sh_mobile_lcdc_fb.0",
501 "sh_mobile_lcdc_fb.1",
502 "sh_mobile_ceu.0",
503};
504
505static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
506 .dev_names = ipmmu_dev_names,
507 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
508};
509
510static struct platform_device ipmmu_device = {
511 .name = "ipmmu",
512 .id = -1,
513 .dev = {
514 .platform_data = &ipmmu_platform_data,
515 },
516 .resource = ipmmu_resources,
517 .num_resources = ARRAY_SIZE(ipmmu_resources),
518};
519
744fdc8d 520static struct platform_device *r8a7740_devices_dt[] __initdata = {
6c01ba44
KM		 521 &scif0_device,
522 &scif1_device,
523 &scif2_device,
524 &scif3_device,
525 &scif4_device,
526 &scif5_device,
527 &scif6_device,
528 &scif7_device,
529 &scifb_device,
530 &cmt10_device,
744fdc8d
BH		 531};
532
533static struct platform_device *r8a7740_early_devices[] __initdata = {
534 &irqpin0_device,
535 &irqpin1_device,
536 &irqpin2_device,
537 &irqpin3_device,
e67d7afc
KM		 538 &tmu00_device,
539 &tmu01_device,
540 &tmu02_device,
f671e022 541 &ipmmu_device,
6c01ba44
KM		 542};
543
643c3307 544/* DMA */
643c3307
KM		 545static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
546 {
cb76eb81
KM		 547 .slave_id = SHDMA_SLAVE_SDHI0_TX,
548 .addr = 0xe6850030,
549 .chcr = CHCR_TX(XMIT_SZ_16BIT),
550 .mid_rid = 0xc1,
551 }, {
552 .slave_id = SHDMA_SLAVE_SDHI0_RX,
553 .addr = 0xe6850030,
554 .chcr = CHCR_RX(XMIT_SZ_16BIT),
555 .mid_rid = 0xc2,
556 }, {
557 .slave_id = SHDMA_SLAVE_SDHI1_TX,
558 .addr = 0xe6860030,
559 .chcr = CHCR_TX(XMIT_SZ_16BIT),
560 .mid_rid = 0xc9,
561 }, {
562 .slave_id = SHDMA_SLAVE_SDHI1_RX,
563 .addr = 0xe6860030,
564 .chcr = CHCR_RX(XMIT_SZ_16BIT),
565 .mid_rid = 0xca,
566 }, {
567 .slave_id = SHDMA_SLAVE_SDHI2_TX,
568 .addr = 0xe6870030,
569 .chcr = CHCR_TX(XMIT_SZ_16BIT),
570 .mid_rid = 0xcd,
571 }, {
572 .slave_id = SHDMA_SLAVE_SDHI2_RX,
573 .addr = 0xe6870030,
574 .chcr = CHCR_RX(XMIT_SZ_16BIT),
575 .mid_rid = 0xce,
576 }, {
643c3307
KM		 577 .slave_id = SHDMA_SLAVE_FSIA_TX,
578 .addr = 0xfe1f0024,
579 .chcr = CHCR_TX(XMIT_SZ_32BIT),
580 .mid_rid = 0xb1,
581 }, {
582 .slave_id = SHDMA_SLAVE_FSIA_RX,
583 .addr = 0xfe1f0020,
584 .chcr = CHCR_RX(XMIT_SZ_32BIT),
585 .mid_rid = 0xb2,
586 }, {
587 .slave_id = SHDMA_SLAVE_FSIB_TX,
588 .addr = 0xfe1f0064,
589 .chcr = CHCR_TX(XMIT_SZ_32BIT),
590 .mid_rid = 0xb5,
591 },
592};
593
594#define DMA_CHANNEL(a, b, c) \
595{ \
596 .offset = a, \
597 .dmars = b, \
598 .dmars_bit = c, \
599 .chclr_offset = (0x220 - 0x20) + a \
600}
601
602static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
603 DMA_CHANNEL(0x00, 0, 0),
604 DMA_CHANNEL(0x10, 0, 8),
605 DMA_CHANNEL(0x20, 4, 0),
606 DMA_CHANNEL(0x30, 4, 8),
607 DMA_CHANNEL(0x50, 8, 0),
608 DMA_CHANNEL(0x60, 8, 8),
609};
610
643c3307
KM		 611static struct sh_dmae_pdata dma_platform_data = {
612 .slave = r8a7740_dmae_slaves,
613 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
614 .channel = r8a7740_dmae_channels,
615 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
d7de938f
KM		 616 .ts_low_shift = TS_LOW_SHIFT,
617 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
618 .ts_high_shift = TS_HI_SHIFT,
619 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
620 .ts_shift = dma_ts_shift,
621 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
643c3307
KM		 622 .dmaor_init = DMAOR_DME,
623 .chclr_present = 1,
624};
625
626/* Resource order important! */
627static struct resource r8a7740_dmae0_resources[] = {
628 {
629 /* Channel registers and DMAOR */
630 .start = 0xfe008020,
631 .end = 0xfe00828f,
632 .flags = IORESOURCE_MEM,
633 },
634 {
635 /* DMARSx */
636 .start = 0xfe009000,
637 .end = 0xfe00900b,
638 .flags = IORESOURCE_MEM,
639 },
640 {
641 .name = "error_irq",
0b7d7820
BH		 642 .start = gic_spi(34),
643 .end = gic_spi(34),
643c3307
KM		 644 .flags = IORESOURCE_IRQ,
645 },
646 {
647 /* IRQ for channels 0-5 */
0b7d7820
BH		 648 .start = gic_spi(28),
649 .end = gic_spi(33),
643c3307
KM		 650 .flags = IORESOURCE_IRQ,
651 },
652};
653
654/* Resource order important! */
655static struct resource r8a7740_dmae1_resources[] = {
656 {
657 /* Channel registers and DMAOR */
658 .start = 0xfe018020,
659 .end = 0xfe01828f,
660 .flags = IORESOURCE_MEM,
661 },
662 {
663 /* DMARSx */
664 .start = 0xfe019000,
665 .end = 0xfe01900b,
666 .flags = IORESOURCE_MEM,
667 },
668 {
669 .name = "error_irq",
0b7d7820
BH		 670 .start = gic_spi(41),
671 .end = gic_spi(41),
643c3307
KM		 672 .flags = IORESOURCE_IRQ,
673 },
674 {
675 /* IRQ for channels 0-5 */
0b7d7820
BH		 676 .start = gic_spi(35),
677 .end = gic_spi(40),
643c3307
KM		 678 .flags = IORESOURCE_IRQ,
679 },
680};
681
682/* Resource order important! */
683static struct resource r8a7740_dmae2_resources[] = {
684 {
685 /* Channel registers and DMAOR */
686 .start = 0xfe028020,
687 .end = 0xfe02828f,
688 .flags = IORESOURCE_MEM,
689 },
690 {
691 /* DMARSx */
692 .start = 0xfe029000,
693 .end = 0xfe02900b,
694 .flags = IORESOURCE_MEM,
695 },
696 {
697 .name = "error_irq",
0b7d7820
BH		 698 .start = gic_spi(48),
699 .end = gic_spi(48),
643c3307
KM		 700 .flags = IORESOURCE_IRQ,
701 },
702 {
703 /* IRQ for channels 0-5 */
0b7d7820
BH		 704 .start = gic_spi(42),
705 .end = gic_spi(47),
643c3307
KM		 706 .flags = IORESOURCE_IRQ,
707 },
708};
709
710static struct platform_device dma0_device = {
711 .name = "sh-dma-engine",
712 .id = 0,
713 .resource = r8a7740_dmae0_resources,
714 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
715 .dev = {
716 .platform_data = &dma_platform_data,
717 },
718};
719
720static struct platform_device dma1_device = {
721 .name = "sh-dma-engine",
722 .id = 1,
723 .resource = r8a7740_dmae1_resources,
724 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
725 .dev = {
726 .platform_data = &dma_platform_data,
727 },
728};
729
730static struct platform_device dma2_device = {
731 .name = "sh-dma-engine",
732 .id = 2,
733 .resource = r8a7740_dmae2_resources,
734 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
735 .dev = {
736 .platform_data = &dma_platform_data,
737 },
738};
739
dbf382e5 740/* USB-DMAC */
dbf382e5
KM		 741static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
742 {
743 .offset = 0,
744 }, {
745 .offset = 0x20,
746 },
747};
748
dbf382e5
KM		 749static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
750 {
751 .slave_id = SHDMA_SLAVE_USBHS_TX,
752 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
753 }, {
754 .slave_id = SHDMA_SLAVE_USBHS_RX,
755 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
756 },
757};
758
759static struct sh_dmae_pdata usb_dma_platform_data = {
760 .slave = r8a7740_usb_dma_slaves,
761 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
762 .channel = r8a7740_usb_dma_channels,
763 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
d7de938f
KM		 764 .ts_low_shift = USBTS_LOW_SHIFT,
765 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
766 .ts_high_shift = USBTS_HI_SHIFT,
767 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
dbf382e5
KM		 768 .ts_shift = dma_usbts_shift,
769 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
770 .dmaor_init = DMAOR_DME,
771 .chcr_offset = 0x14,
772 .chcr_ie_bit = 1 << 5,
773 .dmaor_is_32bit = 1,
774 .needs_tend_set = 1,
775 .no_dmars = 1,
776 .slave_only = 1,
777};
778
779static struct resource r8a7740_usb_dma_resources[] = {
780 {
781 /* Channel registers and DMAOR */
782 .start = 0xe68a0020,
783 .end = 0xe68a0064 - 1,
784 .flags = IORESOURCE_MEM,
785 },
786 {
787 /* VCR/SWR/DMICR */
788 .start = 0xe68a0000,
789 .end = 0xe68a0014 - 1,
790 .flags = IORESOURCE_MEM,
791 },
792 {
793 /* IRQ for channels */
0b7d7820
BH		 794 .start = gic_spi(49),
795 .end = gic_spi(49),
dbf382e5
KM		 796 .flags = IORESOURCE_IRQ,
797 },
798};
799
800static struct platform_device usb_dma_device = {
801 .name = "sh-dma-engine",
802 .id = 3,
803 .resource = r8a7740_usb_dma_resources,
804 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
805 .dev = {
806 .platform_data = &usb_dma_platform_data,
807 },
808};
809
6831f3a9
KM		 810/* I2C */
811static struct resource i2c0_resources[] = {
812 [0] = {
813 .name = "IIC0",
814 .start = 0xfff20000,
815 .end = 0xfff20425 - 1,
816 .flags = IORESOURCE_MEM,
817 },
818 [1] = {
0b7d7820
BH		 819 .start = gic_spi(201),
820 .end = gic_spi(204),
6831f3a9
KM		 821 .flags = IORESOURCE_IRQ,
822 },
823};
824
825static struct resource i2c1_resources[] = {
826 [0] = {
827 .name = "IIC1",
828 .start = 0xe6c20000,
829 .end = 0xe6c20425 - 1,
830 .flags = IORESOURCE_MEM,
831 },
832 [1] = {
0b7d7820
BH		 833 .start = gic_spi(70), /* IIC1_ALI1 */
834 .end = gic_spi(73), /* IIC1_DTEI1 */
6831f3a9
KM		 835 .flags = IORESOURCE_IRQ,
836 },
837};
838
839static struct platform_device i2c0_device = {
840 .name = "i2c-sh_mobile",
841 .id = 0,
842 .resource = i2c0_resources,
843 .num_resources = ARRAY_SIZE(i2c0_resources),
844};
845
846static struct platform_device i2c1_device = {
847 .name = "i2c-sh_mobile",
848 .id = 1,
849 .resource = i2c1_resources,
850 .num_resources = ARRAY_SIZE(i2c1_resources),
851};
852
86bc52ef
NI		 853static struct resource pmu_resources[] = {
854 [0] = {
0b7d7820
BH		 855 .start = gic_spi(83),
856 .end = gic_spi(83),
86bc52ef
NI		 857 .flags = IORESOURCE_IRQ,
858 },
859};
860
861static struct platform_device pmu_device = {
862 .name = "arm-pmu",
863 .id = -1,
864 .num_resources = ARRAY_SIZE(pmu_resources),
865 .resource = pmu_resources,
866};
867
6831f3a9
KM		 868static struct platform_device *r8a7740_late_devices[] __initdata = {
869 &i2c0_device,
870 &i2c1_device,
643c3307
KM		 871 &dma0_device,
872 &dma1_device,
873 &dma2_device,
dbf382e5 874 &usb_dma_device,
86bc52ef 875 &pmu_device,
6831f3a9
KM		 876};
877
d49679e5
KM		 878/*
879 * r8a7740 chip has lasting errata on MERAM buffer.
880 * this is work-around for it.
881 * see
882 * "Media RAM (MERAM)" on r8a7740 documentation
883 */
884#define MEBUFCNTR 0xFE950098
885void r8a7740_meram_workaround(void)
886{
887 void __iomem *reg;
888
889 reg = ioremap_nocache(MEBUFCNTR, 4);
890 if (reg) {
891 iowrite32(0x01600164, reg);
892 iounmap(reg);
893 }
894}
895
6831f3a9
KM		 896#define ICCR 0x0004
897#define ICSTART 0x0070
898
899#define i2c_read(reg, offset) ioread8(reg + offset)
900#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
901
902/*
903 * r8a7740 chip has lasting errata on I2C I/O pad reset.
904 * this is work-around for it.
905 */
906static void r8a7740_i2c_workaround(struct platform_device *pdev)
907{
908 struct resource *res;
909 void __iomem *reg;
910
911 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
912 if (unlikely(!res)) {
913 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
914 return;
915 }
916
917 reg = ioremap(res->start, resource_size(res));
918 if (unlikely(!reg)) {
919 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
920 return;
921 }
922
923 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
924 i2c_read(reg, ICCR); /* dummy read */
925
926 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
927 i2c_read(reg, ICSTART); /* dummy read */
928
4228716c 929 udelay(10);
6831f3a9
KM		 930
931 i2c_write(reg, ICCR, 0x01);
6831f3a9 932 i2c_write(reg, ICSTART, 0x00);
4228716c
KM		 933
934 udelay(10);
6831f3a9
KM		 935
936 i2c_write(reg, ICCR, 0x10);
4228716c 937 udelay(10);
6831f3a9 938 i2c_write(reg, ICCR, 0x00);
4228716c 939 udelay(10);
6831f3a9 940 i2c_write(reg, ICCR, 0x10);
4228716c 941 udelay(10);
6831f3a9
KM		 942
943 iounmap(reg);
944}
945
6c01ba44
KM		 946void __init r8a7740_add_standard_devices(void)
947{
6831f3a9
KM		 948 /* I2C work-around */
949 r8a7740_i2c_workaround(&i2c0_device);
950 r8a7740_i2c_workaround(&i2c1_device);
951
7b567407 952 r8a7740_init_pm_domains();
8459293c
KM		 953
954 /* add devices */
6c01ba44
KM		 955 platform_add_devices(r8a7740_early_devices,
956 ARRAY_SIZE(r8a7740_early_devices));
744fdc8d
BH		 957 platform_add_devices(r8a7740_devices_dt,
958 ARRAY_SIZE(r8a7740_devices_dt));
6831f3a9
KM		 959 platform_add_devices(r8a7740_late_devices,
960 ARRAY_SIZE(r8a7740_late_devices));
802a5639
KM		 961
962 /* add devices to PM domain */
963
8bdd9468
RW		 964 rmobile_add_device_to_domain("A3SP", &scif0_device);
965 rmobile_add_device_to_domain("A3SP", &scif1_device);
966 rmobile_add_device_to_domain("A3SP", &scif2_device);
967 rmobile_add_device_to_domain("A3SP", &scif3_device);
968 rmobile_add_device_to_domain("A3SP", &scif4_device);
969 rmobile_add_device_to_domain("A3SP", &scif5_device);
970 rmobile_add_device_to_domain("A3SP", &scif6_device);
971 rmobile_add_device_to_domain("A3SP", &scif7_device);
972 rmobile_add_device_to_domain("A3SP", &scifb_device);
973 rmobile_add_device_to_domain("A3SP", &i2c1_device);
6c01ba44
KM		 974}
975
976void __init r8a7740_add_early_devices(void)
977{
978 early_platform_add_devices(r8a7740_early_devices,
979 ARRAY_SIZE(r8a7740_early_devices));
744fdc8d
BH		 980 early_platform_add_devices(r8a7740_devices_dt,
981 ARRAY_SIZE(r8a7740_devices_dt));
d3ab7221
MD		 982
983 /* setup early console here as well */
984 shmobile_setup_console();
6c01ba44 985}
755d57b2
MD		 986
987#ifdef CONFIG_USE_OF
988
755d57b2
MD		 989static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
990 { }
991};
992
993void __init r8a7740_add_standard_devices_dt(void)
994{
744fdc8d
BH		 995 platform_add_devices(r8a7740_devices_dt,
996 ARRAY_SIZE(r8a7740_devices_dt));
755d57b2
MD		 997 of_platform_populate(NULL, of_default_bus_match_table,
998 r8a7740_auxdata_lookup, NULL);
999}
1000
744fdc8d
BH		 1001void __init r8a7740_init_delay(void)
1002{
1003 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
1004};
1005
1006static void __init r8a7740_generic_init(void)
1007{
1008 r8a7740_clock_init(0);
1009 r8a7740_add_standard_devices_dt();
1010}
1011
755d57b2
MD		 1012static const char *r8a7740_boards_compat_dt[] __initdata = {
1013 "renesas,r8a7740",
1014 NULL,
1015};
1016
a41acc4a 1017DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
755d57b2 1018 .map_io = r8a7740_map_io,
744fdc8d
BH		 1019 .init_early = r8a7740_init_delay,
1020 .init_irq = r8a7740_init_irq_of,
1021 .init_machine = r8a7740_generic_init,
1022 .init_time = shmobile_timer_init,
755d57b2
MD		 1023 .dt_compat = r8a7740_boards_compat_dt,
1024MACHINE_END
1025
1026#endif /* CONFIG_USE_OF */
Linux kernel - Deliverables
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