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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7740.c
CommitLineData
6c01ba44
KM		 1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
6831f3a9 20#include <linux/delay.h>
3841e6f5 21#include <linux/dma-mapping.h>
6c01ba44
KM		 22#include <linux/kernel.h>
23#include <linux/init.h>
6831f3a9 24#include <linux/io.h>
6c01ba44 25#include <linux/platform_device.h>
755d57b2 26#include <linux/of_platform.h>
6c01ba44 27#include <linux/serial_sci.h>
643c3307 28#include <linux/sh_dma.h>
6c01ba44 29#include <linux/sh_timer.h>
f671e022 30#include <linux/platform_data/sh_ipmmu.h>
d7de938f 31#include <mach/dma-register.h>
6c01ba44 32#include <mach/r8a7740.h>
8459293c 33#include <mach/pm-rmobile.h>
d3ab7221 34#include <mach/common.h>
250a2723 35#include <mach/irqs.h>
6c01ba44 36#include <asm/mach-types.h>
d3ab7221 37#include <asm/mach/map.h>
6c01ba44 38#include <asm/mach/arch.h>
23e5bc03 39#include <asm/mach/time.h>
6c01ba44 40
d3ab7221
MD		 41static struct map_desc r8a7740_io_desc[] __initdata = {
42 /*
43 * for CPGA/INTC/PFC
44 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
45 */
46 {
47 .virtual = 0xe6000000,
48 .pfn = __phys_to_pfn(0xe6000000),
49 .length = 160 << 20,
50 .type = MT_DEVICE_NONSHARED
51 },
52#ifdef CONFIG_CACHE_L2X0
53 /*
54 * for l2x0_init()
55 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
56 */
57 {
58 .virtual = 0xf0002000,
59 .pfn = __phys_to_pfn(0xf0100000),
60 .length = PAGE_SIZE,
61 .type = MT_DEVICE_NONSHARED
62 },
63#endif
64};
65
66void __init r8a7740_map_io(void)
67{
68 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
69}
70
02b01adb
LP		 71/* PFC */
72static struct resource r8a7740_pfc_resources[] = {
73 [0] = {
74 .start = 0xe6050000,
75 .end = 0xe6057fff,
76 .flags = IORESOURCE_MEM,
77 },
78 [1] = {
79 .start = 0xe605800c,
80 .end = 0xe605802b,
81 .flags = IORESOURCE_MEM,
82 }
83};
84
85static struct platform_device r8a7740_pfc_device = {
86 .name = "pfc-r8a7740",
87 .id = -1,
88 .resource = r8a7740_pfc_resources,
89 .num_resources = ARRAY_SIZE(r8a7740_pfc_resources),
90};
91
92void __init r8a7740_pinmux_init(void)
93{
94 platform_device_register(&r8a7740_pfc_device);
95}
96
6c01ba44
KM		 97/* SCIFA0 */
98static struct plat_sci_port scif0_platform_data = {
99 .mapbase = 0xe6c40000,
100 .flags = UPF_BOOT_AUTOCONF,
101 .scscr = SCSCR_RE | SCSCR_TE,
102 .scbrr_algo_id = SCBRR_ALGO_4,
103 .type = PORT_SCIFA,
215d6cc9 104 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
6c01ba44
KM		 105};
106
107static struct platform_device scif0_device = {
108 .name = "sh-sci",
109 .id = 0,
110 .dev = {
111 .platform_data = &scif0_platform_data,
112 },
113};
114
115/* SCIFA1 */
116static struct plat_sci_port scif1_platform_data = {
117 .mapbase = 0xe6c50000,
118 .flags = UPF_BOOT_AUTOCONF,
119 .scscr = SCSCR_RE | SCSCR_TE,
120 .scbrr_algo_id = SCBRR_ALGO_4,
121 .type = PORT_SCIFA,
215d6cc9 122 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
6c01ba44
KM		 123};
124
125static struct platform_device scif1_device = {
126 .name = "sh-sci",
127 .id = 1,
128 .dev = {
129 .platform_data = &scif1_platform_data,
130 },
131};
132
133/* SCIFA2 */
134static struct plat_sci_port scif2_platform_data = {
135 .mapbase = 0xe6c60000,
136 .flags = UPF_BOOT_AUTOCONF,
137 .scscr = SCSCR_RE | SCSCR_TE,
138 .scbrr_algo_id = SCBRR_ALGO_4,
139 .type = PORT_SCIFA,
215d6cc9 140 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
6c01ba44
KM		 141};
142
143static struct platform_device scif2_device = {
144 .name = "sh-sci",
145 .id = 2,
146 .dev = {
147 .platform_data = &scif2_platform_data,
148 },
149};
150
151/* SCIFA3 */
152static struct plat_sci_port scif3_platform_data = {
153 .mapbase = 0xe6c70000,
154 .flags = UPF_BOOT_AUTOCONF,
155 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4,
157 .type = PORT_SCIFA,
215d6cc9 158 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
6c01ba44
KM		 159};
160
161static struct platform_device scif3_device = {
162 .name = "sh-sci",
163 .id = 3,
164 .dev = {
165 .platform_data = &scif3_platform_data,
166 },
167};
168
169/* SCIFA4 */
170static struct plat_sci_port scif4_platform_data = {
171 .mapbase = 0xe6c80000,
172 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE,
174 .scbrr_algo_id = SCBRR_ALGO_4,
175 .type = PORT_SCIFA,
215d6cc9 176 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
6c01ba44
KM		 177};
178
179static struct platform_device scif4_device = {
180 .name = "sh-sci",
181 .id = 4,
182 .dev = {
183 .platform_data = &scif4_platform_data,
184 },
185};
186
187/* SCIFA5 */
188static struct plat_sci_port scif5_platform_data = {
189 .mapbase = 0xe6cb0000,
190 .flags = UPF_BOOT_AUTOCONF,
191 .scscr = SCSCR_RE | SCSCR_TE,
192 .scbrr_algo_id = SCBRR_ALGO_4,
193 .type = PORT_SCIFA,
215d6cc9 194 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
6c01ba44
KM		 195};
196
197static struct platform_device scif5_device = {
198 .name = "sh-sci",
199 .id = 5,
200 .dev = {
201 .platform_data = &scif5_platform_data,
202 },
203};
204
205/* SCIFA6 */
206static struct plat_sci_port scif6_platform_data = {
207 .mapbase = 0xe6cc0000,
208 .flags = UPF_BOOT_AUTOCONF,
209 .scscr = SCSCR_RE | SCSCR_TE,
210 .scbrr_algo_id = SCBRR_ALGO_4,
211 .type = PORT_SCIFA,
215d6cc9 212 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
6c01ba44
KM		 213};
214
215static struct platform_device scif6_device = {
216 .name = "sh-sci",
217 .id = 6,
218 .dev = {
219 .platform_data = &scif6_platform_data,
220 },
221};
222
223/* SCIFA7 */
224static struct plat_sci_port scif7_platform_data = {
225 .mapbase = 0xe6cd0000,
226 .flags = UPF_BOOT_AUTOCONF,
227 .scscr = SCSCR_RE | SCSCR_TE,
228 .scbrr_algo_id = SCBRR_ALGO_4,
229 .type = PORT_SCIFA,
215d6cc9 230 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
6c01ba44
KM		 231};
232
233static struct platform_device scif7_device = {
234 .name = "sh-sci",
235 .id = 7,
236 .dev = {
237 .platform_data = &scif7_platform_data,
238 },
239};
240
241/* SCIFB */
242static struct plat_sci_port scifb_platform_data = {
243 .mapbase = 0xe6c30000,
244 .flags = UPF_BOOT_AUTOCONF,
245 .scscr = SCSCR_RE | SCSCR_TE,
246 .scbrr_algo_id = SCBRR_ALGO_4,
247 .type = PORT_SCIFB,
215d6cc9 248 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
6c01ba44
KM		 249};
250
251static struct platform_device scifb_device = {
252 .name = "sh-sci",
253 .id = 8,
254 .dev = {
255 .platform_data = &scifb_platform_data,
256 },
257};
258
259/* CMT */
260static struct sh_timer_config cmt10_platform_data = {
261 .name = "CMT10",
262 .channel_offset = 0x10,
263 .timer_bit = 0,
264 .clockevent_rating = 125,
265 .clocksource_rating = 125,
266};
267
268static struct resource cmt10_resources[] = {
269 [0] = {
270 .name = "CMT10",
271 .start = 0xe6138010,
272 .end = 0xe613801b,
273 .flags = IORESOURCE_MEM,
274 },
275 [1] = {
215d6cc9 276 .start = evt2irq(0x0b00),
6c01ba44
KM		 277 .flags = IORESOURCE_IRQ,
278 },
279};
280
281static struct platform_device cmt10_device = {
282 .name = "sh_cmt",
283 .id = 10,
284 .dev = {
285 .platform_data = &cmt10_platform_data,
286 },
287 .resource = cmt10_resources,
288 .num_resources = ARRAY_SIZE(cmt10_resources),
289};
290
e67d7afc
KM		 291/* TMU */
292static struct sh_timer_config tmu00_platform_data = {
293 .name = "TMU00",
294 .channel_offset = 0x4,
295 .timer_bit = 0,
296 .clockevent_rating = 200,
297};
298
299static struct resource tmu00_resources[] = {
300 [0] = {
301 .name = "TMU00",
302 .start = 0xfff80008,
303 .end = 0xfff80014 - 1,
304 .flags = IORESOURCE_MEM,
305 },
306 [1] = {
307 .start = intcs_evt2irq(0xe80),
308 .flags = IORESOURCE_IRQ,
309 },
310};
311
312static struct platform_device tmu00_device = {
313 .name = "sh_tmu",
314 .id = 0,
315 .dev = {
316 .platform_data = &tmu00_platform_data,
317 },
318 .resource = tmu00_resources,
319 .num_resources = ARRAY_SIZE(tmu00_resources),
320};
321
322static struct sh_timer_config tmu01_platform_data = {
323 .name = "TMU01",
324 .channel_offset = 0x10,
325 .timer_bit = 1,
326 .clocksource_rating = 200,
327};
328
329static struct resource tmu01_resources[] = {
330 [0] = {
331 .name = "TMU01",
332 .start = 0xfff80014,
333 .end = 0xfff80020 - 1,
334 .flags = IORESOURCE_MEM,
335 },
336 [1] = {
337 .start = intcs_evt2irq(0xea0),
338 .flags = IORESOURCE_IRQ,
339 },
340};
341
342static struct platform_device tmu01_device = {
343 .name = "sh_tmu",
344 .id = 1,
345 .dev = {
346 .platform_data = &tmu01_platform_data,
347 },
348 .resource = tmu01_resources,
349 .num_resources = ARRAY_SIZE(tmu01_resources),
350};
351
352static struct sh_timer_config tmu02_platform_data = {
353 .name = "TMU02",
354 .channel_offset = 0x1C,
355 .timer_bit = 2,
356 .clocksource_rating = 200,
357};
358
359static struct resource tmu02_resources[] = {
360 [0] = {
361 .name = "TMU02",
362 .start = 0xfff80020,
363 .end = 0xfff8002C - 1,
364 .flags = IORESOURCE_MEM,
365 },
366 [1] = {
367 .start = intcs_evt2irq(0xec0),
368 .flags = IORESOURCE_IRQ,
369 },
370};
371
372static struct platform_device tmu02_device = {
373 .name = "sh_tmu",
374 .id = 2,
375 .dev = {
376 .platform_data = &tmu02_platform_data,
377 },
378 .resource = tmu02_resources,
379 .num_resources = ARRAY_SIZE(tmu02_resources),
380};
381
f671e022
HE		 382/* IPMMUI (an IPMMU module for ICB/LMB) */
383static struct resource ipmmu_resources[] = {
384 [0] = {
385 .name = "IPMMUI",
386 .start = 0xfe951000,
387 .end = 0xfe9510ff,
388 .flags = IORESOURCE_MEM,
389 },
390};
391
392static const char * const ipmmu_dev_names[] = {
393 "sh_mobile_lcdc_fb.0",
394 "sh_mobile_lcdc_fb.1",
395 "sh_mobile_ceu.0",
396};
397
398static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
399 .dev_names = ipmmu_dev_names,
400 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
401};
402
403static struct platform_device ipmmu_device = {
404 .name = "ipmmu",
405 .id = -1,
406 .dev = {
407 .platform_data = &ipmmu_platform_data,
408 },
409 .resource = ipmmu_resources,
410 .num_resources = ARRAY_SIZE(ipmmu_resources),
411};
412
6c01ba44
KM		 413static struct platform_device *r8a7740_early_devices[] __initdata = {
414 &scif0_device,
415 &scif1_device,
416 &scif2_device,
417 &scif3_device,
418 &scif4_device,
419 &scif5_device,
420 &scif6_device,
421 &scif7_device,
422 &scifb_device,
423 &cmt10_device,
e67d7afc
KM		 424 &tmu00_device,
425 &tmu01_device,
426 &tmu02_device,
f671e022 427 &ipmmu_device,
6c01ba44
KM		 428};
429
643c3307 430/* DMA */
643c3307
KM		 431static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
432 {
cb76eb81
KM		 433 .slave_id = SHDMA_SLAVE_SDHI0_TX,
434 .addr = 0xe6850030,
435 .chcr = CHCR_TX(XMIT_SZ_16BIT),
436 .mid_rid = 0xc1,
437 }, {
438 .slave_id = SHDMA_SLAVE_SDHI0_RX,
439 .addr = 0xe6850030,
440 .chcr = CHCR_RX(XMIT_SZ_16BIT),
441 .mid_rid = 0xc2,
442 }, {
443 .slave_id = SHDMA_SLAVE_SDHI1_TX,
444 .addr = 0xe6860030,
445 .chcr = CHCR_TX(XMIT_SZ_16BIT),
446 .mid_rid = 0xc9,
447 }, {
448 .slave_id = SHDMA_SLAVE_SDHI1_RX,
449 .addr = 0xe6860030,
450 .chcr = CHCR_RX(XMIT_SZ_16BIT),
451 .mid_rid = 0xca,
452 }, {
453 .slave_id = SHDMA_SLAVE_SDHI2_TX,
454 .addr = 0xe6870030,
455 .chcr = CHCR_TX(XMIT_SZ_16BIT),
456 .mid_rid = 0xcd,
457 }, {
458 .slave_id = SHDMA_SLAVE_SDHI2_RX,
459 .addr = 0xe6870030,
460 .chcr = CHCR_RX(XMIT_SZ_16BIT),
461 .mid_rid = 0xce,
462 }, {
643c3307
KM		 463 .slave_id = SHDMA_SLAVE_FSIA_TX,
464 .addr = 0xfe1f0024,
465 .chcr = CHCR_TX(XMIT_SZ_32BIT),
466 .mid_rid = 0xb1,
467 }, {
468 .slave_id = SHDMA_SLAVE_FSIA_RX,
469 .addr = 0xfe1f0020,
470 .chcr = CHCR_RX(XMIT_SZ_32BIT),
471 .mid_rid = 0xb2,
472 }, {
473 .slave_id = SHDMA_SLAVE_FSIB_TX,
474 .addr = 0xfe1f0064,
475 .chcr = CHCR_TX(XMIT_SZ_32BIT),
476 .mid_rid = 0xb5,
477 },
478};
479
480#define DMA_CHANNEL(a, b, c) \
481{ \
482 .offset = a, \
483 .dmars = b, \
484 .dmars_bit = c, \
485 .chclr_offset = (0x220 - 0x20) + a \
486}
487
488static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
489 DMA_CHANNEL(0x00, 0, 0),
490 DMA_CHANNEL(0x10, 0, 8),
491 DMA_CHANNEL(0x20, 4, 0),
492 DMA_CHANNEL(0x30, 4, 8),
493 DMA_CHANNEL(0x50, 8, 0),
494 DMA_CHANNEL(0x60, 8, 8),
495};
496
643c3307
KM		 497static struct sh_dmae_pdata dma_platform_data = {
498 .slave = r8a7740_dmae_slaves,
499 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
500 .channel = r8a7740_dmae_channels,
501 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
d7de938f
KM		 502 .ts_low_shift = TS_LOW_SHIFT,
503 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
504 .ts_high_shift = TS_HI_SHIFT,
505 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
506 .ts_shift = dma_ts_shift,
507 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
643c3307
KM		 508 .dmaor_init = DMAOR_DME,
509 .chclr_present = 1,
510};
511
512/* Resource order important! */
513static struct resource r8a7740_dmae0_resources[] = {
514 {
515 /* Channel registers and DMAOR */
516 .start = 0xfe008020,
517 .end = 0xfe00828f,
518 .flags = IORESOURCE_MEM,
519 },
520 {
521 /* DMARSx */
522 .start = 0xfe009000,
523 .end = 0xfe00900b,
524 .flags = IORESOURCE_MEM,
525 },
526 {
527 .name = "error_irq",
528 .start = evt2irq(0x20c0),
529 .end = evt2irq(0x20c0),
530 .flags = IORESOURCE_IRQ,
531 },
532 {
533 /* IRQ for channels 0-5 */
534 .start = evt2irq(0x2000),
535 .end = evt2irq(0x20a0),
536 .flags = IORESOURCE_IRQ,
537 },
538};
539
540/* Resource order important! */
541static struct resource r8a7740_dmae1_resources[] = {
542 {
543 /* Channel registers and DMAOR */
544 .start = 0xfe018020,
545 .end = 0xfe01828f,
546 .flags = IORESOURCE_MEM,
547 },
548 {
549 /* DMARSx */
550 .start = 0xfe019000,
551 .end = 0xfe01900b,
552 .flags = IORESOURCE_MEM,
553 },
554 {
555 .name = "error_irq",
556 .start = evt2irq(0x21c0),
557 .end = evt2irq(0x21c0),
558 .flags = IORESOURCE_IRQ,
559 },
560 {
561 /* IRQ for channels 0-5 */
562 .start = evt2irq(0x2100),
563 .end = evt2irq(0x21a0),
564 .flags = IORESOURCE_IRQ,
565 },
566};
567
568/* Resource order important! */
569static struct resource r8a7740_dmae2_resources[] = {
570 {
571 /* Channel registers and DMAOR */
572 .start = 0xfe028020,
573 .end = 0xfe02828f,
574 .flags = IORESOURCE_MEM,
575 },
576 {
577 /* DMARSx */
578 .start = 0xfe029000,
579 .end = 0xfe02900b,
580 .flags = IORESOURCE_MEM,
581 },
582 {
583 .name = "error_irq",
584 .start = evt2irq(0x22c0),
585 .end = evt2irq(0x22c0),
586 .flags = IORESOURCE_IRQ,
587 },
588 {
589 /* IRQ for channels 0-5 */
590 .start = evt2irq(0x2200),
591 .end = evt2irq(0x22a0),
592 .flags = IORESOURCE_IRQ,
593 },
594};
595
596static struct platform_device dma0_device = {
597 .name = "sh-dma-engine",
598 .id = 0,
599 .resource = r8a7740_dmae0_resources,
600 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
601 .dev = {
602 .platform_data = &dma_platform_data,
603 },
604};
605
606static struct platform_device dma1_device = {
607 .name = "sh-dma-engine",
608 .id = 1,
609 .resource = r8a7740_dmae1_resources,
610 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
611 .dev = {
612 .platform_data = &dma_platform_data,
613 },
614};
615
616static struct platform_device dma2_device = {
617 .name = "sh-dma-engine",
618 .id = 2,
619 .resource = r8a7740_dmae2_resources,
620 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
621 .dev = {
622 .platform_data = &dma_platform_data,
623 },
624};
625
dbf382e5 626/* USB-DMAC */
dbf382e5
KM		 627static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
628 {
629 .offset = 0,
630 }, {
631 .offset = 0x20,
632 },
633};
634
dbf382e5
KM		 635static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
636 {
637 .slave_id = SHDMA_SLAVE_USBHS_TX,
638 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
639 }, {
640 .slave_id = SHDMA_SLAVE_USBHS_RX,
641 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
642 },
643};
644
645static struct sh_dmae_pdata usb_dma_platform_data = {
646 .slave = r8a7740_usb_dma_slaves,
647 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
648 .channel = r8a7740_usb_dma_channels,
649 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
d7de938f
KM		 650 .ts_low_shift = USBTS_LOW_SHIFT,
651 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
652 .ts_high_shift = USBTS_HI_SHIFT,
653 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
dbf382e5
KM		 654 .ts_shift = dma_usbts_shift,
655 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
656 .dmaor_init = DMAOR_DME,
657 .chcr_offset = 0x14,
658 .chcr_ie_bit = 1 << 5,
659 .dmaor_is_32bit = 1,
660 .needs_tend_set = 1,
661 .no_dmars = 1,
662 .slave_only = 1,
663};
664
665static struct resource r8a7740_usb_dma_resources[] = {
666 {
667 /* Channel registers and DMAOR */
668 .start = 0xe68a0020,
669 .end = 0xe68a0064 - 1,
670 .flags = IORESOURCE_MEM,
671 },
672 {
673 /* VCR/SWR/DMICR */
674 .start = 0xe68a0000,
675 .end = 0xe68a0014 - 1,
676 .flags = IORESOURCE_MEM,
677 },
678 {
679 /* IRQ for channels */
680 .start = evt2irq(0x0a00),
681 .end = evt2irq(0x0a00),
682 .flags = IORESOURCE_IRQ,
683 },
684};
685
686static struct platform_device usb_dma_device = {
687 .name = "sh-dma-engine",
688 .id = 3,
689 .resource = r8a7740_usb_dma_resources,
690 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
691 .dev = {
692 .platform_data = &usb_dma_platform_data,
693 },
694};
695
6831f3a9
KM		 696/* I2C */
697static struct resource i2c0_resources[] = {
698 [0] = {
699 .name = "IIC0",
700 .start = 0xfff20000,
701 .end = 0xfff20425 - 1,
702 .flags = IORESOURCE_MEM,
703 },
704 [1] = {
215d6cc9
KM		 705 .start = intcs_evt2irq(0xe00),
706 .end = intcs_evt2irq(0xe60),
6831f3a9
KM		 707 .flags = IORESOURCE_IRQ,
708 },
709};
710
711static struct resource i2c1_resources[] = {
712 [0] = {
713 .name = "IIC1",
714 .start = 0xe6c20000,
715 .end = 0xe6c20425 - 1,
716 .flags = IORESOURCE_MEM,
717 },
718 [1] = {
215d6cc9
KM		 719 .start = evt2irq(0x780), /* IIC1_ALI1 */
720 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
6831f3a9
KM		 721 .flags = IORESOURCE_IRQ,
722 },
723};
724
725static struct platform_device i2c0_device = {
726 .name = "i2c-sh_mobile",
727 .id = 0,
728 .resource = i2c0_resources,
729 .num_resources = ARRAY_SIZE(i2c0_resources),
730};
731
732static struct platform_device i2c1_device = {
733 .name = "i2c-sh_mobile",
734 .id = 1,
735 .resource = i2c1_resources,
736 .num_resources = ARRAY_SIZE(i2c1_resources),
737};
738
86bc52ef
NI		 739static struct resource pmu_resources[] = {
740 [0] = {
741 .start = evt2irq(0x19a0),
742 .end = evt2irq(0x19a0),
743 .flags = IORESOURCE_IRQ,
744 },
745};
746
747static struct platform_device pmu_device = {
748 .name = "arm-pmu",
749 .id = -1,
750 .num_resources = ARRAY_SIZE(pmu_resources),
751 .resource = pmu_resources,
752};
753
6831f3a9
KM		 754static struct platform_device *r8a7740_late_devices[] __initdata = {
755 &i2c0_device,
756 &i2c1_device,
643c3307
KM		 757 &dma0_device,
758 &dma1_device,
759 &dma2_device,
dbf382e5 760 &usb_dma_device,
86bc52ef 761 &pmu_device,
6831f3a9
KM		 762};
763
d49679e5
KM		 764/*
765 * r8a7740 chip has lasting errata on MERAM buffer.
766 * this is work-around for it.
767 * see
768 * "Media RAM (MERAM)" on r8a7740 documentation
769 */
770#define MEBUFCNTR 0xFE950098
771void r8a7740_meram_workaround(void)
772{
773 void __iomem *reg;
774
775 reg = ioremap_nocache(MEBUFCNTR, 4);
776 if (reg) {
777 iowrite32(0x01600164, reg);
778 iounmap(reg);
779 }
780}
781
6831f3a9
KM		 782#define ICCR 0x0004
783#define ICSTART 0x0070
784
785#define i2c_read(reg, offset) ioread8(reg + offset)
786#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
787
788/*
789 * r8a7740 chip has lasting errata on I2C I/O pad reset.
790 * this is work-around for it.
791 */
792static void r8a7740_i2c_workaround(struct platform_device *pdev)
793{
794 struct resource *res;
795 void __iomem *reg;
796
797 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
798 if (unlikely(!res)) {
799 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
800 return;
801 }
802
803 reg = ioremap(res->start, resource_size(res));
804 if (unlikely(!reg)) {
805 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
806 return;
807 }
808
809 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
810 i2c_read(reg, ICCR); /* dummy read */
811
812 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
813 i2c_read(reg, ICSTART); /* dummy read */
814
4228716c 815 udelay(10);
6831f3a9
KM		 816
817 i2c_write(reg, ICCR, 0x01);
6831f3a9 818 i2c_write(reg, ICSTART, 0x00);
4228716c
KM		 819
820 udelay(10);
6831f3a9
KM		 821
822 i2c_write(reg, ICCR, 0x10);
4228716c 823 udelay(10);
6831f3a9 824 i2c_write(reg, ICCR, 0x00);
4228716c 825 udelay(10);
6831f3a9 826 i2c_write(reg, ICCR, 0x10);
4228716c 827 udelay(10);
6831f3a9
KM		 828
829 iounmap(reg);
830}
831
6c01ba44
KM		 832void __init r8a7740_add_standard_devices(void)
833{
6831f3a9
KM		 834 /* I2C work-around */
835 r8a7740_i2c_workaround(&i2c0_device);
836 r8a7740_i2c_workaround(&i2c1_device);
837
7b567407 838 r8a7740_init_pm_domains();
8459293c
KM		 839
840 /* add devices */
6c01ba44
KM		 841 platform_add_devices(r8a7740_early_devices,
842 ARRAY_SIZE(r8a7740_early_devices));
6831f3a9
KM		 843 platform_add_devices(r8a7740_late_devices,
844 ARRAY_SIZE(r8a7740_late_devices));
802a5639
KM		 845
846 /* add devices to PM domain */
847
8bdd9468
RW		 848 rmobile_add_device_to_domain("A3SP", &scif0_device);
849 rmobile_add_device_to_domain("A3SP", &scif1_device);
850 rmobile_add_device_to_domain("A3SP", &scif2_device);
851 rmobile_add_device_to_domain("A3SP", &scif3_device);
852 rmobile_add_device_to_domain("A3SP", &scif4_device);
853 rmobile_add_device_to_domain("A3SP", &scif5_device);
854 rmobile_add_device_to_domain("A3SP", &scif6_device);
855 rmobile_add_device_to_domain("A3SP", &scif7_device);
856 rmobile_add_device_to_domain("A3SP", &scifb_device);
857 rmobile_add_device_to_domain("A3SP", &i2c1_device);
6c01ba44
KM		 858}
859
860void __init r8a7740_add_early_devices(void)
861{
862 early_platform_add_devices(r8a7740_early_devices,
863 ARRAY_SIZE(r8a7740_early_devices));
d3ab7221
MD		 864
865 /* setup early console here as well */
866 shmobile_setup_console();
6c01ba44 867}
755d57b2
MD		 868
869#ifdef CONFIG_USE_OF
870
871void __init r8a7740_add_early_devices_dt(void)
872{
873 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
874
875 early_platform_add_devices(r8a7740_early_devices,
876 ARRAY_SIZE(r8a7740_early_devices));
877
878 /* setup early console here as well */
879 shmobile_setup_console();
880}
881
882static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
883 { }
884};
885
886void __init r8a7740_add_standard_devices_dt(void)
887{
888 /* clocks are setup late during boot in the case of DT */
889 r8a7740_clock_init(0);
890
891 platform_add_devices(r8a7740_early_devices,
892 ARRAY_SIZE(r8a7740_early_devices));
893
894 of_platform_populate(NULL, of_default_bus_match_table,
895 r8a7740_auxdata_lookup, NULL);
896}
897
898static const char *r8a7740_boards_compat_dt[] __initdata = {
899 "renesas,r8a7740",
900 NULL,
901};
902
a41acc4a 903DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
755d57b2
MD		 904 .map_io = r8a7740_map_io,
905 .init_early = r8a7740_add_early_devices_dt,
906 .init_irq = r8a7740_init_irq,
907 .handle_irq = shmobile_handle_irq_intc,
908 .init_machine = r8a7740_add_standard_devices_dt,
6bb27d73 909 .init_time = shmobile_timer_init,
755d57b2
MD		 910 .dt_compat = r8a7740_boards_compat_dt,
911MACHINE_END
912
913#endif /* CONFIG_USE_OF */
Linux kernel - Deliverables
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