[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7740.c

/*
 * R8A7740 processor support
 *
 * Copyright (C) 2011  Renesas Solutions Corp.
 * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/serial_sci.h>
#include <linux/sh_dma.h>
#include <linux/sh_timer.h>
#include <linux/dma-mapping.h>
#include <mach/dma-register.h>
#include <mach/r8a7740.h>
#include <mach/pm-rmobile.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>

static struct map_desc r8a7740_io_desc[] __initdata = {
	 /*
	  * for CPGA/INTC/PFC
	  * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
	  */
	{
		.virtual	= 0xe6000000,
		.pfn		= __phys_to_pfn(0xe6000000),
		.length		= 160 << 20,
		.type		= MT_DEVICE_NONSHARED
	},
#ifdef CONFIG_CACHE_L2X0
	/*
	 * for l2x0_init()
	 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
	 */
	{
		.virtual	= 0xf0002000,
		.pfn		= __phys_to_pfn(0xf0100000),
		.length		= PAGE_SIZE,
		.type		= MT_DEVICE_NONSHARED
	},
#endif
};

void __init r8a7740_map_io(void)
{
	iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));

	/*
	 * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
	 * enough to allocate the frame buffer memory.
	 */
	init_consistent_dma_size(12 << 20);
}

/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = {
	.mapbase	= 0xe6c40000,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE,
	.scbrr_algo_id	= SCBRR_ALGO_4,
	.type		= PORT_SCIFA,
	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x0c00)),
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

/* SCIFA1 */
static struct plat_sci_port scif1_platform_data = {
	.mapbase	= 0xe6c50000,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE,
	.scbrr_algo_id	= SCBRR_ALGO_4,
	.type		= PORT_SCIFA,
	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x0c20)),
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};

/* SCIFA2 */
static struct plat_sci_port scif2_platform_data = {
	.mapbase	= 0xe6c60000,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE,
	.scbrr_algo_id	= SCBRR_ALGO_4,
	.type		= PORT_SCIFA,
	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x0c40)),
};

static struct platform_device scif2_device = {
	.name		= "sh-sci",
	.id		= 2,
	.dev		= {
		.platform_data	= &scif2_platform_data,
	},
};

/* SCIFA3 */
static struct plat_sci_port scif3_platform_data = {
	.mapbase	= 0xe6c70000,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE,
	.scbrr_algo_id	= SCBRR_ALGO_4,
	.type		= PORT_SCIFA,
	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x0c60)),
};

static struct platform_device scif3_device = {
	.name		= "sh-sci",
	.id		= 3,
	.dev		= {
		.platform_data	= &scif3_platform_data,
	},
};

/* SCIFA4 */
static struct plat_sci_port scif4_platform_data = {
	.mapbase	= 0xe6c80000,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE,
	.scbrr_algo_id	= SCBRR_ALGO_4,
	.type		= PORT_SCIFA,
	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x0d20)),
};

static struct platform_device scif4_device = {
	.name		= "sh-sci",
	.id		= 4,
	.dev		= {
		.platform_data	= &scif4_platform_data,
	},
};

/* SCIFA5 */
static struct plat_sci_port scif5_platform_data = {
	.mapbase	= 0xe6cb0000,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE,
	.scbrr_algo_id	= SCBRR_ALGO_4,
	.type		= PORT_SCIFA,
	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x0d40)),
};

static struct platform_device scif5_device = {
	.name		= "sh-sci",
	.id		= 5,
	.dev		= {
		.platform_data	= &scif5_platform_data,
	},
};

/* SCIFA6 */
static struct plat_sci_port scif6_platform_data = {
	.mapbase	= 0xe6cc0000,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE,
	.scbrr_algo_id	= SCBRR_ALGO_4,
	.type		= PORT_SCIFA,
	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x04c0)),
};

static struct platform_device scif6_device = {
	.name		= "sh-sci",
	.id		= 6,
	.dev		= {
		.platform_data	= &scif6_platform_data,
	},
};

/* SCIFA7 */
static struct plat_sci_port scif7_platform_data = {
	.mapbase	= 0xe6cd0000,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE,
	.scbrr_algo_id	= SCBRR_ALGO_4,
	.type		= PORT_SCIFA,
	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x04e0)),
};

static struct platform_device scif7_device = {
	.name		= "sh-sci",
	.id		= 7,
	.dev		= {
		.platform_data	= &scif7_platform_data,
	},
};

/* SCIFB */
static struct plat_sci_port scifb_platform_data = {
	.mapbase	= 0xe6c30000,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE,
	.scbrr_algo_id	= SCBRR_ALGO_4,
	.type		= PORT_SCIFB,
	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x0d60)),
};

static struct platform_device scifb_device = {
	.name		= "sh-sci",
	.id		= 8,
	.dev		= {
		.platform_data	= &scifb_platform_data,
	},
};

/* CMT */
static struct sh_timer_config cmt10_platform_data = {
	.name = "CMT10",
	.channel_offset = 0x10,
	.timer_bit = 0,
	.clockevent_rating = 125,
	.clocksource_rating = 125,
};

static struct resource cmt10_resources[] = {
	[0] = {
		.name	= "CMT10",
		.start	= 0xe6138010,
		.end	= 0xe613801b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0x0b00),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device cmt10_device = {
	.name		= "sh_cmt",
	.id		= 10,
	.dev = {
		.platform_data	= &cmt10_platform_data,
	},
	.resource	= cmt10_resources,
	.num_resources	= ARRAY_SIZE(cmt10_resources),
};

static struct platform_device *r8a7740_early_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&scif4_device,
	&scif5_device,
	&scif6_device,
	&scif7_device,
	&scifb_device,
	&cmt10_device,
};

/* DMA */
static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
	{
		.slave_id	= SHDMA_SLAVE_SDHI0_TX,
		.addr		= 0xe6850030,
		.chcr		= CHCR_TX(XMIT_SZ_16BIT),
		.mid_rid	= 0xc1,
	}, {
		.slave_id	= SHDMA_SLAVE_SDHI0_RX,
		.addr		= 0xe6850030,
		.chcr		= CHCR_RX(XMIT_SZ_16BIT),
		.mid_rid	= 0xc2,
	}, {
		.slave_id	= SHDMA_SLAVE_SDHI1_TX,
		.addr		= 0xe6860030,
		.chcr		= CHCR_TX(XMIT_SZ_16BIT),
		.mid_rid	= 0xc9,
	}, {
		.slave_id	= SHDMA_SLAVE_SDHI1_RX,
		.addr		= 0xe6860030,
		.chcr		= CHCR_RX(XMIT_SZ_16BIT),
		.mid_rid	= 0xca,
	}, {
		.slave_id	= SHDMA_SLAVE_SDHI2_TX,
		.addr		= 0xe6870030,
		.chcr		= CHCR_TX(XMIT_SZ_16BIT),
		.mid_rid	= 0xcd,
	}, {
		.slave_id	= SHDMA_SLAVE_SDHI2_RX,
		.addr		= 0xe6870030,
		.chcr		= CHCR_RX(XMIT_SZ_16BIT),
		.mid_rid	= 0xce,
	}, {
		.slave_id	= SHDMA_SLAVE_FSIA_TX,
		.addr		= 0xfe1f0024,
		.chcr		= CHCR_TX(XMIT_SZ_32BIT),
		.mid_rid	= 0xb1,
	}, {
		.slave_id	= SHDMA_SLAVE_FSIA_RX,
		.addr		= 0xfe1f0020,
		.chcr		= CHCR_RX(XMIT_SZ_32BIT),
		.mid_rid	= 0xb2,
	}, {
		.slave_id	= SHDMA_SLAVE_FSIB_TX,
		.addr		= 0xfe1f0064,
		.chcr		= CHCR_TX(XMIT_SZ_32BIT),
		.mid_rid	= 0xb5,
	},
};

#define DMA_CHANNEL(a, b, c)			\
{						\
	.offset		= a,			\
	.dmars		= b,			\
	.dmars_bit	= c,			\
	.chclr_offset	= (0x220 - 0x20) + a	\
}

static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
	DMA_CHANNEL(0x00, 0, 0),
	DMA_CHANNEL(0x10, 0, 8),
	DMA_CHANNEL(0x20, 4, 0),
	DMA_CHANNEL(0x30, 4, 8),
	DMA_CHANNEL(0x50, 8, 0),
	DMA_CHANNEL(0x60, 8, 8),
};

static struct sh_dmae_pdata dma_platform_data = {
	.slave		= r8a7740_dmae_slaves,
	.slave_num	= ARRAY_SIZE(r8a7740_dmae_slaves),
	.channel	= r8a7740_dmae_channels,
	.channel_num	= ARRAY_SIZE(r8a7740_dmae_channels),
	.ts_low_shift	= TS_LOW_SHIFT,
	.ts_low_mask	= TS_LOW_BIT << TS_LOW_SHIFT,
	.ts_high_shift	= TS_HI_SHIFT,
	.ts_high_mask	= TS_HI_BIT << TS_HI_SHIFT,
	.ts_shift	= dma_ts_shift,
	.ts_shift_num	= ARRAY_SIZE(dma_ts_shift),
	.dmaor_init	= DMAOR_DME,
	.chclr_present	= 1,
};

/* Resource order important! */
static struct resource r8a7740_dmae0_resources[] = {
	{
		/* Channel registers and DMAOR */
		.start	= 0xfe008020,
		.end	= 0xfe00828f,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* DMARSx */
		.start	= 0xfe009000,
		.end	= 0xfe00900b,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "error_irq",
		.start	= evt2irq(0x20c0),
		.end	= evt2irq(0x20c0),
		.flags	= IORESOURCE_IRQ,
	},
	{
		/* IRQ for channels 0-5 */
		.start	= evt2irq(0x2000),
		.end	= evt2irq(0x20a0),
		.flags	= IORESOURCE_IRQ,
	},
};

/* Resource order important! */
static struct resource r8a7740_dmae1_resources[] = {
	{
		/* Channel registers and DMAOR */
		.start	= 0xfe018020,
		.end	= 0xfe01828f,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* DMARSx */
		.start	= 0xfe019000,
		.end	= 0xfe01900b,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "error_irq",
		.start	= evt2irq(0x21c0),
		.end	= evt2irq(0x21c0),
		.flags	= IORESOURCE_IRQ,
	},
	{
		/* IRQ for channels 0-5 */
		.start	= evt2irq(0x2100),
		.end	= evt2irq(0x21a0),
		.flags	= IORESOURCE_IRQ,
	},
};

/* Resource order important! */
static struct resource r8a7740_dmae2_resources[] = {
	{
		/* Channel registers and DMAOR */
		.start	= 0xfe028020,
		.end	= 0xfe02828f,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* DMARSx */
		.start	= 0xfe029000,
		.end	= 0xfe02900b,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "error_irq",
		.start	= evt2irq(0x22c0),
		.end	= evt2irq(0x22c0),
		.flags	= IORESOURCE_IRQ,
	},
	{
		/* IRQ for channels 0-5 */
		.start	= evt2irq(0x2200),
		.end	= evt2irq(0x22a0),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dma0_device = {
	.name		= "sh-dma-engine",
	.id		= 0,
	.resource	= r8a7740_dmae0_resources,
	.num_resources	= ARRAY_SIZE(r8a7740_dmae0_resources),
	.dev		= {
		.platform_data	= &dma_platform_data,
	},
};

static struct platform_device dma1_device = {
	.name		= "sh-dma-engine",
	.id		= 1,
	.resource	= r8a7740_dmae1_resources,
	.num_resources	= ARRAY_SIZE(r8a7740_dmae1_resources),
	.dev		= {
		.platform_data	= &dma_platform_data,
	},
};

static struct platform_device dma2_device = {
	.name		= "sh-dma-engine",
	.id		= 2,
	.resource	= r8a7740_dmae2_resources,
	.num_resources	= ARRAY_SIZE(r8a7740_dmae2_resources),
	.dev		= {
		.platform_data	= &dma_platform_data,
	},
};

/* USB-DMAC */
static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
	{
		.offset = 0,
	}, {
		.offset = 0x20,
	},
};

static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
	{
		.slave_id	= SHDMA_SLAVE_USBHS_TX,
		.chcr		= USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
	}, {
		.slave_id	= SHDMA_SLAVE_USBHS_RX,
		.chcr		= USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
	},
};

static struct sh_dmae_pdata usb_dma_platform_data = {
	.slave		= r8a7740_usb_dma_slaves,
	.slave_num	= ARRAY_SIZE(r8a7740_usb_dma_slaves),
	.channel	= r8a7740_usb_dma_channels,
	.channel_num	= ARRAY_SIZE(r8a7740_usb_dma_channels),
	.ts_low_shift	= USBTS_LOW_SHIFT,
	.ts_low_mask	= USBTS_LOW_BIT << USBTS_LOW_SHIFT,
	.ts_high_shift	= USBTS_HI_SHIFT,
	.ts_high_mask	= USBTS_HI_BIT << USBTS_HI_SHIFT,
	.ts_shift	= dma_usbts_shift,
	.ts_shift_num	= ARRAY_SIZE(dma_usbts_shift),
	.dmaor_init	= DMAOR_DME,
	.chcr_offset	= 0x14,
	.chcr_ie_bit	= 1 << 5,
	.dmaor_is_32bit	= 1,
	.needs_tend_set	= 1,
	.no_dmars	= 1,
	.slave_only	= 1,
};

static struct resource r8a7740_usb_dma_resources[] = {
	{
		/* Channel registers and DMAOR */
		.start	= 0xe68a0020,
		.end	= 0xe68a0064 - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* VCR/SWR/DMICR */
		.start	= 0xe68a0000,
		.end	= 0xe68a0014 - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* IRQ for channels */
		.start	= evt2irq(0x0a00),
		.end	= evt2irq(0x0a00),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device usb_dma_device = {
	.name		= "sh-dma-engine",
	.id		= 3,
	.resource	= r8a7740_usb_dma_resources,
	.num_resources	= ARRAY_SIZE(r8a7740_usb_dma_resources),
	.dev		= {
		.platform_data	= &usb_dma_platform_data,
	},
};

/* I2C */
static struct resource i2c0_resources[] = {
	[0] = {
		.name	= "IIC0",
		.start	= 0xfff20000,
		.end	= 0xfff20425 - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= intcs_evt2irq(0xe00),
		.end	= intcs_evt2irq(0xe60),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct resource i2c1_resources[] = {
	[0] = {
		.name	= "IIC1",
		.start	= 0xe6c20000,
		.end	= 0xe6c20425 - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0x780), /* IIC1_ALI1 */
		.end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device i2c0_device = {
	.name		= "i2c-sh_mobile",
	.id		= 0,
	.resource	= i2c0_resources,
	.num_resources	= ARRAY_SIZE(i2c0_resources),
};

static struct platform_device i2c1_device = {
	.name		= "i2c-sh_mobile",
	.id		= 1,
	.resource	= i2c1_resources,
	.num_resources	= ARRAY_SIZE(i2c1_resources),
};

static struct platform_device *r8a7740_late_devices[] __initdata = {
	&i2c0_device,
	&i2c1_device,
	&dma0_device,
	&dma1_device,
	&dma2_device,
	&usb_dma_device,
};

/*
 * r8a7740 chip has lasting errata on MERAM buffer.
 * this is work-around for it.
 * see
 *	"Media RAM (MERAM)" on r8a7740 documentation
 */
#define MEBUFCNTR	0xFE950098
void r8a7740_meram_workaround(void)
{
	void __iomem *reg;

	reg = ioremap_nocache(MEBUFCNTR, 4);
	if (reg) {
		iowrite32(0x01600164, reg);
		iounmap(reg);
	}
}

#define ICCR	0x0004
#define ICSTART	0x0070

#define i2c_read(reg, offset)		ioread8(reg + offset)
#define i2c_write(reg, offset, data)	iowrite8(data, reg + offset)

/*
 * r8a7740 chip has lasting errata on I2C I/O pad reset.
 * this is work-around for it.
 */
static void r8a7740_i2c_workaround(struct platform_device *pdev)
{
	struct resource *res;
	void __iomem *reg;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(!res)) {
		pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
		return;
	}

	reg = ioremap(res->start, resource_size(res));
	if (unlikely(!reg)) {
		pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
		return;
	}

	i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
	i2c_read(reg, ICCR); /* dummy read */

	i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
	i2c_read(reg, ICSTART); /* dummy read */

	udelay(10);

	i2c_write(reg, ICCR, 0x01);
	i2c_write(reg, ICSTART, 0x00);

	udelay(10);

	i2c_write(reg, ICCR, 0x10);
	udelay(10);
	i2c_write(reg, ICCR, 0x00);
	udelay(10);
	i2c_write(reg, ICCR, 0x10);
	udelay(10);

	iounmap(reg);
}

void __init r8a7740_add_standard_devices(void)
{
	/* I2C work-around */
	r8a7740_i2c_workaround(&i2c0_device);
	r8a7740_i2c_workaround(&i2c1_device);

	/* PM domain */
	rmobile_init_pm_domain(&r8a7740_pd_a4s);

	/* add devices */
	platform_add_devices(r8a7740_early_devices,
			    ARRAY_SIZE(r8a7740_early_devices));
	platform_add_devices(r8a7740_late_devices,
			     ARRAY_SIZE(r8a7740_late_devices));
}

static void __init r8a7740_earlytimer_init(void)
{
	r8a7740_clock_init(0);
	shmobile_earlytimer_init();
}

void __init r8a7740_add_early_devices(void)
{
	early_platform_add_devices(r8a7740_early_devices,
				   ARRAY_SIZE(r8a7740_early_devices));

	/* setup early console here as well */
	shmobile_setup_console();

	/* override timer setup with soc-specific code */
	shmobile_timer.init = r8a7740_earlytimer_init;
}
Commit	Line	Data
6c01ba44 KM	1	/*
	2	* R8A7740 processor support
	3	*
	4	* Copyright (C) 2011 Renesas Solutions Corp.
	5	* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
6831f3a9	20	#include <linux/delay.h>
3841e6f5	21	#include <linux/dma-mapping.h>
6c01ba44 KM	22	#include <linux/kernel.h>
6c01ba44 KM	23	#include <linux/init.h>
6831f3a9	24	#include <linux/io.h>
6c01ba44 KM	25	#include <linux/platform_device.h>
6c01ba44 KM	26	#include <linux/serial_sci.h>
643c3307	27	#include <linux/sh_dma.h>
6c01ba44	28	#include <linux/sh_timer.h>
643c3307	29	#include <linux/dma-mapping.h>
d7de938f	30	#include <mach/dma-register.h>
6c01ba44	31	#include <mach/r8a7740.h>
8459293c	32	#include <mach/pm-rmobile.h>
d3ab7221	33	#include <mach/common.h>
250a2723	34	#include <mach/irqs.h>
6c01ba44	35	#include <asm/mach-types.h>
d3ab7221	36	#include <asm/mach/map.h>
6c01ba44	37	#include <asm/mach/arch.h>
23e5bc03	38	#include <asm/mach/time.h>
6c01ba44	39
d3ab7221 MD	40	static struct map_desc r8a7740_io_desc[] __initdata = {
	41	/*
	42	* for CPGA/INTC/PFC
	43	* 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
	44	*/
	45	{
	46	.virtual = 0xe6000000,
	47	.pfn = __phys_to_pfn(0xe6000000),
	48	.length = 160 << 20,
	49	.type = MT_DEVICE_NONSHARED
	50	},
	51	#ifdef CONFIG_CACHE_L2X0
	52	/*
	53	* for l2x0_init()
	54	* 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
	55	*/
	56	{
	57	.virtual = 0xf0002000,
	58	.pfn = __phys_to_pfn(0xf0100000),
	59	.length = PAGE_SIZE,
	60	.type = MT_DEVICE_NONSHARED
	61	},
	62	#endif
	63	};
	64
	65	void __init r8a7740_map_io(void)
	66	{
	67	iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
3841e6f5 KM	68
	69	/*
	70	* DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
	71	* enough to allocate the frame buffer memory.
	72	*/
	73	init_consistent_dma_size(12 << 20);
d3ab7221 MD	74	}
d3ab7221 MD	75
6c01ba44 KM	76	/* SCIFA0 */
	77	static struct plat_sci_port scif0_platform_data = {
	78	.mapbase = 0xe6c40000,
	79	.flags = UPF_BOOT_AUTOCONF,
	80	.scscr = SCSCR_RE \| SCSCR_TE,
	81	.scbrr_algo_id = SCBRR_ALGO_4,
	82	.type = PORT_SCIFA,
215d6cc9	83	.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
6c01ba44 KM	84	};
	85
	86	static struct platform_device scif0_device = {
	87	.name = "sh-sci",
	88	.id = 0,
	89	.dev = {
	90	.platform_data = &scif0_platform_data,
	91	},
	92	};
	93
	94	/* SCIFA1 */
	95	static struct plat_sci_port scif1_platform_data = {
	96	.mapbase = 0xe6c50000,
	97	.flags = UPF_BOOT_AUTOCONF,
	98	.scscr = SCSCR_RE \| SCSCR_TE,
	99	.scbrr_algo_id = SCBRR_ALGO_4,
	100	.type = PORT_SCIFA,
215d6cc9	101	.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
6c01ba44 KM	102	};
	103
	104	static struct platform_device scif1_device = {
	105	.name = "sh-sci",
	106	.id = 1,
	107	.dev = {
	108	.platform_data = &scif1_platform_data,
	109	},
	110	};
	111
	112	/* SCIFA2 */
	113	static struct plat_sci_port scif2_platform_data = {
	114	.mapbase = 0xe6c60000,
	115	.flags = UPF_BOOT_AUTOCONF,
	116	.scscr = SCSCR_RE \| SCSCR_TE,
	117	.scbrr_algo_id = SCBRR_ALGO_4,
	118	.type = PORT_SCIFA,
215d6cc9	119	.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
6c01ba44 KM	120	};
	121
	122	static struct platform_device scif2_device = {
	123	.name = "sh-sci",
	124	.id = 2,
	125	.dev = {
	126	.platform_data = &scif2_platform_data,
	127	},
	128	};
	129
	130	/* SCIFA3 */
	131	static struct plat_sci_port scif3_platform_data = {
	132	.mapbase = 0xe6c70000,
	133	.flags = UPF_BOOT_AUTOCONF,
	134	.scscr = SCSCR_RE \| SCSCR_TE,
	135	.scbrr_algo_id = SCBRR_ALGO_4,
	136	.type = PORT_SCIFA,
215d6cc9	137	.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
6c01ba44 KM	138	};
	139
	140	static struct platform_device scif3_device = {
	141	.name = "sh-sci",
	142	.id = 3,
	143	.dev = {
	144	.platform_data = &scif3_platform_data,
	145	},
	146	};
	147
	148	/* SCIFA4 */
	149	static struct plat_sci_port scif4_platform_data = {
	150	.mapbase = 0xe6c80000,
	151	.flags = UPF_BOOT_AUTOCONF,
	152	.scscr = SCSCR_RE \| SCSCR_TE,
	153	.scbrr_algo_id = SCBRR_ALGO_4,
	154	.type = PORT_SCIFA,
215d6cc9	155	.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
6c01ba44 KM	156	};
	157
	158	static struct platform_device scif4_device = {
	159	.name = "sh-sci",
	160	.id = 4,
	161	.dev = {
	162	.platform_data = &scif4_platform_data,
	163	},
	164	};
	165
	166	/* SCIFA5 */
	167	static struct plat_sci_port scif5_platform_data = {
	168	.mapbase = 0xe6cb0000,
	169	.flags = UPF_BOOT_AUTOCONF,
	170	.scscr = SCSCR_RE \| SCSCR_TE,
	171	.scbrr_algo_id = SCBRR_ALGO_4,
	172	.type = PORT_SCIFA,
215d6cc9	173	.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
6c01ba44 KM	174	};
	175
	176	static struct platform_device scif5_device = {
	177	.name = "sh-sci",
	178	.id = 5,
	179	.dev = {
	180	.platform_data = &scif5_platform_data,
	181	},
	182	};
	183
	184	/* SCIFA6 */
	185	static struct plat_sci_port scif6_platform_data = {
	186	.mapbase = 0xe6cc0000,
	187	.flags = UPF_BOOT_AUTOCONF,
	188	.scscr = SCSCR_RE \| SCSCR_TE,
	189	.scbrr_algo_id = SCBRR_ALGO_4,
	190	.type = PORT_SCIFA,
215d6cc9	191	.irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
6c01ba44 KM	192	};
	193
	194	static struct platform_device scif6_device = {
	195	.name = "sh-sci",
	196	.id = 6,
	197	.dev = {
	198	.platform_data = &scif6_platform_data,
	199	},
	200	};
	201
	202	/* SCIFA7 */
	203	static struct plat_sci_port scif7_platform_data = {
	204	.mapbase = 0xe6cd0000,
	205	.flags = UPF_BOOT_AUTOCONF,
	206	.scscr = SCSCR_RE \| SCSCR_TE,
	207	.scbrr_algo_id = SCBRR_ALGO_4,
	208	.type = PORT_SCIFA,
215d6cc9	209	.irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
6c01ba44 KM	210	};
	211
	212	static struct platform_device scif7_device = {
	213	.name = "sh-sci",
	214	.id = 7,
	215	.dev = {
	216	.platform_data = &scif7_platform_data,
	217	},
	218	};
	219
	220	/* SCIFB */
	221	static struct plat_sci_port scifb_platform_data = {
	222	.mapbase = 0xe6c30000,
	223	.flags = UPF_BOOT_AUTOCONF,
	224	.scscr = SCSCR_RE \| SCSCR_TE,
	225	.scbrr_algo_id = SCBRR_ALGO_4,
	226	.type = PORT_SCIFB,
215d6cc9	227	.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
6c01ba44 KM	228	};
	229
	230	static struct platform_device scifb_device = {
	231	.name = "sh-sci",
	232	.id = 8,
	233	.dev = {
	234	.platform_data = &scifb_platform_data,
	235	},
	236	};
	237
	238	/* CMT */
	239	static struct sh_timer_config cmt10_platform_data = {
	240	.name = "CMT10",
	241	.channel_offset = 0x10,
	242	.timer_bit = 0,
	243	.clockevent_rating = 125,
	244	.clocksource_rating = 125,
	245	};
	246
	247	static struct resource cmt10_resources[] = {
	248	[0] = {
	249	.name = "CMT10",
	250	.start = 0xe6138010,
	251	.end = 0xe613801b,
	252	.flags = IORESOURCE_MEM,
	253	},
	254	[1] = {
215d6cc9	255	.start = evt2irq(0x0b00),
6c01ba44 KM	256	.flags = IORESOURCE_IRQ,
	257	},
	258	};
	259
	260	static struct platform_device cmt10_device = {
	261	.name = "sh_cmt",
	262	.id = 10,
	263	.dev = {
	264	.platform_data = &cmt10_platform_data,
	265	},
	266	.resource = cmt10_resources,
	267	.num_resources = ARRAY_SIZE(cmt10_resources),
	268	};
	269
	270	static struct platform_device *r8a7740_early_devices[] __initdata = {
	271	&scif0_device,
	272	&scif1_device,
	273	&scif2_device,
	274	&scif3_device,
	275	&scif4_device,
	276	&scif5_device,
	277	&scif6_device,
	278	&scif7_device,
	279	&scifb_device,
	280	&cmt10_device,
	281	};
	282
643c3307	283	/* DMA */
643c3307 KM	284	static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
643c3307 KM	285	{
cb76eb81 KM	286	.slave_id = SHDMA_SLAVE_SDHI0_TX,
	287	.addr = 0xe6850030,
	288	.chcr = CHCR_TX(XMIT_SZ_16BIT),
	289	.mid_rid = 0xc1,
	290	}, {
	291	.slave_id = SHDMA_SLAVE_SDHI0_RX,
	292	.addr = 0xe6850030,
	293	.chcr = CHCR_RX(XMIT_SZ_16BIT),
	294	.mid_rid = 0xc2,
	295	}, {
	296	.slave_id = SHDMA_SLAVE_SDHI1_TX,
	297	.addr = 0xe6860030,
	298	.chcr = CHCR_TX(XMIT_SZ_16BIT),
	299	.mid_rid = 0xc9,
	300	}, {
	301	.slave_id = SHDMA_SLAVE_SDHI1_RX,
	302	.addr = 0xe6860030,
	303	.chcr = CHCR_RX(XMIT_SZ_16BIT),
	304	.mid_rid = 0xca,
	305	}, {
	306	.slave_id = SHDMA_SLAVE_SDHI2_TX,
	307	.addr = 0xe6870030,
	308	.chcr = CHCR_TX(XMIT_SZ_16BIT),
	309	.mid_rid = 0xcd,
	310	}, {
	311	.slave_id = SHDMA_SLAVE_SDHI2_RX,
	312	.addr = 0xe6870030,
	313	.chcr = CHCR_RX(XMIT_SZ_16BIT),
	314	.mid_rid = 0xce,
	315	}, {
643c3307 KM	316	.slave_id = SHDMA_SLAVE_FSIA_TX,
	317	.addr = 0xfe1f0024,
	318	.chcr = CHCR_TX(XMIT_SZ_32BIT),
	319	.mid_rid = 0xb1,
	320	}, {
	321	.slave_id = SHDMA_SLAVE_FSIA_RX,
	322	.addr = 0xfe1f0020,
	323	.chcr = CHCR_RX(XMIT_SZ_32BIT),
	324	.mid_rid = 0xb2,
	325	}, {
	326	.slave_id = SHDMA_SLAVE_FSIB_TX,
	327	.addr = 0xfe1f0064,
	328	.chcr = CHCR_TX(XMIT_SZ_32BIT),
	329	.mid_rid = 0xb5,
	330	},
	331	};
	332
	333	#define DMA_CHANNEL(a, b, c) \
	334	{ \
	335	.offset = a, \
	336	.dmars = b, \
	337	.dmars_bit = c, \
	338	.chclr_offset = (0x220 - 0x20) + a \
	339	}
	340
	341	static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
	342	DMA_CHANNEL(0x00, 0, 0),
	343	DMA_CHANNEL(0x10, 0, 8),
	344	DMA_CHANNEL(0x20, 4, 0),
	345	DMA_CHANNEL(0x30, 4, 8),
	346	DMA_CHANNEL(0x50, 8, 0),
	347	DMA_CHANNEL(0x60, 8, 8),
	348	};
	349
643c3307 KM	350	static struct sh_dmae_pdata dma_platform_data = {
	351	.slave = r8a7740_dmae_slaves,
	352	.slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
	353	.channel = r8a7740_dmae_channels,
	354	.channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
d7de938f KM	355	.ts_low_shift = TS_LOW_SHIFT,
	356	.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
	357	.ts_high_shift = TS_HI_SHIFT,
	358	.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
	359	.ts_shift = dma_ts_shift,
	360	.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
643c3307 KM	361	.dmaor_init = DMAOR_DME,
	362	.chclr_present = 1,
	363	};
	364
	365	/* Resource order important! */
	366	static struct resource r8a7740_dmae0_resources[] = {
	367	{
	368	/* Channel registers and DMAOR */
	369	.start = 0xfe008020,
	370	.end = 0xfe00828f,
	371	.flags = IORESOURCE_MEM,
	372	},
	373	{
	374	/* DMARSx */
	375	.start = 0xfe009000,
	376	.end = 0xfe00900b,
	377	.flags = IORESOURCE_MEM,
	378	},
	379	{
	380	.name = "error_irq",
	381	.start = evt2irq(0x20c0),
	382	.end = evt2irq(0x20c0),
	383	.flags = IORESOURCE_IRQ,
	384	},
	385	{
	386	/* IRQ for channels 0-5 */
	387	.start = evt2irq(0x2000),
	388	.end = evt2irq(0x20a0),
	389	.flags = IORESOURCE_IRQ,
	390	},
	391	};
	392
	393	/* Resource order important! */
	394	static struct resource r8a7740_dmae1_resources[] = {
	395	{
	396	/* Channel registers and DMAOR */
	397	.start = 0xfe018020,
	398	.end = 0xfe01828f,
	399	.flags = IORESOURCE_MEM,
	400	},
	401	{
	402	/* DMARSx */
	403	.start = 0xfe019000,
	404	.end = 0xfe01900b,
	405	.flags = IORESOURCE_MEM,
	406	},
	407	{
	408	.name = "error_irq",
	409	.start = evt2irq(0x21c0),
	410	.end = evt2irq(0x21c0),
	411	.flags = IORESOURCE_IRQ,
	412	},
	413	{
	414	/* IRQ for channels 0-5 */
	415	.start = evt2irq(0x2100),
	416	.end = evt2irq(0x21a0),
	417	.flags = IORESOURCE_IRQ,
	418	},
	419	};
	420
	421	/* Resource order important! */
	422	static struct resource r8a7740_dmae2_resources[] = {
	423	{
	424	/* Channel registers and DMAOR */
425	.start = 0xfe028020,
426	.end = 0xfe02828f,
427	.flags = IORESOURCE_MEM,
428	},
429	{
430	/* DMARSx */
431	.start = 0xfe029000,
432	.end = 0xfe02900b,
433	.flags = IORESOURCE_MEM,
434	},
435	{
436	.name = "error_irq",
437	.start = evt2irq(0x22c0),
438	.end = evt2irq(0x22c0),
439	.flags = IORESOURCE_IRQ,
440	},
441	{
442	/* IRQ for channels 0-5 */
443	.start = evt2irq(0x2200),
444	.end = evt2irq(0x22a0),
445	.flags = IORESOURCE_IRQ,
446	},
447	};
448
449	static struct platform_device dma0_device = {
450	.name = "sh-dma-engine",
451	.id = 0,
452	.resource = r8a7740_dmae0_resources,
453	.num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
454	.dev = {
455	.platform_data = &dma_platform_data,
456	},
457	};
458
459	static struct platform_device dma1_device = {
460	.name = "sh-dma-engine",
461	.id = 1,
462	.resource = r8a7740_dmae1_resources,
463	.num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
464	.dev = {
465	.platform_data = &dma_platform_data,
466	},
467	};
468
469	static struct platform_device dma2_device = {
470	.name = "sh-dma-engine",
471	.id = 2,
472	.resource = r8a7740_dmae2_resources,
473	.num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
474	.dev = {
475	.platform_data = &dma_platform_data,
476	},
477	};
478
dbf382e5	479	/* USB-DMAC */
dbf382e5 KM	480	static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
	481	{
	482	.offset = 0,
	483	}, {
	484	.offset = 0x20,
	485	},
	486	};
	487
dbf382e5 KM	488	static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
	489	{
	490	.slave_id = SHDMA_SLAVE_USBHS_TX,
	491	.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
	492	}, {
	493	.slave_id = SHDMA_SLAVE_USBHS_RX,
	494	.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
	495	},
	496	};
	497
	498	static struct sh_dmae_pdata usb_dma_platform_data = {
	499	.slave = r8a7740_usb_dma_slaves,
	500	.slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
	501	.channel = r8a7740_usb_dma_channels,
	502	.channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
d7de938f KM	503	.ts_low_shift = USBTS_LOW_SHIFT,
	504	.ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
	505	.ts_high_shift = USBTS_HI_SHIFT,
	506	.ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
dbf382e5 KM	507	.ts_shift = dma_usbts_shift,
	508	.ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
	509	.dmaor_init = DMAOR_DME,
	510	.chcr_offset = 0x14,
	511	.chcr_ie_bit = 1 << 5,
	512	.dmaor_is_32bit = 1,
	513	.needs_tend_set = 1,
	514	.no_dmars = 1,
	515	.slave_only = 1,
	516	};
	517
	518	static struct resource r8a7740_usb_dma_resources[] = {
	519	{
	520	/* Channel registers and DMAOR */
	521	.start = 0xe68a0020,
	522	.end = 0xe68a0064 - 1,
	523	.flags = IORESOURCE_MEM,
	524	},
	525	{
	526	/* VCR/SWR/DMICR */
	527	.start = 0xe68a0000,
	528	.end = 0xe68a0014 - 1,
	529	.flags = IORESOURCE_MEM,
	530	},
	531	{
	532	/* IRQ for channels */
	533	.start = evt2irq(0x0a00),
	534	.end = evt2irq(0x0a00),
	535	.flags = IORESOURCE_IRQ,
	536	},
	537	};
	538
	539	static struct platform_device usb_dma_device = {
	540	.name = "sh-dma-engine",
	541	.id = 3,
	542	.resource = r8a7740_usb_dma_resources,
	543	.num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
	544	.dev = {
	545	.platform_data = &usb_dma_platform_data,
	546	},
	547	};
	548
6831f3a9 KM	549	/* I2C */
	550	static struct resource i2c0_resources[] = {
	551	[0] = {
	552	.name = "IIC0",
	553	.start = 0xfff20000,
	554	.end = 0xfff20425 - 1,
	555	.flags = IORESOURCE_MEM,
	556	},
	557	[1] = {
215d6cc9 KM	558	.start = intcs_evt2irq(0xe00),
215d6cc9 KM	559	.end = intcs_evt2irq(0xe60),
6831f3a9 KM	560	.flags = IORESOURCE_IRQ,
	561	},
	562	};
	563
	564	static struct resource i2c1_resources[] = {
	565	[0] = {
	566	.name = "IIC1",
	567	.start = 0xe6c20000,
	568	.end = 0xe6c20425 - 1,
	569	.flags = IORESOURCE_MEM,
	570	},
	571	[1] = {
215d6cc9 KM	572	.start = evt2irq(0x780), /* IIC1_ALI1 */
215d6cc9 KM	573	.end = evt2irq(0x7e0), /* IIC1_DTEI1 */
6831f3a9 KM	574	.flags = IORESOURCE_IRQ,
	575	},
	576	};
	577
	578	static struct platform_device i2c0_device = {
	579	.name = "i2c-sh_mobile",
	580	.id = 0,
	581	.resource = i2c0_resources,
	582	.num_resources = ARRAY_SIZE(i2c0_resources),
	583	};
	584
	585	static struct platform_device i2c1_device = {
	586	.name = "i2c-sh_mobile",
	587	.id = 1,
	588	.resource = i2c1_resources,
	589	.num_resources = ARRAY_SIZE(i2c1_resources),
	590	};
	591
	592	static struct platform_device *r8a7740_late_devices[] __initdata = {
	593	&i2c0_device,
	594	&i2c1_device,
643c3307 KM	595	&dma0_device,
	596	&dma1_device,
	597	&dma2_device,
dbf382e5	598	&usb_dma_device,
6831f3a9 KM	599	};
6831f3a9 KM	600
d49679e5 KM	601	/*
	602	* r8a7740 chip has lasting errata on MERAM buffer.
	603	* this is work-around for it.
	604	* see
	605	* "Media RAM (MERAM)" on r8a7740 documentation
	606	*/
	607	#define MEBUFCNTR 0xFE950098
	608	void r8a7740_meram_workaround(void)
	609	{
	610	void __iomem *reg;
	611
	612	reg = ioremap_nocache(MEBUFCNTR, 4);
	613	if (reg) {
	614	iowrite32(0x01600164, reg);
	615	iounmap(reg);
	616	}
	617	}
	618
6831f3a9 KM	619	#define ICCR 0x0004
	620	#define ICSTART 0x0070
	621
	622	#define i2c_read(reg, offset) ioread8(reg + offset)
	623	#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
	624
	625	/*
	626	* r8a7740 chip has lasting errata on I2C I/O pad reset.
	627	* this is work-around for it.
	628	*/
	629	static void r8a7740_i2c_workaround(struct platform_device *pdev)
	630	{
	631	struct resource *res;
	632	void __iomem *reg;
	633
	634	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	635	if (unlikely(!res)) {
	636	pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
	637	return;
	638	}
	639
	640	reg = ioremap(res->start, resource_size(res));
	641	if (unlikely(!reg)) {
	642	pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
	643	return;
	644	}
	645
	646	i2c_write(reg, ICCR, i2c_read(reg, ICCR) \| 0x80);
	647	i2c_read(reg, ICCR); /* dummy read */
	648
	649	i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) \| 0x10);
	650	i2c_read(reg, ICSTART); /* dummy read */
	651
4228716c	652	udelay(10);
6831f3a9 KM	653
6831f3a9 KM	654	i2c_write(reg, ICCR, 0x01);
6831f3a9	655	i2c_write(reg, ICSTART, 0x00);
4228716c KM	656
4228716c KM	657	udelay(10);
6831f3a9 KM	658
6831f3a9 KM	659	i2c_write(reg, ICCR, 0x10);
4228716c	660	udelay(10);
6831f3a9	661	i2c_write(reg, ICCR, 0x00);
4228716c	662	udelay(10);
6831f3a9	663	i2c_write(reg, ICCR, 0x10);
4228716c	664	udelay(10);
6831f3a9 KM	665
	666	iounmap(reg);
	667	}
	668
6c01ba44 KM	669	void __init r8a7740_add_standard_devices(void)
6c01ba44 KM	670	{
6831f3a9 KM	671	/* I2C work-around */
	672	r8a7740_i2c_workaround(&i2c0_device);
	673	r8a7740_i2c_workaround(&i2c1_device);
	674
8459293c KM	675	/* PM domain */
	676	rmobile_init_pm_domain(&r8a7740_pd_a4s);
	677
	678	/* add devices */
6c01ba44 KM	679	platform_add_devices(r8a7740_early_devices,
6c01ba44 KM	680	ARRAY_SIZE(r8a7740_early_devices));
6831f3a9 KM	681	platform_add_devices(r8a7740_late_devices,
6831f3a9 KM	682	ARRAY_SIZE(r8a7740_late_devices));
6c01ba44 KM	683	}
6c01ba44 KM	684
23e5bc03 MD	685	static void __init r8a7740_earlytimer_init(void)
	686	{
	687	r8a7740_clock_init(0);
	688	shmobile_earlytimer_init();
	689	}
	690
6c01ba44 KM	691	void __init r8a7740_add_early_devices(void)
	692	{
	693	early_platform_add_devices(r8a7740_early_devices,
	694	ARRAY_SIZE(r8a7740_early_devices));
d3ab7221 MD	695
	696	/* setup early console here as well */
	697	shmobile_setup_console();
23e5bc03 MD	698
	699	/* override timer setup with soc-specific code */
	700	shmobile_timer.init = r8a7740_earlytimer_init;
6c01ba44	701	}