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ARM: shmobile: r8a7740: Enable PMU
[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7740.c
CommitLineData
6c01ba44
KM		 1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
6831f3a9 20#include <linux/delay.h>
3841e6f5 21#include <linux/dma-mapping.h>
6c01ba44
KM		 22#include <linux/kernel.h>
23#include <linux/init.h>
6831f3a9 24#include <linux/io.h>
6c01ba44 25#include <linux/platform_device.h>
755d57b2 26#include <linux/of_platform.h>
6c01ba44 27#include <linux/serial_sci.h>
643c3307 28#include <linux/sh_dma.h>
6c01ba44 29#include <linux/sh_timer.h>
643c3307 30#include <linux/dma-mapping.h>
d7de938f 31#include <mach/dma-register.h>
6c01ba44 32#include <mach/r8a7740.h>
8459293c 33#include <mach/pm-rmobile.h>
d3ab7221 34#include <mach/common.h>
250a2723 35#include <mach/irqs.h>
6c01ba44 36#include <asm/mach-types.h>
d3ab7221 37#include <asm/mach/map.h>
6c01ba44 38#include <asm/mach/arch.h>
23e5bc03 39#include <asm/mach/time.h>
6c01ba44 40
d3ab7221
MD		 41static struct map_desc r8a7740_io_desc[] __initdata = {
42 /*
43 * for CPGA/INTC/PFC
44 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
45 */
46 {
47 .virtual = 0xe6000000,
48 .pfn = __phys_to_pfn(0xe6000000),
49 .length = 160 << 20,
50 .type = MT_DEVICE_NONSHARED
51 },
52#ifdef CONFIG_CACHE_L2X0
53 /*
54 * for l2x0_init()
55 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
56 */
57 {
58 .virtual = 0xf0002000,
59 .pfn = __phys_to_pfn(0xf0100000),
60 .length = PAGE_SIZE,
61 .type = MT_DEVICE_NONSHARED
62 },
63#endif
64};
65
66void __init r8a7740_map_io(void)
67{
68 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
3841e6f5
KM		 69
70 /*
71 * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
72 * enough to allocate the frame buffer memory.
73 */
74 init_consistent_dma_size(12 << 20);
d3ab7221
MD		 75}
76
6c01ba44
KM		 77/* SCIFA0 */
78static struct plat_sci_port scif0_platform_data = {
79 .mapbase = 0xe6c40000,
80 .flags = UPF_BOOT_AUTOCONF,
81 .scscr = SCSCR_RE | SCSCR_TE,
82 .scbrr_algo_id = SCBRR_ALGO_4,
83 .type = PORT_SCIFA,
215d6cc9 84 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
6c01ba44
KM		 85};
86
87static struct platform_device scif0_device = {
88 .name = "sh-sci",
89 .id = 0,
90 .dev = {
91 .platform_data = &scif0_platform_data,
92 },
93};
94
95/* SCIFA1 */
96static struct plat_sci_port scif1_platform_data = {
97 .mapbase = 0xe6c50000,
98 .flags = UPF_BOOT_AUTOCONF,
99 .scscr = SCSCR_RE | SCSCR_TE,
100 .scbrr_algo_id = SCBRR_ALGO_4,
101 .type = PORT_SCIFA,
215d6cc9 102 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
6c01ba44
KM		 103};
104
105static struct platform_device scif1_device = {
106 .name = "sh-sci",
107 .id = 1,
108 .dev = {
109 .platform_data = &scif1_platform_data,
110 },
111};
112
113/* SCIFA2 */
114static struct plat_sci_port scif2_platform_data = {
115 .mapbase = 0xe6c60000,
116 .flags = UPF_BOOT_AUTOCONF,
117 .scscr = SCSCR_RE | SCSCR_TE,
118 .scbrr_algo_id = SCBRR_ALGO_4,
119 .type = PORT_SCIFA,
215d6cc9 120 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
6c01ba44
KM		 121};
122
123static struct platform_device scif2_device = {
124 .name = "sh-sci",
125 .id = 2,
126 .dev = {
127 .platform_data = &scif2_platform_data,
128 },
129};
130
131/* SCIFA3 */
132static struct plat_sci_port scif3_platform_data = {
133 .mapbase = 0xe6c70000,
134 .flags = UPF_BOOT_AUTOCONF,
135 .scscr = SCSCR_RE | SCSCR_TE,
136 .scbrr_algo_id = SCBRR_ALGO_4,
137 .type = PORT_SCIFA,
215d6cc9 138 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
6c01ba44
KM		 139};
140
141static struct platform_device scif3_device = {
142 .name = "sh-sci",
143 .id = 3,
144 .dev = {
145 .platform_data = &scif3_platform_data,
146 },
147};
148
149/* SCIFA4 */
150static struct plat_sci_port scif4_platform_data = {
151 .mapbase = 0xe6c80000,
152 .flags = UPF_BOOT_AUTOCONF,
153 .scscr = SCSCR_RE | SCSCR_TE,
154 .scbrr_algo_id = SCBRR_ALGO_4,
155 .type = PORT_SCIFA,
215d6cc9 156 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
6c01ba44
KM		 157};
158
159static struct platform_device scif4_device = {
160 .name = "sh-sci",
161 .id = 4,
162 .dev = {
163 .platform_data = &scif4_platform_data,
164 },
165};
166
167/* SCIFA5 */
168static struct plat_sci_port scif5_platform_data = {
169 .mapbase = 0xe6cb0000,
170 .flags = UPF_BOOT_AUTOCONF,
171 .scscr = SCSCR_RE | SCSCR_TE,
172 .scbrr_algo_id = SCBRR_ALGO_4,
173 .type = PORT_SCIFA,
215d6cc9 174 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
6c01ba44
KM		 175};
176
177static struct platform_device scif5_device = {
178 .name = "sh-sci",
179 .id = 5,
180 .dev = {
181 .platform_data = &scif5_platform_data,
182 },
183};
184
185/* SCIFA6 */
186static struct plat_sci_port scif6_platform_data = {
187 .mapbase = 0xe6cc0000,
188 .flags = UPF_BOOT_AUTOCONF,
189 .scscr = SCSCR_RE | SCSCR_TE,
190 .scbrr_algo_id = SCBRR_ALGO_4,
191 .type = PORT_SCIFA,
215d6cc9 192 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
6c01ba44
KM		 193};
194
195static struct platform_device scif6_device = {
196 .name = "sh-sci",
197 .id = 6,
198 .dev = {
199 .platform_data = &scif6_platform_data,
200 },
201};
202
203/* SCIFA7 */
204static struct plat_sci_port scif7_platform_data = {
205 .mapbase = 0xe6cd0000,
206 .flags = UPF_BOOT_AUTOCONF,
207 .scscr = SCSCR_RE | SCSCR_TE,
208 .scbrr_algo_id = SCBRR_ALGO_4,
209 .type = PORT_SCIFA,
215d6cc9 210 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
6c01ba44
KM		 211};
212
213static struct platform_device scif7_device = {
214 .name = "sh-sci",
215 .id = 7,
216 .dev = {
217 .platform_data = &scif7_platform_data,
218 },
219};
220
221/* SCIFB */
222static struct plat_sci_port scifb_platform_data = {
223 .mapbase = 0xe6c30000,
224 .flags = UPF_BOOT_AUTOCONF,
225 .scscr = SCSCR_RE | SCSCR_TE,
226 .scbrr_algo_id = SCBRR_ALGO_4,
227 .type = PORT_SCIFB,
215d6cc9 228 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
6c01ba44
KM		 229};
230
231static struct platform_device scifb_device = {
232 .name = "sh-sci",
233 .id = 8,
234 .dev = {
235 .platform_data = &scifb_platform_data,
236 },
237};
238
239/* CMT */
240static struct sh_timer_config cmt10_platform_data = {
241 .name = "CMT10",
242 .channel_offset = 0x10,
243 .timer_bit = 0,
244 .clockevent_rating = 125,
245 .clocksource_rating = 125,
246};
247
248static struct resource cmt10_resources[] = {
249 [0] = {
250 .name = "CMT10",
251 .start = 0xe6138010,
252 .end = 0xe613801b,
253 .flags = IORESOURCE_MEM,
254 },
255 [1] = {
215d6cc9 256 .start = evt2irq(0x0b00),
6c01ba44
KM		 257 .flags = IORESOURCE_IRQ,
258 },
259};
260
261static struct platform_device cmt10_device = {
262 .name = "sh_cmt",
263 .id = 10,
264 .dev = {
265 .platform_data = &cmt10_platform_data,
266 },
267 .resource = cmt10_resources,
268 .num_resources = ARRAY_SIZE(cmt10_resources),
269};
270
271static struct platform_device *r8a7740_early_devices[] __initdata = {
272 &scif0_device,
273 &scif1_device,
274 &scif2_device,
275 &scif3_device,
276 &scif4_device,
277 &scif5_device,
278 &scif6_device,
279 &scif7_device,
280 &scifb_device,
281 &cmt10_device,
282};
283
643c3307 284/* DMA */
643c3307
KM		 285static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
286 {
cb76eb81
KM		 287 .slave_id = SHDMA_SLAVE_SDHI0_TX,
288 .addr = 0xe6850030,
289 .chcr = CHCR_TX(XMIT_SZ_16BIT),
290 .mid_rid = 0xc1,
291 }, {
292 .slave_id = SHDMA_SLAVE_SDHI0_RX,
293 .addr = 0xe6850030,
294 .chcr = CHCR_RX(XMIT_SZ_16BIT),
295 .mid_rid = 0xc2,
296 }, {
297 .slave_id = SHDMA_SLAVE_SDHI1_TX,
298 .addr = 0xe6860030,
299 .chcr = CHCR_TX(XMIT_SZ_16BIT),
300 .mid_rid = 0xc9,
301 }, {
302 .slave_id = SHDMA_SLAVE_SDHI1_RX,
303 .addr = 0xe6860030,
304 .chcr = CHCR_RX(XMIT_SZ_16BIT),
305 .mid_rid = 0xca,
306 }, {
307 .slave_id = SHDMA_SLAVE_SDHI2_TX,
308 .addr = 0xe6870030,
309 .chcr = CHCR_TX(XMIT_SZ_16BIT),
310 .mid_rid = 0xcd,
311 }, {
312 .slave_id = SHDMA_SLAVE_SDHI2_RX,
313 .addr = 0xe6870030,
314 .chcr = CHCR_RX(XMIT_SZ_16BIT),
315 .mid_rid = 0xce,
316 }, {
643c3307
KM		 317 .slave_id = SHDMA_SLAVE_FSIA_TX,
318 .addr = 0xfe1f0024,
319 .chcr = CHCR_TX(XMIT_SZ_32BIT),
320 .mid_rid = 0xb1,
321 }, {
322 .slave_id = SHDMA_SLAVE_FSIA_RX,
323 .addr = 0xfe1f0020,
324 .chcr = CHCR_RX(XMIT_SZ_32BIT),
325 .mid_rid = 0xb2,
326 }, {
327 .slave_id = SHDMA_SLAVE_FSIB_TX,
328 .addr = 0xfe1f0064,
329 .chcr = CHCR_TX(XMIT_SZ_32BIT),
330 .mid_rid = 0xb5,
331 },
332};
333
334#define DMA_CHANNEL(a, b, c) \
335{ \
336 .offset = a, \
337 .dmars = b, \
338 .dmars_bit = c, \
339 .chclr_offset = (0x220 - 0x20) + a \
340}
341
342static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
343 DMA_CHANNEL(0x00, 0, 0),
344 DMA_CHANNEL(0x10, 0, 8),
345 DMA_CHANNEL(0x20, 4, 0),
346 DMA_CHANNEL(0x30, 4, 8),
347 DMA_CHANNEL(0x50, 8, 0),
348 DMA_CHANNEL(0x60, 8, 8),
349};
350
643c3307
KM		 351static struct sh_dmae_pdata dma_platform_data = {
352 .slave = r8a7740_dmae_slaves,
353 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
354 .channel = r8a7740_dmae_channels,
355 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
d7de938f
KM		 356 .ts_low_shift = TS_LOW_SHIFT,
357 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
358 .ts_high_shift = TS_HI_SHIFT,
359 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
360 .ts_shift = dma_ts_shift,
361 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
643c3307
KM		 362 .dmaor_init = DMAOR_DME,
363 .chclr_present = 1,
364};
365
366/* Resource order important! */
367static struct resource r8a7740_dmae0_resources[] = {
368 {
369 /* Channel registers and DMAOR */
370 .start = 0xfe008020,
371 .end = 0xfe00828f,
372 .flags = IORESOURCE_MEM,
373 },
374 {
375 /* DMARSx */
376 .start = 0xfe009000,
377 .end = 0xfe00900b,
378 .flags = IORESOURCE_MEM,
379 },
380 {
381 .name = "error_irq",
382 .start = evt2irq(0x20c0),
383 .end = evt2irq(0x20c0),
384 .flags = IORESOURCE_IRQ,
385 },
386 {
387 /* IRQ for channels 0-5 */
388 .start = evt2irq(0x2000),
389 .end = evt2irq(0x20a0),
390 .flags = IORESOURCE_IRQ,
391 },
392};
393
394/* Resource order important! */
395static struct resource r8a7740_dmae1_resources[] = {
396 {
397 /* Channel registers and DMAOR */
398 .start = 0xfe018020,
399 .end = 0xfe01828f,
400 .flags = IORESOURCE_MEM,
401 },
402 {
403 /* DMARSx */
404 .start = 0xfe019000,
405 .end = 0xfe01900b,
406 .flags = IORESOURCE_MEM,
407 },
408 {
409 .name = "error_irq",
410 .start = evt2irq(0x21c0),
411 .end = evt2irq(0x21c0),
412 .flags = IORESOURCE_IRQ,
413 },
414 {
415 /* IRQ for channels 0-5 */
416 .start = evt2irq(0x2100),
417 .end = evt2irq(0x21a0),
418 .flags = IORESOURCE_IRQ,
419 },
420};
421
422/* Resource order important! */
423static struct resource r8a7740_dmae2_resources[] = {
424 {
425 /* Channel registers and DMAOR */
426 .start = 0xfe028020,
427 .end = 0xfe02828f,
428 .flags = IORESOURCE_MEM,
429 },
430 {
431 /* DMARSx */
432 .start = 0xfe029000,
433 .end = 0xfe02900b,
434 .flags = IORESOURCE_MEM,
435 },
436 {
437 .name = "error_irq",
438 .start = evt2irq(0x22c0),
439 .end = evt2irq(0x22c0),
440 .flags = IORESOURCE_IRQ,
441 },
442 {
443 /* IRQ for channels 0-5 */
444 .start = evt2irq(0x2200),
445 .end = evt2irq(0x22a0),
446 .flags = IORESOURCE_IRQ,
447 },
448};
449
450static struct platform_device dma0_device = {
451 .name = "sh-dma-engine",
452 .id = 0,
453 .resource = r8a7740_dmae0_resources,
454 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
455 .dev = {
456 .platform_data = &dma_platform_data,
457 },
458};
459
460static struct platform_device dma1_device = {
461 .name = "sh-dma-engine",
462 .id = 1,
463 .resource = r8a7740_dmae1_resources,
464 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
465 .dev = {
466 .platform_data = &dma_platform_data,
467 },
468};
469
470static struct platform_device dma2_device = {
471 .name = "sh-dma-engine",
472 .id = 2,
473 .resource = r8a7740_dmae2_resources,
474 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
475 .dev = {
476 .platform_data = &dma_platform_data,
477 },
478};
479
dbf382e5 480/* USB-DMAC */
dbf382e5
KM		 481static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
482 {
483 .offset = 0,
484 }, {
485 .offset = 0x20,
486 },
487};
488
dbf382e5
KM		 489static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
490 {
491 .slave_id = SHDMA_SLAVE_USBHS_TX,
492 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
493 }, {
494 .slave_id = SHDMA_SLAVE_USBHS_RX,
495 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
496 },
497};
498
499static struct sh_dmae_pdata usb_dma_platform_data = {
500 .slave = r8a7740_usb_dma_slaves,
501 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
502 .channel = r8a7740_usb_dma_channels,
503 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
d7de938f
KM		 504 .ts_low_shift = USBTS_LOW_SHIFT,
505 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
506 .ts_high_shift = USBTS_HI_SHIFT,
507 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
dbf382e5
KM		 508 .ts_shift = dma_usbts_shift,
509 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
510 .dmaor_init = DMAOR_DME,
511 .chcr_offset = 0x14,
512 .chcr_ie_bit = 1 << 5,
513 .dmaor_is_32bit = 1,
514 .needs_tend_set = 1,
515 .no_dmars = 1,
516 .slave_only = 1,
517};
518
519static struct resource r8a7740_usb_dma_resources[] = {
520 {
521 /* Channel registers and DMAOR */
522 .start = 0xe68a0020,
523 .end = 0xe68a0064 - 1,
524 .flags = IORESOURCE_MEM,
525 },
526 {
527 /* VCR/SWR/DMICR */
528 .start = 0xe68a0000,
529 .end = 0xe68a0014 - 1,
530 .flags = IORESOURCE_MEM,
531 },
532 {
533 /* IRQ for channels */
534 .start = evt2irq(0x0a00),
535 .end = evt2irq(0x0a00),
536 .flags = IORESOURCE_IRQ,
537 },
538};
539
540static struct platform_device usb_dma_device = {
541 .name = "sh-dma-engine",
542 .id = 3,
543 .resource = r8a7740_usb_dma_resources,
544 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
545 .dev = {
546 .platform_data = &usb_dma_platform_data,
547 },
548};
549
6831f3a9
KM		 550/* I2C */
551static struct resource i2c0_resources[] = {
552 [0] = {
553 .name = "IIC0",
554 .start = 0xfff20000,
555 .end = 0xfff20425 - 1,
556 .flags = IORESOURCE_MEM,
557 },
558 [1] = {
215d6cc9
KM		 559 .start = intcs_evt2irq(0xe00),
560 .end = intcs_evt2irq(0xe60),
6831f3a9
KM		 561 .flags = IORESOURCE_IRQ,
562 },
563};
564
565static struct resource i2c1_resources[] = {
566 [0] = {
567 .name = "IIC1",
568 .start = 0xe6c20000,
569 .end = 0xe6c20425 - 1,
570 .flags = IORESOURCE_MEM,
571 },
572 [1] = {
215d6cc9
KM		 573 .start = evt2irq(0x780), /* IIC1_ALI1 */
574 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
6831f3a9
KM		 575 .flags = IORESOURCE_IRQ,
576 },
577};
578
579static struct platform_device i2c0_device = {
580 .name = "i2c-sh_mobile",
581 .id = 0,
582 .resource = i2c0_resources,
583 .num_resources = ARRAY_SIZE(i2c0_resources),
584};
585
586static struct platform_device i2c1_device = {
587 .name = "i2c-sh_mobile",
588 .id = 1,
589 .resource = i2c1_resources,
590 .num_resources = ARRAY_SIZE(i2c1_resources),
591};
592
86bc52ef
NI		 593static struct resource pmu_resources[] = {
594 [0] = {
595 .start = evt2irq(0x19a0),
596 .end = evt2irq(0x19a0),
597 .flags = IORESOURCE_IRQ,
598 },
599};
600
601static struct platform_device pmu_device = {
602 .name = "arm-pmu",
603 .id = -1,
604 .num_resources = ARRAY_SIZE(pmu_resources),
605 .resource = pmu_resources,
606};
607
6831f3a9
KM		 608static struct platform_device *r8a7740_late_devices[] __initdata = {
609 &i2c0_device,
610 &i2c1_device,
643c3307
KM		 611 &dma0_device,
612 &dma1_device,
613 &dma2_device,
dbf382e5 614 &usb_dma_device,
86bc52ef 615 &pmu_device,
6831f3a9
KM		 616};
617
d49679e5
KM		 618/*
619 * r8a7740 chip has lasting errata on MERAM buffer.
620 * this is work-around for it.
621 * see
622 * "Media RAM (MERAM)" on r8a7740 documentation
623 */
624#define MEBUFCNTR 0xFE950098
625void r8a7740_meram_workaround(void)
626{
627 void __iomem *reg;
628
629 reg = ioremap_nocache(MEBUFCNTR, 4);
630 if (reg) {
631 iowrite32(0x01600164, reg);
632 iounmap(reg);
633 }
634}
635
6831f3a9
KM		 636#define ICCR 0x0004
637#define ICSTART 0x0070
638
639#define i2c_read(reg, offset) ioread8(reg + offset)
640#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
641
642/*
643 * r8a7740 chip has lasting errata on I2C I/O pad reset.
644 * this is work-around for it.
645 */
646static void r8a7740_i2c_workaround(struct platform_device *pdev)
647{
648 struct resource *res;
649 void __iomem *reg;
650
651 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
652 if (unlikely(!res)) {
653 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
654 return;
655 }
656
657 reg = ioremap(res->start, resource_size(res));
658 if (unlikely(!reg)) {
659 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
660 return;
661 }
662
663 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
664 i2c_read(reg, ICCR); /* dummy read */
665
666 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
667 i2c_read(reg, ICSTART); /* dummy read */
668
4228716c 669 udelay(10);
6831f3a9
KM		 670
671 i2c_write(reg, ICCR, 0x01);
6831f3a9 672 i2c_write(reg, ICSTART, 0x00);
4228716c
KM		 673
674 udelay(10);
6831f3a9
KM		 675
676 i2c_write(reg, ICCR, 0x10);
4228716c 677 udelay(10);
6831f3a9 678 i2c_write(reg, ICCR, 0x00);
4228716c 679 udelay(10);
6831f3a9 680 i2c_write(reg, ICCR, 0x10);
4228716c 681 udelay(10);
6831f3a9
KM		 682
683 iounmap(reg);
684}
685
6c01ba44
KM		 686void __init r8a7740_add_standard_devices(void)
687{
6831f3a9
KM		 688 /* I2C work-around */
689 r8a7740_i2c_workaround(&i2c0_device);
690 r8a7740_i2c_workaround(&i2c1_device);
691
7b567407 692 r8a7740_init_pm_domains();
8459293c
KM		 693
694 /* add devices */
6c01ba44
KM		 695 platform_add_devices(r8a7740_early_devices,
696 ARRAY_SIZE(r8a7740_early_devices));
6831f3a9
KM		 697 platform_add_devices(r8a7740_late_devices,
698 ARRAY_SIZE(r8a7740_late_devices));
802a5639
KM		 699
700 /* add devices to PM domain */
701
8bdd9468
RW		 702 rmobile_add_device_to_domain("A3SP", &scif0_device);
703 rmobile_add_device_to_domain("A3SP", &scif1_device);
704 rmobile_add_device_to_domain("A3SP", &scif2_device);
705 rmobile_add_device_to_domain("A3SP", &scif3_device);
706 rmobile_add_device_to_domain("A3SP", &scif4_device);
707 rmobile_add_device_to_domain("A3SP", &scif5_device);
708 rmobile_add_device_to_domain("A3SP", &scif6_device);
709 rmobile_add_device_to_domain("A3SP", &scif7_device);
710 rmobile_add_device_to_domain("A3SP", &scifb_device);
711 rmobile_add_device_to_domain("A3SP", &i2c1_device);
6c01ba44
KM		 712}
713
23e5bc03
MD		 714static void __init r8a7740_earlytimer_init(void)
715{
716 r8a7740_clock_init(0);
717 shmobile_earlytimer_init();
718}
719
6c01ba44
KM		 720void __init r8a7740_add_early_devices(void)
721{
722 early_platform_add_devices(r8a7740_early_devices,
723 ARRAY_SIZE(r8a7740_early_devices));
d3ab7221
MD		 724
725 /* setup early console here as well */
726 shmobile_setup_console();
23e5bc03
MD		 727
728 /* override timer setup with soc-specific code */
729 shmobile_timer.init = r8a7740_earlytimer_init;
6c01ba44 730}
755d57b2
MD		 731
732#ifdef CONFIG_USE_OF
733
734void __init r8a7740_add_early_devices_dt(void)
735{
736 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
737
738 early_platform_add_devices(r8a7740_early_devices,
739 ARRAY_SIZE(r8a7740_early_devices));
740
741 /* setup early console here as well */
742 shmobile_setup_console();
743}
744
745static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
746 { }
747};
748
749void __init r8a7740_add_standard_devices_dt(void)
750{
751 /* clocks are setup late during boot in the case of DT */
752 r8a7740_clock_init(0);
753
754 platform_add_devices(r8a7740_early_devices,
755 ARRAY_SIZE(r8a7740_early_devices));
756
757 of_platform_populate(NULL, of_default_bus_match_table,
758 r8a7740_auxdata_lookup, NULL);
759}
760
761static const char *r8a7740_boards_compat_dt[] __initdata = {
762 "renesas,r8a7740",
763 NULL,
764};
765
a41acc4a 766DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
755d57b2
MD		 767 .map_io = r8a7740_map_io,
768 .init_early = r8a7740_add_early_devices_dt,
769 .init_irq = r8a7740_init_irq,
770 .handle_irq = shmobile_handle_irq_intc,
771 .init_machine = r8a7740_add_standard_devices_dt,
772 .timer = &shmobile_timer,
773 .dt_compat = r8a7740_boards_compat_dt,
774MACHINE_END
775
776#endif /* CONFIG_USE_OF */
Linux kernel - Deliverables
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