projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 6c01ba44 KM |
1 | /* |
| 2 | * R8A7740 processor support | |
| 3 | * | |
| 4 | * Copyright (C) 2011 Renesas Solutions Corp. | |
| 5 | * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License as published by | |
| 9 | * the Free Software Foundation; version 2 of the License. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * GNU General Public License for more details. | |
| 6c01ba44 KM |
15 | */ |
| 16 | #include <linux/kernel.h> | |
| 17 | #include <linux/init.h> | |
| 6831f3a9 | 18 | #include <linux/io.h> |
| 70e3f3d4 KM |
19 | #include <linux/irqchip.h> |
| 20 | #include <linux/irqchip/arm-gic.h> | |
| 755d57b2 | 21 | #include <linux/of_platform.h> |
| 9e38b84b | 22 | |
| d3ab7221 | 23 | #include <asm/mach/map.h> |
| 6c01ba44 | 24 | #include <asm/mach/arch.h> |
| 23e5bc03 | 25 | #include <asm/mach/time.h> |
| 9e38b84b | 26 | |
| fd44aa5e | 27 | #include "common.h" |
| 6c01ba44 | 28 | |
| d49679e5 KM |
29 | /* |
| 30 | * r8a7740 chip has lasting errata on MERAM buffer. | |
| 31 | * this is work-around for it. | |
| 32 | * see | |
| 33 | * "Media RAM (MERAM)" on r8a7740 documentation | |
| 34 | */ | |
| 35 | #define MEBUFCNTR 0xFE950098 | |
| 44d88c75 | 36 | static void __init r8a7740_meram_workaround(void) |
| d49679e5 KM |
37 | { |
| 38 | void __iomem *reg; | |
| 39 | ||
| 40 | reg = ioremap_nocache(MEBUFCNTR, 4); | |
| 41 | if (reg) { | |
| 42 | iowrite32(0x01600164, reg); | |
| 43 | iounmap(reg); | |
| 44 | } | |
| 45 | } | |
| 46 | ||
| 44d88c75 | 47 | static void __init r8a7740_init_irq_of(void) |
| 70e3f3d4 KM |
48 | { |
| 49 | void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); | |
| 50 | void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); | |
| 51 | void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); | |
| 52 | ||
| 53 | irqchip_init(); | |
| 54 | ||
| 55 | /* route signals to GIC */ | |
| 56 | iowrite32(0x0, pfc_inta_ctrl); | |
| 57 | ||
| 58 | /* | |
| 59 | * To mask the shared interrupt to SPI 149 we must ensure to set | |
| 60 | * PRIO *and* MASK. Else we run into IRQ floods when registering | |
| 61 | * the intc_irqpin devices | |
| 62 | */ | |
| 63 | iowrite32(0x0, intc_prio_base + 0x0); | |
| 64 | iowrite32(0x0, intc_prio_base + 0x4); | |
| 65 | iowrite32(0x0, intc_prio_base + 0x8); | |
| 66 | iowrite32(0x0, intc_prio_base + 0xc); | |
| 67 | iowrite8(0xff, intc_msk_base + 0x0); | |
| 68 | iowrite8(0xff, intc_msk_base + 0x4); | |
| 69 | iowrite8(0xff, intc_msk_base + 0x8); | |
| 70 | iowrite8(0xff, intc_msk_base + 0xc); | |
| 71 | ||
| 72 | iounmap(intc_prio_base); | |
| 73 | iounmap(intc_msk_base); | |
| 74 | iounmap(pfc_inta_ctrl); | |
| 75 | } | |
| 76 | ||
| 744fdc8d BH |
77 | static void __init r8a7740_generic_init(void) |
| 78 | { | |
| c41215b7 MD |
79 | r8a7740_meram_workaround(); |
| 80 | ||
| 43330674 | 81 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 744fdc8d BH |
82 | } |
| 83 | ||
| 19c233b7 | 84 | static const char *const r8a7740_boards_compat_dt[] __initconst = { |
| 755d57b2 MD |
85 | "renesas,r8a7740", |
| 86 | NULL, | |
| 87 | }; | |
| 88 | ||
| a41acc4a | 89 | DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") |
| 4a6cc501 GU |
90 | .l2c_aux_val = 0, |
| 91 | .l2c_aux_mask = ~0, | |
| a0c1fb0c | 92 | .init_early = shmobile_init_delay, |
| 744fdc8d BH |
93 | .init_irq = r8a7740_init_irq_of, |
| 94 | .init_machine = r8a7740_generic_init, | |
| 34b9fa40 | 95 | .init_late = shmobile_init_late, |
| 755d57b2 MD |
96 | .dt_compat = r8a7740_boards_compat_dt, |
| 97 | MACHINE_END |