[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7779.c

/*
 * r8a7779 processor support
 *
 * Copyright (C) 2011  Renesas Solutions Corp.
 * Copyright (C) 2011  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/serial_sci.h>
#include <linux/sh_intc.h>
#include <linux/sh_timer.h>
#include <mach/hardware.h>
#include <mach/r8a7779.h>
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>

static struct map_desc r8a7779_io_desc[] __initdata = {
	/* 2M entity map for 0xf0000000 (MPCORE) */
	{
		.virtual	= 0xf0000000,
		.pfn		= __phys_to_pfn(0xf0000000),
		.length		= SZ_2M,
		.type		= MT_DEVICE_NONSHARED
	},
	/* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
	{
		.virtual	= 0xfe000000,
		.pfn		= __phys_to_pfn(0xfe000000),
		.length		= SZ_16M,
		.type		= MT_DEVICE_NONSHARED
	},
};

void __init r8a7779_map_io(void)
{
	iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
}

static struct plat_sci_port scif0_platform_data = {
	.mapbase	= 0xffe40000,
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= { gic_spi(88), gic_spi(88),
			    gic_spi(88), gic_spi(88) },
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

static struct plat_sci_port scif1_platform_data = {
	.mapbase	= 0xffe41000,
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= { gic_spi(89), gic_spi(89),
			    gic_spi(89), gic_spi(89) },
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};

static struct plat_sci_port scif2_platform_data = {
	.mapbase	= 0xffe42000,
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= { gic_spi(90), gic_spi(90),
			    gic_spi(90), gic_spi(90) },
};

static struct platform_device scif2_device = {
	.name		= "sh-sci",
	.id		= 2,
	.dev		= {
		.platform_data	= &scif2_platform_data,
	},
};

static struct plat_sci_port scif3_platform_data = {
	.mapbase	= 0xffe43000,
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= { gic_spi(91), gic_spi(91),
			    gic_spi(91), gic_spi(91) },
};

static struct platform_device scif3_device = {
	.name		= "sh-sci",
	.id		= 3,
	.dev		= {
		.platform_data	= &scif3_platform_data,
	},
};

static struct plat_sci_port scif4_platform_data = {
	.mapbase	= 0xffe44000,
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= { gic_spi(92), gic_spi(92),
			    gic_spi(92), gic_spi(92) },
};

static struct platform_device scif4_device = {
	.name		= "sh-sci",
	.id		= 4,
	.dev		= {
		.platform_data	= &scif4_platform_data,
	},
};

static struct plat_sci_port scif5_platform_data = {
	.mapbase	= 0xffe45000,
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= { gic_spi(93), gic_spi(93),
			    gic_spi(93), gic_spi(93) },
};

static struct platform_device scif5_device = {
	.name		= "sh-sci",
	.id		= 5,
	.dev		= {
		.platform_data	= &scif5_platform_data,
	},
};

/* TMU */
static struct sh_timer_config tmu00_platform_data = {
	.name = "TMU00",
	.channel_offset = 0x4,
	.timer_bit = 0,
	.clockevent_rating = 200,
};

static struct resource tmu00_resources[] = {
	[0] = {
		.name	= "TMU00",
		.start	= 0xffd80008,
		.end	= 0xffd80013,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= gic_spi(32),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu00_device = {
	.name		= "sh_tmu",
	.id		= 0,
	.dev = {
		.platform_data	= &tmu00_platform_data,
	},
	.resource	= tmu00_resources,
	.num_resources	= ARRAY_SIZE(tmu00_resources),
};

static struct sh_timer_config tmu01_platform_data = {
	.name = "TMU01",
	.channel_offset = 0x10,
	.timer_bit = 1,
	.clocksource_rating = 200,
};

static struct resource tmu01_resources[] = {
	[0] = {
		.name	= "TMU01",
		.start	= 0xffd80014,
		.end	= 0xffd8001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= gic_spi(33),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu01_device = {
	.name		= "sh_tmu",
	.id		= 1,
	.dev = {
		.platform_data	= &tmu01_platform_data,
	},
	.resource	= tmu01_resources,
	.num_resources	= ARRAY_SIZE(tmu01_resources),
};

static struct platform_device *r8a7779_early_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&scif4_device,
	&scif5_device,
	&tmu00_device,
	&tmu01_device,
};

static struct platform_device *r8a7779_late_devices[] __initdata = {
};

void __init r8a7779_add_standard_devices(void)
{
#ifdef CONFIG_CACHE_L2X0
	/* Early BRESP enable, Shared attribute override enable, 64K*16way */
	l2x0_init(__io(0xf0100000), 0x40470000, 0x82000fff);
#endif
	r8a7779_pm_init();

	r8a7779_init_pm_domain(&r8a7779_sh4a);
	r8a7779_init_pm_domain(&r8a7779_sgx);
	r8a7779_init_pm_domain(&r8a7779_vdp1);
	r8a7779_init_pm_domain(&r8a7779_impx3);

	platform_add_devices(r8a7779_early_devices,
			    ARRAY_SIZE(r8a7779_early_devices));
	platform_add_devices(r8a7779_late_devices,
			    ARRAY_SIZE(r8a7779_late_devices));
}

void __init r8a7779_add_early_devices(void)
{
	early_platform_add_devices(r8a7779_early_devices,
				   ARRAY_SIZE(r8a7779_early_devices));

	/* Early serial console setup is not included here due to
	 * memory map collisions. The SCIF serial ports in r8a7779
	 * are difficult to entity map 1:1 due to collision with the
	 * virtual memory range used by the coherent DMA code on ARM.
	 *
	 * Anyone wanting to debug early can remove UPF_IOREMAP from
	 * the sh-sci serial console platform data, adjust mapbase
	 * to a static M:N virt:phys mapping that needs to be added to
	 * the mappings passed with iotable_init() above.
	 *
	 * Then add a call to shmobile_setup_console() from this function.
	 *
	 * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
	 * command line in case of the marzen board.
	 */
}
Commit	Line	Data
f411fade MD	1	/*
	2	* r8a7779 processor support
	3	*
	4	* Copyright (C) 2011 Renesas Solutions Corp.
	5	* Copyright (C) 2011 Magnus Damm
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/irq.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/delay.h>
	26	#include <linux/input.h>
	27	#include <linux/io.h>
	28	#include <linux/serial_sci.h>
	29	#include <linux/sh_intc.h>
	30	#include <linux/sh_timer.h>
	31	#include <mach/hardware.h>
	32	#include <mach/r8a7779.h>
a662c082	33	#include <mach/common.h>
f411fade MD	34	#include <asm/mach-types.h>
f411fade MD	35	#include <asm/mach/arch.h>
3e353b87	36	#include <asm/mach/map.h>
8bac13f5	37	#include <asm/hardware/cache-l2x0.h>
3e353b87 MD	38
	39	static struct map_desc r8a7779_io_desc[] __initdata = {
	40	/* 2M entity map for 0xf0000000 (MPCORE) */
	41	{
	42	.virtual = 0xf0000000,
	43	.pfn = __phys_to_pfn(0xf0000000),
	44	.length = SZ_2M,
	45	.type = MT_DEVICE_NONSHARED
	46	},
	47	/* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
	48	{
	49	.virtual = 0xfe000000,
	50	.pfn = __phys_to_pfn(0xfe000000),
	51	.length = SZ_16M,
	52	.type = MT_DEVICE_NONSHARED
	53	},
	54	};
	55
	56	void __init r8a7779_map_io(void)
	57	{
	58	iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
	59	}
f411fade MD	60
	61	static struct plat_sci_port scif0_platform_data = {
	62	.mapbase = 0xffe40000,
	63	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP,
	64	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
	65	.scbrr_algo_id = SCBRR_ALGO_2,
	66	.type = PORT_SCIF,
	67	.irqs = { gic_spi(88), gic_spi(88),
	68	gic_spi(88), gic_spi(88) },
	69	};
	70
	71	static struct platform_device scif0_device = {
	72	.name = "sh-sci",
	73	.id = 0,
	74	.dev = {
	75	.platform_data = &scif0_platform_data,
	76	},
	77	};
	78
	79	static struct plat_sci_port scif1_platform_data = {
	80	.mapbase = 0xffe41000,
	81	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP,
	82	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
	83	.scbrr_algo_id = SCBRR_ALGO_2,
	84	.type = PORT_SCIF,
	85	.irqs = { gic_spi(89), gic_spi(89),
	86	gic_spi(89), gic_spi(89) },
	87	};
	88
	89	static struct platform_device scif1_device = {
	90	.name = "sh-sci",
	91	.id = 1,
	92	.dev = {
	93	.platform_data = &scif1_platform_data,
	94	},
	95	};
	96
	97	static struct plat_sci_port scif2_platform_data = {
	98	.mapbase = 0xffe42000,
	99	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP,
	100	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
	101	.scbrr_algo_id = SCBRR_ALGO_2,
	102	.type = PORT_SCIF,
	103	.irqs = { gic_spi(90), gic_spi(90),
	104	gic_spi(90), gic_spi(90) },
	105	};
	106
	107	static struct platform_device scif2_device = {
	108	.name = "sh-sci",
	109	.id = 2,
	110	.dev = {
	111	.platform_data = &scif2_platform_data,
	112	},
	113	};
	114
	115	static struct plat_sci_port scif3_platform_data = {
	116	.mapbase = 0xffe43000,
	117	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP,
	118	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
	119	.scbrr_algo_id = SCBRR_ALGO_2,
	120	.type = PORT_SCIF,
	121	.irqs = { gic_spi(91), gic_spi(91),
	122	gic_spi(91), gic_spi(91) },
	123	};
124
125	static struct platform_device scif3_device = {
126	.name = "sh-sci",
127	.id = 3,
128	.dev = {
129	.platform_data = &scif3_platform_data,
130	},
131	};
132
133	static struct plat_sci_port scif4_platform_data = {
134	.mapbase = 0xffe44000,
135	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP,
136	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
137	.scbrr_algo_id = SCBRR_ALGO_2,
138	.type = PORT_SCIF,
139	.irqs = { gic_spi(92), gic_spi(92),
140	gic_spi(92), gic_spi(92) },
141	};
142
143	static struct platform_device scif4_device = {
144	.name = "sh-sci",
145	.id = 4,
146	.dev = {
147	.platform_data = &scif4_platform_data,
148	},
149	};
150
151	static struct plat_sci_port scif5_platform_data = {
152	.mapbase = 0xffe45000,
153	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP,
154	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
155	.scbrr_algo_id = SCBRR_ALGO_2,
156	.type = PORT_SCIF,
157	.irqs = { gic_spi(93), gic_spi(93),
158	gic_spi(93), gic_spi(93) },
159	};
160
161	static struct platform_device scif5_device = {
162	.name = "sh-sci",
163	.id = 5,
164	.dev = {
165	.platform_data = &scif5_platform_data,
166	},
167	};
168
169	/* TMU */
170	static struct sh_timer_config tmu00_platform_data = {
171	.name = "TMU00",
172	.channel_offset = 0x4,
173	.timer_bit = 0,
174	.clockevent_rating = 200,
175	};
176
177	static struct resource tmu00_resources[] = {
178	[0] = {
179	.name = "TMU00",
180	.start = 0xffd80008,
181	.end = 0xffd80013,
182	.flags = IORESOURCE_MEM,
183	},
184	[1] = {
185	.start = gic_spi(32),
186	.flags = IORESOURCE_IRQ,
187	},
188	};
189
190	static struct platform_device tmu00_device = {
191	.name = "sh_tmu",
192	.id = 0,
193	.dev = {
194	.platform_data = &tmu00_platform_data,
195	},
196	.resource = tmu00_resources,
197	.num_resources = ARRAY_SIZE(tmu00_resources),
198	};
199
200	static struct sh_timer_config tmu01_platform_data = {
201	.name = "TMU01",
202	.channel_offset = 0x10,
203	.timer_bit = 1,
204	.clocksource_rating = 200,
205	};
206
207	static struct resource tmu01_resources[] = {
208	[0] = {
209	.name = "TMU01",
210	.start = 0xffd80014,
211	.end = 0xffd8001f,
212	.flags = IORESOURCE_MEM,
213	},
214	[1] = {
215	.start = gic_spi(33),
216	.flags = IORESOURCE_IRQ,
217	},
218	};
219
220	static struct platform_device tmu01_device = {
221	.name = "sh_tmu",
222	.id = 1,
223	.dev = {
224	.platform_data = &tmu01_platform_data,
225	},
226	.resource = tmu01_resources,
227	.num_resources = ARRAY_SIZE(tmu01_resources),
228	};
229
230	static struct platform_device *r8a7779_early_devices[] __initdata = {
231	&scif0_device,
232	&scif1_device,
233	&scif2_device,
234	&scif3_device,
235	&scif4_device,
236	&scif5_device,
237	&tmu00_device,
238	&tmu01_device,
239	};
240
241	static struct platform_device *r8a7779_late_devices[] __initdata = {
242	};
243
244	void __init r8a7779_add_standard_devices(void)
245	{
8bac13f5 MD	246	#ifdef CONFIG_CACHE_L2X0
	247	/* Early BRESP enable, Shared attribute override enable, 64K16way /
	248	l2x0_init(__io(0xf0100000), 0x40470000, 0x82000fff);
	249	#endif
a662c082 MD	250	r8a7779_pm_init();
	251
	252	r8a7779_init_pm_domain(&r8a7779_sh4a);
	253	r8a7779_init_pm_domain(&r8a7779_sgx);
	254	r8a7779_init_pm_domain(&r8a7779_vdp1);
	255	r8a7779_init_pm_domain(&r8a7779_impx3);
	256
f411fade MD	257	platform_add_devices(r8a7779_early_devices,
	258	ARRAY_SIZE(r8a7779_early_devices));
	259	platform_add_devices(r8a7779_late_devices,
	260	ARRAY_SIZE(r8a7779_late_devices));
	261	}
	262
	263	void __init r8a7779_add_early_devices(void)
	264	{
	265	early_platform_add_devices(r8a7779_early_devices,
	266	ARRAY_SIZE(r8a7779_early_devices));
3e353b87 MD	267
	268	/* Early serial console setup is not included here due to
	269	* memory map collisions. The SCIF serial ports in r8a7779
	270	* are difficult to entity map 1:1 due to collision with the
	271	* virtual memory range used by the coherent DMA code on ARM.
	272	*
	273	* Anyone wanting to debug early can remove UPF_IOREMAP from
	274	* the sh-sci serial console platform data, adjust mapbase
	275	* to a static M:N virt:phys mapping that needs to be added to
	276	* the mappings passed with iotable_init() above.
	277	*
	278	* Then add a call to shmobile_setup_console() from this function.
	279	*
	280	* As a final step pass earlyprint=sh-sci.2,115200 on the kernel
	281	* command line in case of the marzen board.
	282	*/
f411fade	283	}