[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7779.c

/*
 * r8a7779 processor support
 *
 * Copyright (C) 2011, 2013  Renesas Solutions Corp.
 * Copyright (C) 2011  Magnus Damm
 * Copyright (C) 2013  Cogent Embedded, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/of_platform.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/serial_sci.h>
#include <linux/sh_intc.h>
#include <linux/sh_timer.h>
#include <linux/dma-mapping.h>
#include <linux/usb/otg.h>
#include <linux/usb/hcd.h>
#include <linux/usb/ehci_pdriver.h>
#include <linux/usb/ohci_pdriver.h>
#include <linux/pm_runtime.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/r8a7779.h>
#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>

static struct map_desc r8a7779_io_desc[] __initdata = {
	/* 2M entity map for 0xf0000000 (MPCORE) */
	{
		.virtual	= 0xf0000000,
		.pfn		= __phys_to_pfn(0xf0000000),
		.length		= SZ_2M,
		.type		= MT_DEVICE_NONSHARED
	},
	/* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
	{
		.virtual	= 0xfe000000,
		.pfn		= __phys_to_pfn(0xfe000000),
		.length		= SZ_16M,
		.type		= MT_DEVICE_NONSHARED
	},
};

void __init r8a7779_map_io(void)
{
	iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
}

static struct resource r8a7779_pfc_resources[] = {
	DEFINE_RES_MEM(0xfffc0000, 0x023c),
};

static struct platform_device r8a7779_pfc_device = {
	.name		= "pfc-r8a7779",
	.id		= -1,
	.resource	= r8a7779_pfc_resources,
	.num_resources	= ARRAY_SIZE(r8a7779_pfc_resources),
};

#define R8A7779_GPIO(idx, npins) \
static struct resource r8a7779_gpio##idx##_resources[] = {		\
	DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),		\
	DEFINE_RES_IRQ(gic_iid(0xad + (idx))),				\
};									\
									\
static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {	\
	.gpio_base	= 32 * (idx),					\
	.irq_base	= 0,						\
	.number_of_pins	= npins,					\
	.pctl_name	= "pfc-r8a7779",				\
};									\
									\
static struct platform_device r8a7779_gpio##idx##_device = {		\
	.name		= "gpio_rcar",					\
	.id		= idx,						\
	.resource	= r8a7779_gpio##idx##_resources,		\
	.num_resources	= ARRAY_SIZE(r8a7779_gpio##idx##_resources),	\
	.dev		= {						\
		.platform_data	= &r8a7779_gpio##idx##_platform_data,	\
	},								\
}

R8A7779_GPIO(0, 32);
R8A7779_GPIO(1, 32);
R8A7779_GPIO(2, 32);
R8A7779_GPIO(3, 32);
R8A7779_GPIO(4, 32);
R8A7779_GPIO(5, 32);
R8A7779_GPIO(6, 9);

static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
	&r8a7779_pfc_device,
	&r8a7779_gpio0_device,
	&r8a7779_gpio1_device,
	&r8a7779_gpio2_device,
	&r8a7779_gpio3_device,
	&r8a7779_gpio4_device,
	&r8a7779_gpio5_device,
	&r8a7779_gpio6_device,
};

void __init r8a7779_pinmux_init(void)
{
	platform_add_devices(r8a7779_pinctrl_devices,
			    ARRAY_SIZE(r8a7779_pinctrl_devices));
}

static struct plat_sci_port scif0_platform_data = {
	.mapbase	= 0xffe40000,
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= SCIx_IRQ_MUXED(gic_iid(0x78)),
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

static struct plat_sci_port scif1_platform_data = {
	.mapbase	= 0xffe41000,
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= SCIx_IRQ_MUXED(gic_iid(0x79)),
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};

static struct plat_sci_port scif2_platform_data = {
	.mapbase	= 0xffe42000,
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= SCIx_IRQ_MUXED(gic_iid(0x7a)),
};

static struct platform_device scif2_device = {
	.name		= "sh-sci",
	.id		= 2,
	.dev		= {
		.platform_data	= &scif2_platform_data,
	},
};

static struct plat_sci_port scif3_platform_data = {
	.mapbase	= 0xffe43000,
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= SCIx_IRQ_MUXED(gic_iid(0x7b)),
};

static struct platform_device scif3_device = {
	.name		= "sh-sci",
	.id		= 3,
	.dev		= {
		.platform_data	= &scif3_platform_data,
	},
};

static struct plat_sci_port scif4_platform_data = {
	.mapbase	= 0xffe44000,
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= SCIx_IRQ_MUXED(gic_iid(0x7c)),
};

static struct platform_device scif4_device = {
	.name		= "sh-sci",
	.id		= 4,
	.dev		= {
		.platform_data	= &scif4_platform_data,
	},
};

static struct plat_sci_port scif5_platform_data = {
	.mapbase	= 0xffe45000,
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= SCIx_IRQ_MUXED(gic_iid(0x7d)),
};

static struct platform_device scif5_device = {
	.name		= "sh-sci",
	.id		= 5,
	.dev		= {
		.platform_data	= &scif5_platform_data,
	},
};

/* TMU */
static struct sh_timer_config tmu00_platform_data = {
	.name = "TMU00",
	.channel_offset = 0x4,
	.timer_bit = 0,
	.clockevent_rating = 200,
};

static struct resource tmu00_resources[] = {
	[0] = {
		.name	= "TMU00",
		.start	= 0xffd80008,
		.end	= 0xffd80013,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= gic_iid(0x40),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu00_device = {
	.name		= "sh_tmu",
	.id		= 0,
	.dev = {
		.platform_data	= &tmu00_platform_data,
	},
	.resource	= tmu00_resources,
	.num_resources	= ARRAY_SIZE(tmu00_resources),
};

static struct sh_timer_config tmu01_platform_data = {
	.name = "TMU01",
	.channel_offset = 0x10,
	.timer_bit = 1,
	.clocksource_rating = 200,
};

static struct resource tmu01_resources[] = {
	[0] = {
		.name	= "TMU01",
		.start	= 0xffd80014,
		.end	= 0xffd8001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= gic_iid(0x41),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu01_device = {
	.name		= "sh_tmu",
	.id		= 1,
	.dev = {
		.platform_data	= &tmu01_platform_data,
	},
	.resource	= tmu01_resources,
	.num_resources	= ARRAY_SIZE(tmu01_resources),
};

/* I2C */
static struct resource rcar_i2c0_res[] = {
	{
		.start  = 0xffc70000,
		.end    = 0xffc70fff,
		.flags  = IORESOURCE_MEM,
	}, {
		.start  = gic_iid(0x6f),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device i2c0_device = {
	.name		= "i2c-rcar",
	.id		= 0,
	.resource	= rcar_i2c0_res,
	.num_resources	= ARRAY_SIZE(rcar_i2c0_res),
};

static struct resource rcar_i2c1_res[] = {
	{
		.start  = 0xffc71000,
		.end    = 0xffc71fff,
		.flags  = IORESOURCE_MEM,
	}, {
		.start  = gic_iid(0x72),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device i2c1_device = {
	.name		= "i2c-rcar",
	.id		= 1,
	.resource	= rcar_i2c1_res,
	.num_resources	= ARRAY_SIZE(rcar_i2c1_res),
};

static struct resource rcar_i2c2_res[] = {
	{
		.start  = 0xffc72000,
		.end    = 0xffc72fff,
		.flags  = IORESOURCE_MEM,
	}, {
		.start  = gic_iid(0x70),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device i2c2_device = {
	.name		= "i2c-rcar",
	.id		= 2,
	.resource	= rcar_i2c2_res,
	.num_resources	= ARRAY_SIZE(rcar_i2c2_res),
};

static struct resource rcar_i2c3_res[] = {
	{
		.start  = 0xffc73000,
		.end    = 0xffc73fff,
		.flags  = IORESOURCE_MEM,
	}, {
		.start  = gic_iid(0x71),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device i2c3_device = {
	.name		= "i2c-rcar",
	.id		= 3,
	.resource	= rcar_i2c3_res,
	.num_resources	= ARRAY_SIZE(rcar_i2c3_res),
};

static struct resource sata_resources[] = {
	[0] = {
		.name	= "rcar-sata",
		.start	= 0xfc600000,
		.end	= 0xfc601fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= gic_iid(0x84),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device sata_device = {
	.name		= "sata_rcar",
	.id		= -1,
	.resource	= sata_resources,
	.num_resources	= ARRAY_SIZE(sata_resources),
	.dev		= {
		.dma_mask		= &sata_device.dev.coherent_dma_mask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
};

/* USB PHY */
static struct resource usb_phy_resources[] = {
	[0] = {
		.start		= 0xffe70000,
		.end		= 0xffe70900 - 1,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
		.start		= 0xfff70000,
		.end		= 0xfff70900 - 1,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device usb_phy_device = {
	.name		= "rcar_usb_phy",
	.id		= -1,
	.resource	= usb_phy_resources,
	.num_resources	= ARRAY_SIZE(usb_phy_resources),
};

/* USB */
static struct usb_phy *phy;

static int usb_power_on(struct platform_device *pdev)
{
	if (IS_ERR(phy))
		return PTR_ERR(phy);

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	usb_phy_init(phy);

	return 0;
}

static void usb_power_off(struct platform_device *pdev)
{
	if (IS_ERR(phy))
		return;

	usb_phy_shutdown(phy);

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
}

static int ehci_init_internal_buffer(struct usb_hcd *hcd)
{
	/*
	 * Below are recommended values from the datasheet;
	 * see [USB :: Setting of EHCI Internal Buffer].
	 */
	/* EHCI IP internal buffer setting */
	iowrite32(0x00ff0040, hcd->regs + 0x0094);
	/* EHCI IP internal buffer enable */
	iowrite32(0x00000001, hcd->regs + 0x009C);

	return 0;
}

static struct usb_ehci_pdata ehcix_pdata = {
	.power_on	= usb_power_on,
	.power_off	= usb_power_off,
	.power_suspend	= usb_power_off,
	.pre_setup	= ehci_init_internal_buffer,
};

static struct resource ehci0_resources[] = {
	[0] = {
		.start	= 0xffe70000,
		.end	= 0xffe70400 - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= gic_iid(0x4c),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device ehci0_device = {
	.name	= "ehci-platform",
	.id	= 0,
	.dev	= {
		.dma_mask		= &ehci0_device.dev.coherent_dma_mask,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &ehcix_pdata,
	},
	.num_resources	= ARRAY_SIZE(ehci0_resources),
	.resource	= ehci0_resources,
};

static struct resource ehci1_resources[] = {
	[0] = {
		.start	= 0xfff70000,
		.end	= 0xfff70400 - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= gic_iid(0x4d),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device ehci1_device = {
	.name	= "ehci-platform",
	.id	= 1,
	.dev	= {
		.dma_mask		= &ehci1_device.dev.coherent_dma_mask,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &ehcix_pdata,
	},
	.num_resources	= ARRAY_SIZE(ehci1_resources),
	.resource	= ehci1_resources,
};

static struct usb_ohci_pdata ohcix_pdata = {
	.power_on	= usb_power_on,
	.power_off	= usb_power_off,
	.power_suspend	= usb_power_off,
};

static struct resource ohci0_resources[] = {
	[0] = {
		.start	= 0xffe70400,
		.end	= 0xffe70800 - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= gic_iid(0x4c),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device ohci0_device = {
	.name	= "ohci-platform",
	.id	= 0,
	.dev	= {
		.dma_mask		= &ohci0_device.dev.coherent_dma_mask,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &ohcix_pdata,
	},
	.num_resources	= ARRAY_SIZE(ohci0_resources),
	.resource	= ohci0_resources,
};

static struct resource ohci1_resources[] = {
	[0] = {
		.start	= 0xfff70400,
		.end	= 0xfff70800 - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= gic_iid(0x4d),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device ohci1_device = {
	.name	= "ohci-platform",
	.id	= 1,
	.dev	= {
		.dma_mask		= &ohci1_device.dev.coherent_dma_mask,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &ohcix_pdata,
	},
	.num_resources	= ARRAY_SIZE(ohci1_resources),
	.resource	= ohci1_resources,
};

/* Ether */
static struct resource ether_resources[] = {
	{
		.start	= 0xfde00000,
		.end	= 0xfde003ff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= gic_iid(0xb4),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device *r8a7779_devices_dt[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&scif4_device,
	&scif5_device,
	&tmu00_device,
	&tmu01_device,
	&usb_phy_device,
};

static struct platform_device *r8a7779_standard_devices[] __initdata = {
	&i2c0_device,
	&i2c1_device,
	&i2c2_device,
	&i2c3_device,
	&sata_device,
};

void __init r8a7779_add_standard_devices(void)
{
#ifdef CONFIG_CACHE_L2X0
	/* Early BRESP enable, Shared attribute override enable, 64K*16way */
	l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
#endif
	r8a7779_pm_init();

	r8a7779_init_pm_domains();

	platform_add_devices(r8a7779_devices_dt,
			    ARRAY_SIZE(r8a7779_devices_dt));
	platform_add_devices(r8a7779_standard_devices,
			    ARRAY_SIZE(r8a7779_standard_devices));
}

void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
{
	platform_device_register_resndata(&platform_bus, "sh_eth", -1,
					  ether_resources,
					  ARRAY_SIZE(ether_resources),
					  pdata, sizeof(*pdata));
}

/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
void __init __weak r8a7779_register_twd(void) { }

void __init r8a7779_earlytimer_init(void)
{
	r8a7779_clock_init();
	shmobile_earlytimer_init();
	r8a7779_register_twd();
}

void __init r8a7779_add_early_devices(void)
{
	early_platform_add_devices(r8a7779_devices_dt,
				   ARRAY_SIZE(r8a7779_devices_dt));

	/* Early serial console setup is not included here due to
	 * memory map collisions. The SCIF serial ports in r8a7779
	 * are difficult to entity map 1:1 due to collision with the
	 * virtual memory range used by the coherent DMA code on ARM.
	 *
	 * Anyone wanting to debug early can remove UPF_IOREMAP from
	 * the sh-sci serial console platform data, adjust mapbase
	 * to a static M:N virt:phys mapping that needs to be added to
	 * the mappings passed with iotable_init() above.
	 *
	 * Then add a call to shmobile_setup_console() from this function.
	 *
	 * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
	 * command line in case of the marzen board.
	 */
}

static struct platform_device *r8a7779_late_devices[] __initdata = {
	&ehci0_device,
	&ehci1_device,
	&ohci0_device,
	&ohci1_device,
};

void __init r8a7779_init_late(void)
{
	/* get USB PHY */
	phy = usb_get_phy(USB_PHY_TYPE_USB2);

	shmobile_init_late();
	platform_add_devices(r8a7779_late_devices,
			     ARRAY_SIZE(r8a7779_late_devices));
}

#ifdef CONFIG_USE_OF
void __init r8a7779_init_delay(void)
{
	shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
}

static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
	{},
};

void __init r8a7779_add_standard_devices_dt(void)
{
	/* clocks are setup late during boot in the case of DT */
	r8a7779_clock_init();

	platform_add_devices(r8a7779_devices_dt,
			     ARRAY_SIZE(r8a7779_devices_dt));
	of_platform_populate(NULL, of_default_bus_match_table,
			     r8a7779_auxdata_lookup, NULL);
}

static const char *r8a7779_compat_dt[] __initdata = {
	"renesas,r8a7779",
	NULL,
};

DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
	.map_io		= r8a7779_map_io,
	.init_early	= r8a7779_init_delay,
	.nr_irqs	= NR_IRQS_LEGACY,
	.init_irq	= r8a7779_init_irq_dt,
	.init_machine	= r8a7779_add_standard_devices_dt,
	.init_time	= shmobile_timer_init,
	.init_late	= r8a7779_init_late,
	.dt_compat	= r8a7779_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
Commit	Line	Data
f411fade MD	1	/*
	2	* r8a7779 processor support
	3	*
dace48d0	4	* Copyright (C) 2011, 2013 Renesas Solutions Corp.
f411fade	5	* Copyright (C) 2011 Magnus Damm
dace48d0	6	* Copyright (C) 2013 Cogent Embedded, Inc.
f411fade MD	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	*/
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/irq.h>
10e8d4f6	25	#include <linux/of_platform.h>
37a72d07	26	#include <linux/platform_data/gpio-rcar.h>
f411fade MD	27	#include <linux/platform_device.h>
	28	#include <linux/delay.h>
	29	#include <linux/input.h>
	30	#include <linux/io.h>
	31	#include <linux/serial_sci.h>
	32	#include <linux/sh_intc.h>
	33	#include <linux/sh_timer.h>
a7b9837c	34	#include <linux/dma-mapping.h>
2c8788bf	35	#include <linux/usb/otg.h>
84a812da	36	#include <linux/usb/hcd.h>
2c8788bf SS	37	#include <linux/usb/ehci_pdriver.h>
	38	#include <linux/usb/ohci_pdriver.h>
	39	#include <linux/pm_runtime.h>
f411fade	40	#include <mach/hardware.h>
250a2723	41	#include <mach/irqs.h>
f411fade	42	#include <mach/r8a7779.h>
a662c082	43	#include <mach/common.h>
f411fade MD	44	#include <asm/mach-types.h>
f411fade MD	45	#include <asm/mach/arch.h>
df27a2d8	46	#include <asm/mach/time.h>
3e353b87	47	#include <asm/mach/map.h>
8bac13f5	48	#include <asm/hardware/cache-l2x0.h>
3e353b87 MD	49
	50	static struct map_desc r8a7779_io_desc[] __initdata = {
	51	/* 2M entity map for 0xf0000000 (MPCORE) */
	52	{
	53	.virtual = 0xf0000000,
	54	.pfn = __phys_to_pfn(0xf0000000),
	55	.length = SZ_2M,
	56	.type = MT_DEVICE_NONSHARED
	57	},
	58	/* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
	59	{
	60	.virtual = 0xfe000000,
	61	.pfn = __phys_to_pfn(0xfe000000),
	62	.length = SZ_16M,
	63	.type = MT_DEVICE_NONSHARED
	64	},
	65	};
	66
	67	void __init r8a7779_map_io(void)
	68	{
	69	iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
	70	}
f411fade	71
8b6edf36	72	static struct resource r8a7779_pfc_resources[] = {
0ccaf5bb	73	DEFINE_RES_MEM(0xfffc0000, 0x023c),
8b6edf36 LP	74	};
	75
	76	static struct platform_device r8a7779_pfc_device = {
	77	.name = "pfc-r8a7779",
	78	.id = -1,
	79	.resource = r8a7779_pfc_resources,
	80	.num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
	81	};
	82
37a72d07 LP	83	#define R8A7779_GPIO(idx, npins) \
37a72d07 LP	84	static struct resource r8a7779_gpio##idx##_resources[] = { \
0ccaf5bb MD	85	DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \
0ccaf5bb MD	86	DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \
37a72d07 LP	87	}; \
	88	\
	89	static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
	90	.gpio_base = 32 * (idx), \
	91	.irq_base = 0, \
	92	.number_of_pins = npins, \
	93	.pctl_name = "pfc-r8a7779", \
	94	}; \
	95	\
	96	static struct platform_device r8a7779_gpio##idx##_device = { \
	97	.name = "gpio_rcar", \
	98	.id = idx, \
	99	.resource = r8a7779_gpio##idx##_resources, \
	100	.num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
	101	.dev = { \
	102	.platform_data = &r8a7779_gpio##idx##_platform_data, \
	103	}, \
	104	}
	105
	106	R8A7779_GPIO(0, 32);
	107	R8A7779_GPIO(1, 32);
	108	R8A7779_GPIO(2, 32);
	109	R8A7779_GPIO(3, 32);
	110	R8A7779_GPIO(4, 32);
	111	R8A7779_GPIO(5, 32);
	112	R8A7779_GPIO(6, 9);
	113
	114	static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
	115	&r8a7779_pfc_device,
	116	&r8a7779_gpio0_device,
	117	&r8a7779_gpio1_device,
	118	&r8a7779_gpio2_device,
	119	&r8a7779_gpio3_device,
	120	&r8a7779_gpio4_device,
	121	&r8a7779_gpio5_device,
	122	&r8a7779_gpio6_device,
	123	};
	124
8b6edf36 LP	125	void __init r8a7779_pinmux_init(void)
8b6edf36 LP	126	{
37a72d07 LP	127	platform_add_devices(r8a7779_pinctrl_devices,
37a72d07 LP	128	ARRAY_SIZE(r8a7779_pinctrl_devices));
8b6edf36 LP	129	}
8b6edf36 LP	130
f411fade MD	131	static struct plat_sci_port scif0_platform_data = {
	132	.mapbase = 0xffe40000,
	133	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP,
	134	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
	135	.scbrr_algo_id = SCBRR_ALGO_2,
	136	.type = PORT_SCIF,
dbe95ad0	137	.irqs = SCIx_IRQ_MUXED(gic_iid(0x78)),
f411fade MD	138	};
	139
	140	static struct platform_device scif0_device = {
	141	.name = "sh-sci",
	142	.id = 0,
	143	.dev = {
	144	.platform_data = &scif0_platform_data,
	145	},
	146	};
	147
	148	static struct plat_sci_port scif1_platform_data = {
	149	.mapbase = 0xffe41000,
	150	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP,
	151	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
	152	.scbrr_algo_id = SCBRR_ALGO_2,
	153	.type = PORT_SCIF,
dbe95ad0	154	.irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
f411fade MD	155	};
	156
	157	static struct platform_device scif1_device = {
	158	.name = "sh-sci",
	159	.id = 1,
	160	.dev = {
	161	.platform_data = &scif1_platform_data,
	162	},
	163	};
	164
	165	static struct plat_sci_port scif2_platform_data = {
	166	.mapbase = 0xffe42000,
	167	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP,
	168	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
	169	.scbrr_algo_id = SCBRR_ALGO_2,
	170	.type = PORT_SCIF,
dbe95ad0	171	.irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
f411fade MD	172	};
	173
	174	static struct platform_device scif2_device = {
	175	.name = "sh-sci",
	176	.id = 2,
	177	.dev = {
	178	.platform_data = &scif2_platform_data,
	179	},
	180	};
	181
	182	static struct plat_sci_port scif3_platform_data = {
	183	.mapbase = 0xffe43000,
	184	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP,
	185	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
	186	.scbrr_algo_id = SCBRR_ALGO_2,
	187	.type = PORT_SCIF,
dbe95ad0	188	.irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
f411fade MD	189	};
	190
	191	static struct platform_device scif3_device = {
	192	.name = "sh-sci",
	193	.id = 3,
	194	.dev = {
	195	.platform_data = &scif3_platform_data,
	196	},
	197	};
	198
	199	static struct plat_sci_port scif4_platform_data = {
	200	.mapbase = 0xffe44000,
	201	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP,
	202	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
	203	.scbrr_algo_id = SCBRR_ALGO_2,
	204	.type = PORT_SCIF,
dbe95ad0	205	.irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
f411fade MD	206	};
	207
	208	static struct platform_device scif4_device = {
	209	.name = "sh-sci",
	210	.id = 4,
	211	.dev = {
	212	.platform_data = &scif4_platform_data,
	213	},
	214	};
	215
	216	static struct plat_sci_port scif5_platform_data = {
	217	.mapbase = 0xffe45000,
	218	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP,
	219	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
	220	.scbrr_algo_id = SCBRR_ALGO_2,
	221	.type = PORT_SCIF,
dbe95ad0	222	.irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
f411fade MD	223	};
	224
	225	static struct platform_device scif5_device = {
	226	.name = "sh-sci",
	227	.id = 5,
	228	.dev = {
	229	.platform_data = &scif5_platform_data,
	230	},
	231	};
	232
	233	/* TMU */
	234	static struct sh_timer_config tmu00_platform_data = {
	235	.name = "TMU00",
	236	.channel_offset = 0x4,
	237	.timer_bit = 0,
	238	.clockevent_rating = 200,
	239	};
	240
	241	static struct resource tmu00_resources[] = {
	242	[0] = {
	243	.name = "TMU00",
	244	.start = 0xffd80008,
	245	.end = 0xffd80013,
	246	.flags = IORESOURCE_MEM,
	247	},
	248	[1] = {
dbe95ad0	249	.start = gic_iid(0x40),
f411fade MD	250	.flags = IORESOURCE_IRQ,
	251	},
	252	};
	253
	254	static struct platform_device tmu00_device = {
	255	.name = "sh_tmu",
	256	.id = 0,
	257	.dev = {
	258	.platform_data = &tmu00_platform_data,
	259	},
	260	.resource = tmu00_resources,
	261	.num_resources = ARRAY_SIZE(tmu00_resources),
	262	};
	263
	264	static struct sh_timer_config tmu01_platform_data = {
	265	.name = "TMU01",
	266	.channel_offset = 0x10,
	267	.timer_bit = 1,
	268	.clocksource_rating = 200,
	269	};
	270
	271	static struct resource tmu01_resources[] = {
	272	[0] = {
	273	.name = "TMU01",
	274	.start = 0xffd80014,
	275	.end = 0xffd8001f,
	276	.flags = IORESOURCE_MEM,
	277	},
	278	[1] = {
dbe95ad0	279	.start = gic_iid(0x41),
f411fade MD	280	.flags = IORESOURCE_IRQ,
	281	},
	282	};
	283
	284	static struct platform_device tmu01_device = {
	285	.name = "sh_tmu",
	286	.id = 1,
	287	.dev = {
	288	.platform_data = &tmu01_platform_data,
	289	},
	290	.resource = tmu01_resources,
	291	.num_resources = ARRAY_SIZE(tmu01_resources),
	292	};
	293
ccc2a27b KM	294	/* I2C */
	295	static struct resource rcar_i2c0_res[] = {
	296	{
	297	.start = 0xffc70000,
	298	.end = 0xffc70fff,
	299	.flags = IORESOURCE_MEM,
	300	}, {
dbe95ad0	301	.start = gic_iid(0x6f),
ccc2a27b KM	302	.flags = IORESOURCE_IRQ,
	303	},
	304	};
	305
	306	static struct platform_device i2c0_device = {
	307	.name = "i2c-rcar",
	308	.id = 0,
	309	.resource = rcar_i2c0_res,
	310	.num_resources = ARRAY_SIZE(rcar_i2c0_res),
	311	};
	312
	313	static struct resource rcar_i2c1_res[] = {
	314	{
	315	.start = 0xffc71000,
	316	.end = 0xffc71fff,
	317	.flags = IORESOURCE_MEM,
	318	}, {
dbe95ad0	319	.start = gic_iid(0x72),
ccc2a27b KM	320	.flags = IORESOURCE_IRQ,
	321	},
	322	};
	323
	324	static struct platform_device i2c1_device = {
	325	.name = "i2c-rcar",
	326	.id = 1,
	327	.resource = rcar_i2c1_res,
	328	.num_resources = ARRAY_SIZE(rcar_i2c1_res),
	329	};
	330
	331	static struct resource rcar_i2c2_res[] = {
	332	{
	333	.start = 0xffc72000,
	334	.end = 0xffc72fff,
	335	.flags = IORESOURCE_MEM,
	336	}, {
dbe95ad0	337	.start = gic_iid(0x70),
ccc2a27b KM	338	.flags = IORESOURCE_IRQ,
	339	},
	340	};
	341
	342	static struct platform_device i2c2_device = {
	343	.name = "i2c-rcar",
	344	.id = 2,
	345	.resource = rcar_i2c2_res,
	346	.num_resources = ARRAY_SIZE(rcar_i2c2_res),
	347	};
	348
	349	static struct resource rcar_i2c3_res[] = {
	350	{
	351	.start = 0xffc73000,
	352	.end = 0xffc73fff,
	353	.flags = IORESOURCE_MEM,
	354	}, {
dbe95ad0	355	.start = gic_iid(0x71),
ccc2a27b KM	356	.flags = IORESOURCE_IRQ,
	357	},
	358	};
	359
	360	static struct platform_device i2c3_device = {
	361	.name = "i2c-rcar",
	362	.id = 3,
	363	.resource = rcar_i2c3_res,
	364	.num_resources = ARRAY_SIZE(rcar_i2c3_res),
	365	};
	366
a7b9837c VB	367	static struct resource sata_resources[] = {
	368	[0] = {
	369	.name = "rcar-sata",
	370	.start = 0xfc600000,
	371	.end = 0xfc601fff,
	372	.flags = IORESOURCE_MEM,
	373	},
	374	[1] = {
d60cd5f1	375	.start = gic_iid(0x84),
a7b9837c VB	376	.flags = IORESOURCE_IRQ,
	377	},
	378	};
	379
	380	static struct platform_device sata_device = {
	381	.name = "sata_rcar",
	382	.id = -1,
	383	.resource = sata_resources,
	384	.num_resources = ARRAY_SIZE(sata_resources),
	385	.dev = {
	386	.dma_mask = &sata_device.dev.coherent_dma_mask,
	387	.coherent_dma_mask = DMA_BIT_MASK(32),
	388	},
	389	};
	390
2c8788bf SS	391	/* USB PHY */
	392	static struct resource usb_phy_resources[] = {
	393	[0] = {
	394	.start = 0xffe70000,
	395	.end = 0xffe70900 - 1,
	396	.flags = IORESOURCE_MEM,
	397	},
	398	[1] = {
	399	.start = 0xfff70000,
	400	.end = 0xfff70900 - 1,
	401	.flags = IORESOURCE_MEM,
	402	},
	403	};
	404
	405	static struct platform_device usb_phy_device = {
	406	.name = "rcar_usb_phy",
	407	.id = -1,
	408	.resource = usb_phy_resources,
	409	.num_resources = ARRAY_SIZE(usb_phy_resources),
	410	};
	411
	412	/* USB */
	413	static struct usb_phy *phy;
	414
	415	static int usb_power_on(struct platform_device *pdev)
	416	{
	417	if (IS_ERR(phy))
	418	return PTR_ERR(phy);
	419
	420	pm_runtime_enable(&pdev->dev);
	421	pm_runtime_get_sync(&pdev->dev);
	422
	423	usb_phy_init(phy);
	424
	425	return 0;
	426	}
	427
	428	static void usb_power_off(struct platform_device *pdev)
	429	{
	430	if (IS_ERR(phy))
	431	return;
	432
	433	usb_phy_shutdown(phy);
	434
	435	pm_runtime_put_sync(&pdev->dev);
	436	pm_runtime_disable(&pdev->dev);
	437	}
	438
84a812da SS	439	static int ehci_init_internal_buffer(struct usb_hcd *hcd)
	440	{
	441	/*
	442	* Below are recommended values from the datasheet;
	443	* see [USB :: Setting of EHCI Internal Buffer].
	444	*/
	445	/* EHCI IP internal buffer setting */
	446	iowrite32(0x00ff0040, hcd->regs + 0x0094);
	447	/* EHCI IP internal buffer enable */
	448	iowrite32(0x00000001, hcd->regs + 0x009C);
	449
	450	return 0;
	451	}
	452
2c8788bf SS	453	static struct usb_ehci_pdata ehcix_pdata = {
	454	.power_on = usb_power_on,
	455	.power_off = usb_power_off,
	456	.power_suspend = usb_power_off,
84a812da	457	.pre_setup = ehci_init_internal_buffer,
2c8788bf SS	458	};
	459
	460	static struct resource ehci0_resources[] = {
	461	[0] = {
	462	.start = 0xffe70000,
	463	.end = 0xffe70400 - 1,
	464	.flags = IORESOURCE_MEM,
	465	},
	466	[1] = {
	467	.start = gic_iid(0x4c),
	468	.flags = IORESOURCE_IRQ,
	469	},
	470	};
	471
	472	static struct platform_device ehci0_device = {
	473	.name = "ehci-platform",
	474	.id = 0,
	475	.dev = {
	476	.dma_mask = &ehci0_device.dev.coherent_dma_mask,
	477	.coherent_dma_mask = 0xffffffff,
	478	.platform_data = &ehcix_pdata,
	479	},
	480	.num_resources = ARRAY_SIZE(ehci0_resources),
	481	.resource = ehci0_resources,
	482	};
	483
	484	static struct resource ehci1_resources[] = {
	485	[0] = {
	486	.start = 0xfff70000,
	487	.end = 0xfff70400 - 1,
	488	.flags = IORESOURCE_MEM,
	489	},
	490	[1] = {
	491	.start = gic_iid(0x4d),
	492	.flags = IORESOURCE_IRQ,
	493	},
	494	};
	495
	496	static struct platform_device ehci1_device = {
	497	.name = "ehci-platform",
	498	.id = 1,
	499	.dev = {
	500	.dma_mask = &ehci1_device.dev.coherent_dma_mask,
	501	.coherent_dma_mask = 0xffffffff,
	502	.platform_data = &ehcix_pdata,
	503	},
	504	.num_resources = ARRAY_SIZE(ehci1_resources),
	505	.resource = ehci1_resources,
	506	};
	507
	508	static struct usb_ohci_pdata ohcix_pdata = {
	509	.power_on = usb_power_on,
	510	.power_off = usb_power_off,
	511	.power_suspend = usb_power_off,
	512	};
	513
	514	static struct resource ohci0_resources[] = {
	515	[0] = {
	516	.start = 0xffe70400,
	517	.end = 0xffe70800 - 1,
	518	.flags = IORESOURCE_MEM,
	519	},
	520	[1] = {
	521	.start = gic_iid(0x4c),
522	.flags = IORESOURCE_IRQ,
523	},
524	};
525
526	static struct platform_device ohci0_device = {
527	.name = "ohci-platform",
528	.id = 0,
529	.dev = {
530	.dma_mask = &ohci0_device.dev.coherent_dma_mask,
531	.coherent_dma_mask = 0xffffffff,
532	.platform_data = &ohcix_pdata,
533	},
534	.num_resources = ARRAY_SIZE(ohci0_resources),
535	.resource = ohci0_resources,
536	};
537
538	static struct resource ohci1_resources[] = {
539	[0] = {
540	.start = 0xfff70400,
541	.end = 0xfff70800 - 1,
542	.flags = IORESOURCE_MEM,
543	},
544	[1] = {
545	.start = gic_iid(0x4d),
546	.flags = IORESOURCE_IRQ,
547	},
548	};
549
550	static struct platform_device ohci1_device = {
551	.name = "ohci-platform",
552	.id = 1,
553	.dev = {
554	.dma_mask = &ohci1_device.dev.coherent_dma_mask,
555	.coherent_dma_mask = 0xffffffff,
556	.platform_data = &ohcix_pdata,
557	},
558	.num_resources = ARRAY_SIZE(ohci1_resources),
559	.resource = ohci1_resources,
560	};
561
dace48d0 SS	562	/* Ether */
	563	static struct resource ether_resources[] = {
	564	{
	565	.start = 0xfde00000,
	566	.end = 0xfde003ff,
	567	.flags = IORESOURCE_MEM,
	568	}, {
	569	.start = gic_iid(0xb4),
	570	.flags = IORESOURCE_IRQ,
	571	},
	572	};
	573
916ddc35	574	static struct platform_device *r8a7779_devices_dt[] __initdata = {
f411fade MD	575	&scif0_device,
	576	&scif1_device,
	577	&scif2_device,
	578	&scif3_device,
	579	&scif4_device,
	580	&scif5_device,
	581	&tmu00_device,
	582	&tmu01_device,
2c8788bf	583	&usb_phy_device,
10e8d4f6 SH	584	};
10e8d4f6 SH	585
2c8788bf	586	static struct platform_device *r8a7779_standard_devices[] __initdata = {
ccc2a27b KM	587	&i2c0_device,
	588	&i2c1_device,
	589	&i2c2_device,
	590	&i2c3_device,
a7b9837c	591	&sata_device,
f411fade MD	592	};
f411fade MD	593
f411fade MD	594	void __init r8a7779_add_standard_devices(void)
f411fade MD	595	{
8bac13f5 MD	596	#ifdef CONFIG_CACHE_L2X0
8bac13f5 MD	597	/* Early BRESP enable, Shared attribute override enable, 64K16way /
ed7d132a	598	l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
8bac13f5	599	#endif
a662c082 MD	600	r8a7779_pm_init();
a662c082 MD	601
45e5ca57	602	r8a7779_init_pm_domains();
a662c082	603
916ddc35 SH	604	platform_add_devices(r8a7779_devices_dt,
916ddc35 SH	605	ARRAY_SIZE(r8a7779_devices_dt));
2c8788bf SS	606	platform_add_devices(r8a7779_standard_devices,
2c8788bf SS	607	ARRAY_SIZE(r8a7779_standard_devices));
f411fade MD	608	}
f411fade MD	609
dace48d0 SS	610	void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
	611	{
	612	platform_device_register_resndata(&platform_bus, "sh_eth", -1,
	613	ether_resources,
	614	ARRAY_SIZE(ether_resources),
	615	pdata, sizeof(*pdata));
	616	}
	617
b759bd11 MD	618	/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
	619	void __init __weak r8a7779_register_twd(void) { }
	620
6bb27d73	621	void __init r8a7779_earlytimer_init(void)
df27a2d8 MD	622	{
	623	r8a7779_clock_init();
	624	shmobile_earlytimer_init();
b759bd11	625	r8a7779_register_twd();
df27a2d8 MD	626	}
df27a2d8 MD	627
f411fade MD	628	void __init r8a7779_add_early_devices(void)
f411fade MD	629	{
916ddc35 SH	630	early_platform_add_devices(r8a7779_devices_dt,
916ddc35 SH	631	ARRAY_SIZE(r8a7779_devices_dt));
3e353b87 MD	632
	633	/* Early serial console setup is not included here due to
	634	* memory map collisions. The SCIF serial ports in r8a7779
	635	* are difficult to entity map 1:1 due to collision with the
	636	* virtual memory range used by the coherent DMA code on ARM.
	637	*
	638	* Anyone wanting to debug early can remove UPF_IOREMAP from
	639	* the sh-sci serial console platform data, adjust mapbase
	640	* to a static M:N virt:phys mapping that needs to be added to
	641	* the mappings passed with iotable_init() above.
	642	*
	643	* Then add a call to shmobile_setup_console() from this function.
	644	*
	645	* As a final step pass earlyprint=sh-sci.2,115200 on the kernel
	646	* command line in case of the marzen board.
	647	*/
f411fade	648	}
10e8d4f6	649
2c8788bf SS	650	static struct platform_device *r8a7779_late_devices[] __initdata = {
	651	&ehci0_device,
	652	&ehci1_device,
	653	&ohci0_device,
	654	&ohci1_device,
	655	};
	656
	657	void __init r8a7779_init_late(void)
	658	{
	659	/* get USB PHY */
	660	phy = usb_get_phy(USB_PHY_TYPE_USB2);
	661
	662	shmobile_init_late();
	663	platform_add_devices(r8a7779_late_devices,
	664	ARRAY_SIZE(r8a7779_late_devices));
	665	}
	666
10e8d4f6	667	#ifdef CONFIG_USE_OF
916ddc35	668	void __init r8a7779_init_delay(void)
10e8d4f6 SH	669	{
10e8d4f6 SH	670	shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
10e8d4f6 SH	671	}
	672
	673	static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
	674	{},
	675	};
	676
	677	void __init r8a7779_add_standard_devices_dt(void)
	678	{
	679	/* clocks are setup late during boot in the case of DT */
	680	r8a7779_clock_init();
	681
916ddc35 SH	682	platform_add_devices(r8a7779_devices_dt,
916ddc35 SH	683	ARRAY_SIZE(r8a7779_devices_dt));
10e8d4f6 SH	684	of_platform_populate(NULL, of_default_bus_match_table,
	685	r8a7779_auxdata_lookup, NULL);
	686	}
	687
	688	static const char *r8a7779_compat_dt[] __initdata = {
	689	"renesas,r8a7779",
	690	NULL,
	691	};
	692
abe0e14b	693	DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
10e8d4f6	694	.map_io = r8a7779_map_io,
916ddc35	695	.init_early = r8a7779_init_delay,
10e8d4f6 SH	696	.nr_irqs = NR_IRQS_LEGACY,
	697	.init_irq = r8a7779_init_irq_dt,
	698	.init_machine = r8a7779_add_standard_devices_dt,
	699	.init_time = shmobile_timer_init,
2c8788bf	700	.init_late = r8a7779_init_late,
10e8d4f6 SH	701	.dt_compat = r8a7779_compat_dt,
	702	MACHINE_END
	703	#endif /* CONFIG_USE_OF */