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ARM: shmobile: r8a7779: Declare SCIF register base and IRQ as resources
[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7779.c
CommitLineData
f411fade
MD		 1/*
2 * r8a7779 processor support
3 *
dace48d0 4 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
f411fade 5 * Copyright (C) 2011 Magnus Damm
dace48d0 6 * Copyright (C) 2013 Cogent Embedded, Inc.
f411fade
MD		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
5b3859d7
KM		 25#include <linux/irqchip.h>
26#include <linux/irqchip/arm-gic.h>
10e8d4f6 27#include <linux/of_platform.h>
441f7502 28#include <linux/platform_data/dma-rcar-hpbdma.h>
37a72d07 29#include <linux/platform_data/gpio-rcar.h>
5b3859d7 30#include <linux/platform_data/irq-renesas-intc-irqpin.h>
f411fade
MD		 31#include <linux/platform_device.h>
32#include <linux/delay.h>
33#include <linux/input.h>
34#include <linux/io.h>
35#include <linux/serial_sci.h>
f411fade 36#include <linux/sh_timer.h>
a7b9837c 37#include <linux/dma-mapping.h>
2c8788bf 38#include <linux/usb/otg.h>
84a812da 39#include <linux/usb/hcd.h>
2c8788bf
SS		 40#include <linux/usb/ehci_pdriver.h>
41#include <linux/usb/ohci_pdriver.h>
42#include <linux/pm_runtime.h>
250a2723 43#include <mach/irqs.h>
f411fade 44#include <mach/r8a7779.h>
a662c082 45#include <mach/common.h>
f411fade
MD		 46#include <asm/mach-types.h>
47#include <asm/mach/arch.h>
df27a2d8 48#include <asm/mach/time.h>
3e353b87 49#include <asm/mach/map.h>
8bac13f5 50#include <asm/hardware/cache-l2x0.h>
3e353b87
MD		 51
52static struct map_desc r8a7779_io_desc[] __initdata = {
53 /* 2M entity map for 0xf0000000 (MPCORE) */
54 {
55 .virtual = 0xf0000000,
56 .pfn = __phys_to_pfn(0xf0000000),
57 .length = SZ_2M,
58 .type = MT_DEVICE_NONSHARED
59 },
60 /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
61 {
62 .virtual = 0xfe000000,
63 .pfn = __phys_to_pfn(0xfe000000),
64 .length = SZ_16M,
65 .type = MT_DEVICE_NONSHARED
66 },
67};
68
69void __init r8a7779_map_io(void)
70{
71 iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
72}
f411fade 73
5b3859d7
KM		 74/* IRQ */
75#define INT2SMSKCR0 IOMEM(0xfe7822a0)
76#define INT2SMSKCR1 IOMEM(0xfe7822a4)
77#define INT2SMSKCR2 IOMEM(0xfe7822a8)
78#define INT2SMSKCR3 IOMEM(0xfe7822ac)
79#define INT2SMSKCR4 IOMEM(0xfe7822b0)
80
81#define INT2NTSR0 IOMEM(0xfe700060)
82#define INT2NTSR1 IOMEM(0xfe700064)
83
84static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
85 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
86 .sense_bitfield_width = 2,
87};
88
89static struct resource irqpin0_resources[] __initdata = {
90 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
91 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
92 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
93 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
94 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
95 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
96 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
97 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
98 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
99};
100
31e4e292 101void __init r8a7779_init_irq_extpin_dt(int irlm)
5b3859d7
KM		 102{
103 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
104 u32 tmp;
105
106 if (!icr0) {
107 pr_warn("r8a7779: unable to setup external irq pin mode\n");
108 return;
109 }
110
111 tmp = ioread32(icr0);
112 if (irlm)
113 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
114 else
115 tmp &= ~(1 << 23); /* IRL mode - not supported */
116 tmp |= (1 << 21); /* LVLMODE = 1 */
117 iowrite32(tmp, icr0);
118 iounmap(icr0);
31e4e292 119}
5b3859d7 120
31e4e292
KM		 121void __init r8a7779_init_irq_extpin(int irlm)
122{
123 r8a7779_init_irq_extpin_dt(irlm);
5b3859d7
KM		 124 if (irlm)
125 platform_device_register_resndata(
126 &platform_bus, "renesas_intc_irqpin", -1,
127 irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
128 &irqpin0_platform_data, sizeof(irqpin0_platform_data));
129}
130
131/* PFC/GPIO */
8b6edf36 132static struct resource r8a7779_pfc_resources[] = {
0ccaf5bb 133 DEFINE_RES_MEM(0xfffc0000, 0x023c),
8b6edf36
LP		 134};
135
136static struct platform_device r8a7779_pfc_device = {
137 .name = "pfc-r8a7779",
138 .id = -1,
139 .resource = r8a7779_pfc_resources,
140 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
141};
142
37a72d07
LP		 143#define R8A7779_GPIO(idx, npins) \
144static struct resource r8a7779_gpio##idx##_resources[] = { \
0ccaf5bb
MD		 145 DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \
146 DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \
37a72d07
LP		 147}; \
148 \
149static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
150 .gpio_base = 32 * (idx), \
151 .irq_base = 0, \
152 .number_of_pins = npins, \
153 .pctl_name = "pfc-r8a7779", \
154}; \
155 \
156static struct platform_device r8a7779_gpio##idx##_device = { \
157 .name = "gpio_rcar", \
158 .id = idx, \
159 .resource = r8a7779_gpio##idx##_resources, \
160 .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
161 .dev = { \
162 .platform_data = &r8a7779_gpio##idx##_platform_data, \
163 }, \
164}
165
166R8A7779_GPIO(0, 32);
167R8A7779_GPIO(1, 32);
168R8A7779_GPIO(2, 32);
169R8A7779_GPIO(3, 32);
170R8A7779_GPIO(4, 32);
171R8A7779_GPIO(5, 32);
172R8A7779_GPIO(6, 9);
173
174static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
175 &r8a7779_pfc_device,
176 &r8a7779_gpio0_device,
177 &r8a7779_gpio1_device,
178 &r8a7779_gpio2_device,
179 &r8a7779_gpio3_device,
180 &r8a7779_gpio4_device,
181 &r8a7779_gpio5_device,
182 &r8a7779_gpio6_device,
183};
184
8b6edf36
LP		 185void __init r8a7779_pinmux_init(void)
186{
37a72d07
LP		 187 platform_add_devices(r8a7779_pinctrl_devices,
188 ARRAY_SIZE(r8a7779_pinctrl_devices));
8b6edf36
LP		 189}
190
efced000
LP		 191/* SCIF */
192#define R8A7779_SCIF(index, baseaddr, irq) \
193static struct plat_sci_port scif##index##_platform_data = { \
194 .type = PORT_SCIF, \
efced000 195 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
efced000
LP		 196 .scbrr_algo_id = SCBRR_ALGO_2, \
197 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
198}; \
199 \
aa61ee2e
LP		 200static struct resource scif##index##_resources[] = { \
201 DEFINE_RES_MEM(baseaddr, 0x100), \
202 DEFINE_RES_IRQ(irq), \
203}; \
204 \
efced000
LP		 205static struct platform_device scif##index##_device = { \
206 .name = "sh-sci", \
207 .id = index, \
aa61ee2e
LP		 208 .resource = scif##index##_resources, \
209 .num_resources = ARRAY_SIZE(scif##index##_resources), \
efced000
LP		 210 .dev = { \
211 .platform_data = &scif##index##_platform_data, \
212 }, \
213}
f411fade 214
efced000
LP		 215R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
216R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
217R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
218R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
219R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
220R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
f411fade
MD		 221
222/* TMU */
223static struct sh_timer_config tmu00_platform_data = {
224 .name = "TMU00",
225 .channel_offset = 0x4,
226 .timer_bit = 0,
227 .clockevent_rating = 200,
228};
229
230static struct resource tmu00_resources[] = {
231 [0] = {
232 .name = "TMU00",
233 .start = 0xffd80008,
234 .end = 0xffd80013,
235 .flags = IORESOURCE_MEM,
236 },
237 [1] = {
dbe95ad0 238 .start = gic_iid(0x40),
f411fade
MD		 239 .flags = IORESOURCE_IRQ,
240 },
241};
242
243static struct platform_device tmu00_device = {
244 .name = "sh_tmu",
245 .id = 0,
246 .dev = {
247 .platform_data = &tmu00_platform_data,
248 },
249 .resource = tmu00_resources,
250 .num_resources = ARRAY_SIZE(tmu00_resources),
251};
252
253static struct sh_timer_config tmu01_platform_data = {
254 .name = "TMU01",
255 .channel_offset = 0x10,
256 .timer_bit = 1,
257 .clocksource_rating = 200,
258};
259
260static struct resource tmu01_resources[] = {
261 [0] = {
262 .name = "TMU01",
263 .start = 0xffd80014,
264 .end = 0xffd8001f,
265 .flags = IORESOURCE_MEM,
266 },
267 [1] = {
dbe95ad0 268 .start = gic_iid(0x41),
f411fade
MD		 269 .flags = IORESOURCE_IRQ,
270 },
271};
272
273static struct platform_device tmu01_device = {
274 .name = "sh_tmu",
275 .id = 1,
276 .dev = {
277 .platform_data = &tmu01_platform_data,
278 },
279 .resource = tmu01_resources,
280 .num_resources = ARRAY_SIZE(tmu01_resources),
281};
282
ccc2a27b
KM		 283/* I2C */
284static struct resource rcar_i2c0_res[] = {
285 {
286 .start = 0xffc70000,
287 .end = 0xffc70fff,
288 .flags = IORESOURCE_MEM,
289 }, {
dbe95ad0 290 .start = gic_iid(0x6f),
ccc2a27b
KM		 291 .flags = IORESOURCE_IRQ,
292 },
293};
294
295static struct platform_device i2c0_device = {
296 .name = "i2c-rcar",
297 .id = 0,
298 .resource = rcar_i2c0_res,
299 .num_resources = ARRAY_SIZE(rcar_i2c0_res),
300};
301
302static struct resource rcar_i2c1_res[] = {
303 {
304 .start = 0xffc71000,
305 .end = 0xffc71fff,
306 .flags = IORESOURCE_MEM,
307 }, {
dbe95ad0 308 .start = gic_iid(0x72),
ccc2a27b
KM		 309 .flags = IORESOURCE_IRQ,
310 },
311};
312
313static struct platform_device i2c1_device = {
314 .name = "i2c-rcar",
315 .id = 1,
316 .resource = rcar_i2c1_res,
317 .num_resources = ARRAY_SIZE(rcar_i2c1_res),
318};
319
320static struct resource rcar_i2c2_res[] = {
321 {
322 .start = 0xffc72000,
323 .end = 0xffc72fff,
324 .flags = IORESOURCE_MEM,
325 }, {
dbe95ad0 326 .start = gic_iid(0x70),
ccc2a27b
KM		 327 .flags = IORESOURCE_IRQ,
328 },
329};
330
331static struct platform_device i2c2_device = {
332 .name = "i2c-rcar",
333 .id = 2,
334 .resource = rcar_i2c2_res,
335 .num_resources = ARRAY_SIZE(rcar_i2c2_res),
336};
337
338static struct resource rcar_i2c3_res[] = {
339 {
340 .start = 0xffc73000,
341 .end = 0xffc73fff,
342 .flags = IORESOURCE_MEM,
343 }, {
dbe95ad0 344 .start = gic_iid(0x71),
ccc2a27b
KM		 345 .flags = IORESOURCE_IRQ,
346 },
347};
348
349static struct platform_device i2c3_device = {
350 .name = "i2c-rcar",
351 .id = 3,
352 .resource = rcar_i2c3_res,
353 .num_resources = ARRAY_SIZE(rcar_i2c3_res),
354};
355
a7b9837c
VB		 356static struct resource sata_resources[] = {
357 [0] = {
358 .name = "rcar-sata",
359 .start = 0xfc600000,
360 .end = 0xfc601fff,
361 .flags = IORESOURCE_MEM,
362 },
363 [1] = {
d60cd5f1 364 .start = gic_iid(0x84),
a7b9837c
VB		 365 .flags = IORESOURCE_IRQ,
366 },
367};
368
369static struct platform_device sata_device = {
370 .name = "sata_rcar",
371 .id = -1,
372 .resource = sata_resources,
373 .num_resources = ARRAY_SIZE(sata_resources),
374 .dev = {
375 .dma_mask = &sata_device.dev.coherent_dma_mask,
376 .coherent_dma_mask = DMA_BIT_MASK(32),
377 },
378};
379
2c8788bf
SS		 380/* USB */
381static struct usb_phy *phy;
382
383static int usb_power_on(struct platform_device *pdev)
384{
385 if (IS_ERR(phy))
386 return PTR_ERR(phy);
387
388 pm_runtime_enable(&pdev->dev);
389 pm_runtime_get_sync(&pdev->dev);
390
391 usb_phy_init(phy);
392
393 return 0;
394}
395
396static void usb_power_off(struct platform_device *pdev)
397{
398 if (IS_ERR(phy))
399 return;
400
401 usb_phy_shutdown(phy);
402
403 pm_runtime_put_sync(&pdev->dev);
404 pm_runtime_disable(&pdev->dev);
405}
406
84a812da
SS		 407static int ehci_init_internal_buffer(struct usb_hcd *hcd)
408{
409 /*
410 * Below are recommended values from the datasheet;
411 * see [USB :: Setting of EHCI Internal Buffer].
412 */
413 /* EHCI IP internal buffer setting */
414 iowrite32(0x00ff0040, hcd->regs + 0x0094);
415 /* EHCI IP internal buffer enable */
416 iowrite32(0x00000001, hcd->regs + 0x009C);
417
418 return 0;
419}
420
2c8788bf
SS		 421static struct usb_ehci_pdata ehcix_pdata = {
422 .power_on = usb_power_on,
423 .power_off = usb_power_off,
424 .power_suspend = usb_power_off,
84a812da 425 .pre_setup = ehci_init_internal_buffer,
2c8788bf
SS		 426};
427
428static struct resource ehci0_resources[] = {
429 [0] = {
430 .start = 0xffe70000,
431 .end = 0xffe70400 - 1,
432 .flags = IORESOURCE_MEM,
433 },
434 [1] = {
435 .start = gic_iid(0x4c),
436 .flags = IORESOURCE_IRQ,
437 },
438};
439
440static struct platform_device ehci0_device = {
441 .name = "ehci-platform",
442 .id = 0,
443 .dev = {
444 .dma_mask = &ehci0_device.dev.coherent_dma_mask,
445 .coherent_dma_mask = 0xffffffff,
446 .platform_data = &ehcix_pdata,
447 },
448 .num_resources = ARRAY_SIZE(ehci0_resources),
449 .resource = ehci0_resources,
450};
451
452static struct resource ehci1_resources[] = {
453 [0] = {
454 .start = 0xfff70000,
455 .end = 0xfff70400 - 1,
456 .flags = IORESOURCE_MEM,
457 },
458 [1] = {
459 .start = gic_iid(0x4d),
460 .flags = IORESOURCE_IRQ,
461 },
462};
463
464static struct platform_device ehci1_device = {
465 .name = "ehci-platform",
466 .id = 1,
467 .dev = {
468 .dma_mask = &ehci1_device.dev.coherent_dma_mask,
469 .coherent_dma_mask = 0xffffffff,
470 .platform_data = &ehcix_pdata,
471 },
472 .num_resources = ARRAY_SIZE(ehci1_resources),
473 .resource = ehci1_resources,
474};
475
476static struct usb_ohci_pdata ohcix_pdata = {
477 .power_on = usb_power_on,
478 .power_off = usb_power_off,
479 .power_suspend = usb_power_off,
480};
481
482static struct resource ohci0_resources[] = {
483 [0] = {
484 .start = 0xffe70400,
485 .end = 0xffe70800 - 1,
486 .flags = IORESOURCE_MEM,
487 },
488 [1] = {
489 .start = gic_iid(0x4c),
490 .flags = IORESOURCE_IRQ,
491 },
492};
493
494static struct platform_device ohci0_device = {
495 .name = "ohci-platform",
496 .id = 0,
497 .dev = {
498 .dma_mask = &ohci0_device.dev.coherent_dma_mask,
499 .coherent_dma_mask = 0xffffffff,
500 .platform_data = &ohcix_pdata,
501 },
502 .num_resources = ARRAY_SIZE(ohci0_resources),
503 .resource = ohci0_resources,
504};
505
506static struct resource ohci1_resources[] = {
507 [0] = {
508 .start = 0xfff70400,
509 .end = 0xfff70800 - 1,
510 .flags = IORESOURCE_MEM,
511 },
512 [1] = {
513 .start = gic_iid(0x4d),
514 .flags = IORESOURCE_IRQ,
515 },
516};
517
518static struct platform_device ohci1_device = {
519 .name = "ohci-platform",
520 .id = 1,
521 .dev = {
522 .dma_mask = &ohci1_device.dev.coherent_dma_mask,
523 .coherent_dma_mask = 0xffffffff,
524 .platform_data = &ohcix_pdata,
525 },
526 .num_resources = ARRAY_SIZE(ohci1_resources),
527 .resource = ohci1_resources,
528};
529
dace48d0 530/* Ether */
c7537655 531static struct resource ether_resources[] __initdata = {
dace48d0
SS		 532 {
533 .start = 0xfde00000,
534 .end = 0xfde003ff,
535 .flags = IORESOURCE_MEM,
536 }, {
537 .start = gic_iid(0xb4),
538 .flags = IORESOURCE_IRQ,
539 },
540};
541
4714a025
VB		 542#define R8A7779_VIN(idx) \
543static struct resource vin##idx##_resources[] __initdata = { \
544 DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \
545 DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \
546}; \
547 \
548static struct platform_device_info vin##idx##_info __initdata = { \
549 .parent = &platform_bus, \
550 .name = "r8a7779-vin", \
551 .id = idx, \
552 .res = vin##idx##_resources, \
553 .num_res = ARRAY_SIZE(vin##idx##_resources), \
554 .dma_mask = DMA_BIT_MASK(32), \
555}
556
557R8A7779_VIN(0);
558R8A7779_VIN(1);
559R8A7779_VIN(2);
560R8A7779_VIN(3);
561
562static struct platform_device_info *vin_info_table[] __initdata = {
563 &vin0_info,
564 &vin1_info,
565 &vin2_info,
566 &vin3_info,
567};
568
441f7502
MF		 569/* HPB-DMA */
570
571/* Asynchronous mode register bits */
572#define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */
573#define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */
574#define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */
575#define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */
576#define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */
577#define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */
578#define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */
579#define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */
580#define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */
581#define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */
582#define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */
583#define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */
584#define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */
585#define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */
586#define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */
587#define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */
588#define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */
589#define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */
590#define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */
591#define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */
592#define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */
593#define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */
594#define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */
595#define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */
596#define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */
597#define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */
598#define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */
599#define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */
600#define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */
601#define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */
602#define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */
603#define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */
604#define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */
605#define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */
606#define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */
607#define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */
608#define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */
609#define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */
610#define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */
611#define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */
612#define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */
613#define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */
614#define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */
615#define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */
616#define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */
617#define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */
618#define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */
619#define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */
620#define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */
621#define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */
622#define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */
623#define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */
624#define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */
625#define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */
626#define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */
627#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */
628#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
629#define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */
630#define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */
631#define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */
632#define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */
633#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */
634#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
635#define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */
636#define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */
637#define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */
638#define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */
639#define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */
640#define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */
641#define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */
642#define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */
643#define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */
644
645static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
646 {
647 .id = HPBDMA_SLAVE_SDHI0_TX,
648 .addr = 0xffe4c000 + 0x30,
649 .dcr = HPB_DMAE_DCR_SPDS_16BIT |
650 HPB_DMAE_DCR_DMDL |
651 HPB_DMAE_DCR_DPDS_16BIT,
652 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
653 HPB_DMAE_ASYNCRSTR_ASRST22 |
654 HPB_DMAE_ASYNCRSTR_ASRST23,
655 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
656 HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
657 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
658 HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
659 .port = 0x0D0C,
660 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
661 .dma_ch = 21,
662 }, {
663 .id = HPBDMA_SLAVE_SDHI0_RX,
664 .addr = 0xffe4c000 + 0x30,
665 .dcr = HPB_DMAE_DCR_SMDL |
666 HPB_DMAE_DCR_SPDS_16BIT |
667 HPB_DMAE_DCR_DPDS_16BIT,
668 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
669 HPB_DMAE_ASYNCRSTR_ASRST22 |
670 HPB_DMAE_ASYNCRSTR_ASRST23,
671 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
672 HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
673 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
674 HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
675 .port = 0x0D0C,
676 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
677 .dma_ch = 22,
678 },
679};
680
681static const struct hpb_dmae_channel hpb_dmae_channels[] = {
682 HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
683 HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
684};
685
686static struct hpb_dmae_pdata dma_platform_data __initdata = {
687 .slaves = hpb_dmae_slaves,
688 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
689 .channels = hpb_dmae_channels,
690 .num_channels = ARRAY_SIZE(hpb_dmae_channels),
691 .ts_shift = {
692 [XMIT_SZ_8BIT] = 0,
693 [XMIT_SZ_16BIT] = 1,
694 [XMIT_SZ_32BIT] = 2,
695 },
696 .num_hw_channels = 44,
697};
698
699static struct resource hpb_dmae_resources[] __initdata = {
700 /* Channel registers */
701 DEFINE_RES_MEM(0xffc08000, 0x1000),
702 /* Common registers */
703 DEFINE_RES_MEM(0xffc09000, 0x170),
704 /* Asynchronous reset registers */
705 DEFINE_RES_MEM(0xffc00300, 4),
706 /* Asynchronous mode registers */
707 DEFINE_RES_MEM(0xffc00400, 4),
708 /* IRQ for DMA channels */
709 DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
710};
711
712static void __init r8a7779_register_hpb_dmae(void)
713{
714 platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
715 hpb_dmae_resources,
716 ARRAY_SIZE(hpb_dmae_resources),
717 &dma_platform_data,
718 sizeof(dma_platform_data));
719}
720
916ddc35 721static struct platform_device *r8a7779_devices_dt[] __initdata = {
f411fade
MD		 722 &scif0_device,
723 &scif1_device,
724 &scif2_device,
725 &scif3_device,
726 &scif4_device,
727 &scif5_device,
728 &tmu00_device,
729 &tmu01_device,
10e8d4f6
SH		 730};
731
2c8788bf 732static struct platform_device *r8a7779_standard_devices[] __initdata = {
ccc2a27b
KM		 733 &i2c0_device,
734 &i2c1_device,
735 &i2c2_device,
736 &i2c3_device,
a7b9837c 737 &sata_device,
f411fade
MD		 738};
739
f411fade
MD		 740void __init r8a7779_add_standard_devices(void)
741{
8bac13f5
MD		 742#ifdef CONFIG_CACHE_L2X0
743 /* Early BRESP enable, Shared attribute override enable, 64K*16way */
ed7d132a 744 l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
8bac13f5 745#endif
a662c082
MD		 746 r8a7779_pm_init();
747
45e5ca57 748 r8a7779_init_pm_domains();
a662c082 749
916ddc35
SH		 750 platform_add_devices(r8a7779_devices_dt,
751 ARRAY_SIZE(r8a7779_devices_dt));
2c8788bf
SS		 752 platform_add_devices(r8a7779_standard_devices,
753 ARRAY_SIZE(r8a7779_standard_devices));
441f7502 754 r8a7779_register_hpb_dmae();
f411fade
MD		 755}
756
dace48d0
SS		 757void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
758{
4c370abb 759 platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
dace48d0
SS		 760 ether_resources,
761 ARRAY_SIZE(ether_resources),
762 pdata, sizeof(*pdata));
763}
764
4714a025
VB		 765void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata)
766{
767 BUG_ON(id < 0 || id > 3);
768
769 vin_info_table[id]->data = pdata;
770 vin_info_table[id]->size_data = sizeof(*pdata);
771
772 platform_device_register_full(vin_info_table[id]);
773}
774
b759bd11
MD		 775/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
776void __init __weak r8a7779_register_twd(void) { }
777
6bb27d73 778void __init r8a7779_earlytimer_init(void)
df27a2d8
MD		 779{
780 r8a7779_clock_init();
b759bd11 781 r8a7779_register_twd();
7658ea2f 782 shmobile_earlytimer_init();
df27a2d8
MD		 783}
784
f411fade
MD		 785void __init r8a7779_add_early_devices(void)
786{
916ddc35
SH		 787 early_platform_add_devices(r8a7779_devices_dt,
788 ARRAY_SIZE(r8a7779_devices_dt));
3e353b87
MD		 789
790 /* Early serial console setup is not included here due to
791 * memory map collisions. The SCIF serial ports in r8a7779
792 * are difficult to entity map 1:1 due to collision with the
793 * virtual memory range used by the coherent DMA code on ARM.
794 *
795 * Anyone wanting to debug early can remove UPF_IOREMAP from
796 * the sh-sci serial console platform data, adjust mapbase
797 * to a static M:N virt:phys mapping that needs to be added to
798 * the mappings passed with iotable_init() above.
799 *
800 * Then add a call to shmobile_setup_console() from this function.
801 *
802 * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
803 * command line in case of the marzen board.
804 */
f411fade 805}
10e8d4f6 806
2c8788bf
SS		 807static struct platform_device *r8a7779_late_devices[] __initdata = {
808 &ehci0_device,
809 &ehci1_device,
810 &ohci0_device,
811 &ohci1_device,
812};
813
814void __init r8a7779_init_late(void)
815{
816 /* get USB PHY */
817 phy = usb_get_phy(USB_PHY_TYPE_USB2);
818
819 shmobile_init_late();
820 platform_add_devices(r8a7779_late_devices,
821 ARRAY_SIZE(r8a7779_late_devices));
822}
823
10e8d4f6 824#ifdef CONFIG_USE_OF
5b3859d7
KM		 825static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
826{
827 return 0; /* always allow wakeup */
828}
829
830void __init r8a7779_init_irq_dt(void)
831{
832 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
833
834 irqchip_init();
835
836 /* route all interrupts to ARM */
837 __raw_writel(0xffffffff, INT2NTSR0);
838 __raw_writel(0x3fffffff, INT2NTSR1);
839
840 /* unmask all known interrupts in INTCS2 */
841 __raw_writel(0xfffffff0, INT2SMSKCR0);
842 __raw_writel(0xfff7ffff, INT2SMSKCR1);
843 __raw_writel(0xfffbffdf, INT2SMSKCR2);
844 __raw_writel(0xbffffffc, INT2SMSKCR3);
845 __raw_writel(0x003fee3f, INT2SMSKCR4);
846}
847
916ddc35 848void __init r8a7779_init_delay(void)
10e8d4f6
SH		 849{
850 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
10e8d4f6
SH		 851}
852
10e8d4f6
SH		 853void __init r8a7779_add_standard_devices_dt(void)
854{
855 /* clocks are setup late during boot in the case of DT */
856 r8a7779_clock_init();
857
916ddc35
SH		 858 platform_add_devices(r8a7779_devices_dt,
859 ARRAY_SIZE(r8a7779_devices_dt));
41b0156c 860 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
10e8d4f6
SH		 861}
862
863static const char *r8a7779_compat_dt[] __initdata = {
864 "renesas,r8a7779",
865 NULL,
866};
867
abe0e14b 868DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
10e8d4f6 869 .map_io = r8a7779_map_io,
916ddc35 870 .init_early = r8a7779_init_delay,
10e8d4f6
SH		 871 .nr_irqs = NR_IRQS_LEGACY,
872 .init_irq = r8a7779_init_irq_dt,
873 .init_machine = r8a7779_add_standard_devices_dt,
2c8788bf 874 .init_late = r8a7779_init_late,
10e8d4f6
SH		 875 .dt_compat = r8a7779_compat_dt,
876MACHINE_END
877#endif /* CONFIG_USE_OF */
Linux kernel - Deliverables
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