[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7790.c

/*
 * r8a7790 processor support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/serial_sci.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r8a7790.h>
#include <asm/mach/arch.h>

static struct resource pfc_resources[] __initdata = {
	DEFINE_RES_MEM(0xe6060000, 0x250),
};

#define R8A7790_GPIO(idx)						\
static struct resource r8a7790_gpio##idx##_resources[] __initdata = {	\
	DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),		\
	DEFINE_RES_IRQ(gic_spi(4 + (idx))),				\
};									\
									\
static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = {	\
	.gpio_base	= 32 * (idx),					\
	.irq_base	= 0,						\
	.number_of_pins	= 32,						\
	.pctl_name	= "pfc-r8a7790",				\
	.has_both_edge_trigger = 1,					\
};									\

R8A7790_GPIO(0);
R8A7790_GPIO(1);
R8A7790_GPIO(2);
R8A7790_GPIO(3);
R8A7790_GPIO(4);
R8A7790_GPIO(5);

#define r8a7790_register_gpio(idx)					\
	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
		r8a7790_gpio##idx##_resources,				\
		ARRAY_SIZE(r8a7790_gpio##idx##_resources),		\
		&r8a7790_gpio##idx##_platform_data,			\
		sizeof(r8a7790_gpio##idx##_platform_data))

void __init r8a7790_pinmux_init(void)
{
	platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
					ARRAY_SIZE(pfc_resources));
	r8a7790_register_gpio(0);
	r8a7790_register_gpio(1);
	r8a7790_register_gpio(2);
	r8a7790_register_gpio(3);
	r8a7790_register_gpio(4);
	r8a7790_register_gpio(5);
}

#define SCIF_COMMON(scif_type, baseaddr, irq)			\
	.type		= scif_type,				\
	.mapbase	= baseaddr,				\
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,	\
	.irqs		= SCIx_IRQ_MUXED(irq)

#define SCIFA_DATA(index, baseaddr, irq)		\
[index] = {						\
	SCIF_COMMON(PORT_SCIFA, baseaddr, irq),		\
	.scbrr_algo_id	= SCBRR_ALGO_4,			\
	.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0,	\
}

#define SCIFB_DATA(index, baseaddr, irq)	\
[index] = {					\
	SCIF_COMMON(PORT_SCIFB, baseaddr, irq),	\
	.scbrr_algo_id	= SCBRR_ALGO_4,		\
	.scscr = SCSCR_RE | SCSCR_TE,		\
}

#define SCIF_DATA(index, baseaddr, irq)		\
[index] = {						\
	SCIF_COMMON(PORT_SCIF, baseaddr, irq),		\
	.scbrr_algo_id	= SCBRR_ALGO_2,			\
	.scscr = SCSCR_RE | SCSCR_TE,	\
}

#define HSCIF_DATA(index, baseaddr, irq)		\
[index] = {						\
	SCIF_COMMON(PORT_HSCIF, baseaddr, irq),		\
	.scbrr_algo_id	= SCBRR_ALGO_6,			\
	.scscr = SCSCR_RE | SCSCR_TE,	\
}

enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
       HSCIF0, HSCIF1 };

static struct plat_sci_port scif[] __initdata = {
	SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
	SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
	SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
	SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
	SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
	SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
	SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
	SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
	HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
	HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
};

static inline void r8a7790_register_scif(int idx)
{
	platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
				      sizeof(struct plat_sci_port));
}

static struct renesas_irqc_config irqc0_data __initdata = {
	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
};

static struct resource irqc0_resources[] __initdata = {
	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
};

#define r8a7790_register_irqc(idx)					\
	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
					  idx, irqc##idx##_resources,	\
					  ARRAY_SIZE(irqc##idx##_resources), \
					  &irqc##idx##_data,		\
					  sizeof(struct renesas_irqc_config))

void __init r8a7790_add_standard_devices(void)
{
	r8a7790_register_scif(SCIFA0);
	r8a7790_register_scif(SCIFA1);
	r8a7790_register_scif(SCIFB0);
	r8a7790_register_scif(SCIFB1);
	r8a7790_register_scif(SCIFB2);
	r8a7790_register_scif(SCIFA2);
	r8a7790_register_scif(SCIF0);
	r8a7790_register_scif(SCIF1);
	r8a7790_register_scif(HSCIF0);
	r8a7790_register_scif(HSCIF1);
	r8a7790_register_irqc(0);
}

void __init r8a7790_timer_init(void)
{
	void __iomem *cntcr;

	/* make sure arch timer is started by setting bit 0 of CNTCT */
	cntcr = ioremap(0xe6080000, PAGE_SIZE);
	iowrite32(1, cntcr);
	iounmap(cntcr);

	shmobile_timer_init();
}

#ifdef CONFIG_USE_OF
void __init r8a7790_add_standard_devices_dt(void)
{
	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

static const char *r8a7790_boards_compat_dt[] __initdata = {
	"renesas,r8a7790",
	NULL,
};

DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
	.init_irq	= irqchip_init,
	.init_machine	= r8a7790_add_standard_devices_dt,
	.init_time	= r8a7790_timer_init,
	.dt_compat	= r8a7790_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
Commit	Line	Data
0468b2d6 MD	1	/*
	2	* r8a7790 processor support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Magnus Damm
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20
	21	#include <linux/irq.h>
	22	#include <linux/irqchip.h>
	23	#include <linux/kernel.h>
	24	#include <linux/of_platform.h>
55d9fab2	25	#include <linux/serial_sci.h>
43ca9cbb	26	#include <linux/platform_data/gpio-rcar.h>
8f5ec0a5	27	#include <linux/platform_data/irq-renesas-irqc.h>
0468b2d6 MD	28	#include <mach/common.h>
	29	#include <mach/irqs.h>
	30	#include <mach/r8a7790.h>
	31	#include <asm/mach/arch.h>
	32
f9094c52	33	static struct resource pfc_resources[] __initdata = {
69e351d0 MD	34	DEFINE_RES_MEM(0xe6060000, 0x250),
	35	};
	36
43ca9cbb	37	#define R8A7790_GPIO(idx) \
f9094c52	38	static struct resource r8a7790_gpio##idx##_resources[] __initdata = { \
43ca9cbb LP	39	DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
	40	DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
	41	}; \
	42	\
f9094c52	43	static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \
43ca9cbb LP	44	.gpio_base = 32 * (idx), \
	45	.irq_base = 0, \
	46	.number_of_pins = 32, \
	47	.pctl_name = "pfc-r8a7790", \
d93906b8	48	.has_both_edge_trigger = 1, \
43ca9cbb LP	49	}; \
	50
	51	R8A7790_GPIO(0);
	52	R8A7790_GPIO(1);
	53	R8A7790_GPIO(2);
	54	R8A7790_GPIO(3);
	55	R8A7790_GPIO(4);
	56	R8A7790_GPIO(5);
	57
	58	#define r8a7790_register_gpio(idx) \
	59	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
	60	r8a7790_gpio##idx##_resources, \
	61	ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
	62	&r8a7790_gpio##idx##_platform_data, \
	63	sizeof(r8a7790_gpio##idx##_platform_data))
	64
69e351d0 MD	65	void __init r8a7790_pinmux_init(void)
	66	{
	67	platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
	68	ARRAY_SIZE(pfc_resources));
43ca9cbb LP	69	r8a7790_register_gpio(0);
	70	r8a7790_register_gpio(1);
	71	r8a7790_register_gpio(2);
	72	r8a7790_register_gpio(3);
	73	r8a7790_register_gpio(4);
	74	r8a7790_register_gpio(5);
69e351d0 MD	75	}
69e351d0 MD	76
55d9fab2 MD	77	#define SCIF_COMMON(scif_type, baseaddr, irq) \
	78	.type = scif_type, \
	79	.mapbase = baseaddr, \
	80	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP, \
	81	.irqs = SCIx_IRQ_MUXED(irq)
	82
	83	#define SCIFA_DATA(index, baseaddr, irq) \
	84	[index] = { \
	85	SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
	86	.scbrr_algo_id = SCBRR_ALGO_4, \
	87	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE0, \
	88	}
	89
	90	#define SCIFB_DATA(index, baseaddr, irq) \
	91	[index] = { \
	92	SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
	93	.scbrr_algo_id = SCBRR_ALGO_4, \
	94	.scscr = SCSCR_RE \| SCSCR_TE, \
	95	}
	96
	97	#define SCIF_DATA(index, baseaddr, irq) \
	98	[index] = { \
	99	SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
	100	.scbrr_algo_id = SCBRR_ALGO_2, \
c972f024	101	.scscr = SCSCR_RE \| SCSCR_TE, \
55d9fab2 MD	102	}
55d9fab2 MD	103
d44f8308 UH	104	#define HSCIF_DATA(index, baseaddr, irq) \
	105	[index] = { \
	106	SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
	107	.scbrr_algo_id = SCBRR_ALGO_6, \
	108	.scscr = SCSCR_RE \| SCSCR_TE, \
	109	}
	110
	111	enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
	112	HSCIF0, HSCIF1 };
55d9fab2	113
f9094c52	114	static struct plat_sci_port scif[] __initdata = {
55d9fab2 MD	115	SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
	116	SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
	117	SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
	118	SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
	119	SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
	120	SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
	121	SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
	122	SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
d44f8308 UH	123	HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
d44f8308 UH	124	HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
55d9fab2 MD	125	};
	126
	127	static inline void r8a7790_register_scif(int idx)
	128	{
	129	platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
	130	sizeof(struct plat_sci_port));
	131	}
	132
f9094c52	133	static struct renesas_irqc_config irqc0_data __initdata = {
8f5ec0a5 MD	134	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
	135	};
	136
f9094c52	137	static struct resource irqc0_resources[] __initdata = {
8f5ec0a5 MD	138	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	139	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	140	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	141	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	142	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	143	};
	144
	145	#define r8a7790_register_irqc(idx) \
	146	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
	147	idx, irqc##idx##_resources, \
	148	ARRAY_SIZE(irqc##idx##_resources), \
	149	&irqc##idx##_data, \
	150	sizeof(struct renesas_irqc_config))
	151
0468b2d6 MD	152	void __init r8a7790_add_standard_devices(void)
0468b2d6 MD	153	{
55d9fab2 MD	154	r8a7790_register_scif(SCIFA0);
	155	r8a7790_register_scif(SCIFA1);
	156	r8a7790_register_scif(SCIFB0);
	157	r8a7790_register_scif(SCIFB1);
	158	r8a7790_register_scif(SCIFB2);
	159	r8a7790_register_scif(SCIFA2);
	160	r8a7790_register_scif(SCIF0);
	161	r8a7790_register_scif(SCIF1);
d44f8308 UH	162	r8a7790_register_scif(HSCIF0);
d44f8308 UH	163	r8a7790_register_scif(HSCIF1);
8f5ec0a5	164	r8a7790_register_irqc(0);
0468b2d6 MD	165	}
0468b2d6 MD	166
ab5fdfd5 MD	167	void __init r8a7790_timer_init(void)
	168	{
	169	void __iomem *cntcr;
	170
	171	/* make sure arch timer is started by setting bit 0 of CNTCT */
	172	cntcr = ioremap(0xe6080000, PAGE_SIZE);
	173	iowrite32(1, cntcr);
	174	iounmap(cntcr);
	175
	176	shmobile_timer_init();
	177	}
	178
0468b2d6 MD	179	#ifdef CONFIG_USE_OF
	180	void __init r8a7790_add_standard_devices_dt(void)
	181	{
	182	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
	183	}
	184
	185	static const char *r8a7790_boards_compat_dt[] __initdata = {
	186	"renesas,r8a7790",
	187	NULL,
	188	};
	189
	190	DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
	191	.init_irq = irqchip_init,
	192	.init_machine = r8a7790_add_standard_devices_dt,
ab5fdfd5	193	.init_time = r8a7790_timer_init,
0468b2d6 MD	194	.dt_compat = r8a7790_boards_compat_dt,
	195	MACHINE_END
	196	#endif /* CONFIG_USE_OF */