[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7790.c

/*
 * r8a7790 processor support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/clocksource.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r8a7790.h>
#include <asm/mach/arch.h>

static const struct resource pfc_resources[] __initconst = {
	DEFINE_RES_MEM(0xe6060000, 0x250),
};

#define R8A7790_GPIO(idx)						\
static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
	DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),		\
	DEFINE_RES_IRQ(gic_spi(4 + (idx))),				\
};									\
									\
static const struct gpio_rcar_config					\
r8a7790_gpio##idx##_platform_data __initconst = {			\
	.gpio_base	= 32 * (idx),					\
	.irq_base	= 0,						\
	.number_of_pins	= 32,						\
	.pctl_name	= "pfc-r8a7790",				\
	.has_both_edge_trigger = 1,					\
};									\

R8A7790_GPIO(0);
R8A7790_GPIO(1);
R8A7790_GPIO(2);
R8A7790_GPIO(3);
R8A7790_GPIO(4);
R8A7790_GPIO(5);

#define r8a7790_register_gpio(idx)					\
	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
		r8a7790_gpio##idx##_resources,				\
		ARRAY_SIZE(r8a7790_gpio##idx##_resources),		\
		&r8a7790_gpio##idx##_platform_data,			\
		sizeof(r8a7790_gpio##idx##_platform_data))

void __init r8a7790_pinmux_init(void)
{
	platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
					ARRAY_SIZE(pfc_resources));
	r8a7790_register_gpio(0);
	r8a7790_register_gpio(1);
	r8a7790_register_gpio(2);
	r8a7790_register_gpio(3);
	r8a7790_register_gpio(4);
	r8a7790_register_gpio(5);
}

#define SCIF_COMMON(scif_type, baseaddr, irq)			\
	.type		= scif_type,				\
	.mapbase	= baseaddr,				\
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,	\
	.irqs		= SCIx_IRQ_MUXED(irq)

#define SCIFA_DATA(index, baseaddr, irq)		\
[index] = {						\
	SCIF_COMMON(PORT_SCIFA, baseaddr, irq),		\
	.scbrr_algo_id	= SCBRR_ALGO_4,			\
	.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0,	\
}

#define SCIFB_DATA(index, baseaddr, irq)	\
[index] = {					\
	SCIF_COMMON(PORT_SCIFB, baseaddr, irq),	\
	.scbrr_algo_id	= SCBRR_ALGO_4,		\
	.scscr = SCSCR_RE | SCSCR_TE,		\
}

#define SCIF_DATA(index, baseaddr, irq)		\
[index] = {						\
	SCIF_COMMON(PORT_SCIF, baseaddr, irq),		\
	.scbrr_algo_id	= SCBRR_ALGO_2,			\
	.scscr = SCSCR_RE | SCSCR_TE,	\
}

#define HSCIF_DATA(index, baseaddr, irq)		\
[index] = {						\
	SCIF_COMMON(PORT_HSCIF, baseaddr, irq),		\
	.scbrr_algo_id	= SCBRR_ALGO_6,			\
	.scscr = SCSCR_RE | SCSCR_TE,	\
}

enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
       HSCIF0, HSCIF1 };

static const struct plat_sci_port scif[] __initconst = {
	SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
	SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
	SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
	SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
	SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
	SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
	SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
	SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
	HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
	HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
};

static inline void r8a7790_register_scif(int idx)
{
	platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
				      sizeof(struct plat_sci_port));
}

static const struct renesas_irqc_config irqc0_data __initconst = {
	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
};

static const struct resource irqc0_resources[] __initconst = {
	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
};

#define r8a7790_register_irqc(idx)					\
	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
					  idx, irqc##idx##_resources,	\
					  ARRAY_SIZE(irqc##idx##_resources), \
					  &irqc##idx##_data,		\
					  sizeof(struct renesas_irqc_config))

static const struct resource thermal_resources[] __initconst = {
	DEFINE_RES_MEM(0xe61f0000, 0x14),
	DEFINE_RES_MEM(0xe61f0100, 0x38),
	DEFINE_RES_IRQ(gic_spi(69)),
};

#define r8a7790_register_thermal()					\
	platform_device_register_simple("rcar_thermal", -1,		\
					thermal_resources,		\
					ARRAY_SIZE(thermal_resources))

static const struct sh_timer_config cmt00_platform_data __initconst = {
	.name = "CMT00",
	.timer_bit = 0,
	.clockevent_rating = 80,
};

static const struct resource cmt00_resources[] __initconst = {
	DEFINE_RES_MEM(0xffca0510, 0x0c),
	DEFINE_RES_MEM(0xffca0500, 0x04),
	DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
};

#define r8a7790_register_cmt(idx)					\
	platform_device_register_resndata(&platform_bus, "sh_cmt",	\
					  idx, cmt##idx##_resources,	\
					  ARRAY_SIZE(cmt##idx##_resources), \
					  &cmt##idx##_platform_data,	\
					  sizeof(struct sh_timer_config))

void __init r8a7790_add_dt_devices(void)
{
	r8a7790_register_scif(SCIFA0);
	r8a7790_register_scif(SCIFA1);
	r8a7790_register_scif(SCIFB0);
	r8a7790_register_scif(SCIFB1);
	r8a7790_register_scif(SCIFB2);
	r8a7790_register_scif(SCIFA2);
	r8a7790_register_scif(SCIF0);
	r8a7790_register_scif(SCIF1);
	r8a7790_register_scif(HSCIF0);
	r8a7790_register_scif(HSCIF1);
	r8a7790_register_cmt(00);
}

void __init r8a7790_add_standard_devices(void)
{
	r8a7790_add_dt_devices();
	r8a7790_register_irqc(0);
	r8a7790_register_thermal();
}

#define MODEMR 0xe6160060

u32 __init r8a7790_read_mode_pins(void)
{
	void __iomem *modemr = ioremap_nocache(MODEMR, 4);
	u32 mode;

	BUG_ON(!modemr);
	mode = ioread32(modemr);
	iounmap(modemr);

	return mode;
}

#define CNTCR 0
#define CNTFID0 0x20

void __init r8a7790_timer_init(void)
{
#ifdef CONFIG_ARM_ARCH_TIMER
	u32 mode = r8a7790_read_mode_pins();
	void __iomem *base;
	int extal_mhz = 0;
	u32 freq;

	/* At Linux boot time the r8a7790 arch timer comes up
	 * with the counter disabled. Moreover, it may also report
	 * a potentially incorrect fixed 13 MHz frequency. To be
	 * correct these registers need to be updated to use the
	 * frequency EXTAL / 2 which can be determined by the MD pins.
	 */

	switch (mode & (MD(14) | MD(13))) {
	case 0:
		extal_mhz = 15;
		break;
	case MD(13):
		extal_mhz = 20;
		break;
	case MD(14):
		extal_mhz = 26;
		break;
	case MD(13) | MD(14):
		extal_mhz = 30;
		break;
	}

	/* The arch timer frequency equals EXTAL / 2 */
	freq = extal_mhz * (1000000 / 2);

	/* Remap "armgcnt address map" space */
	base = ioremap(0xe6080000, PAGE_SIZE);

	/* Update registers with correct frequency */
	iowrite32(freq, base + CNTFID0);
	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));

	/* make sure arch timer is started by setting bit 0 of CNTCR */
	iowrite32(1, base + CNTCR);
	iounmap(base);
#endif /* CONFIG_ARM_ARCH_TIMER */

	clocksource_of_init();
}

void __init r8a7790_init_early(void)
{
#ifndef CONFIG_ARM_ARCH_TIMER
	shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
#endif
}

#ifdef CONFIG_USE_OF

static const char * const r8a7790_boards_compat_dt[] __initconst = {
	"renesas,r8a7790",
	NULL,
};

DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
	.init_early	= r8a7790_init_early,
	.init_time	= r8a7790_timer_init,
	.dt_compat	= r8a7790_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
Commit	Line	Data
0468b2d6 MD	1	/*
	2	* r8a7790 processor support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Magnus Damm
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20
c4a62a5f	21	#include <linux/clocksource.h>
0468b2d6	22	#include <linux/irq.h>
0468b2d6 MD	23	#include <linux/kernel.h>
0468b2d6 MD	24	#include <linux/of_platform.h>
43ca9cbb	25	#include <linux/platform_data/gpio-rcar.h>
8f5ec0a5	26	#include <linux/platform_data/irq-renesas-irqc.h>
99ade1a0 MD	27	#include <linux/serial_sci.h>
99ade1a0 MD	28	#include <linux/sh_timer.h>
0468b2d6 MD	29	#include <mach/common.h>
	30	#include <mach/irqs.h>
	31	#include <mach/r8a7790.h>
	32	#include <asm/mach/arch.h>
	33
cde214a8	34	static const struct resource pfc_resources[] __initconst = {
69e351d0 MD	35	DEFINE_RES_MEM(0xe6060000, 0x250),
	36	};
	37
43ca9cbb	38	#define R8A7790_GPIO(idx) \
cde214a8	39	static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
43ca9cbb LP	40	DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
	41	DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
	42	}; \
	43	\
cde214a8 LP	44	static const struct gpio_rcar_config \
cde214a8 LP	45	r8a7790_gpio##idx##_platform_data __initconst = { \
43ca9cbb LP	46	.gpio_base = 32 * (idx), \
	47	.irq_base = 0, \
	48	.number_of_pins = 32, \
	49	.pctl_name = "pfc-r8a7790", \
d93906b8	50	.has_both_edge_trigger = 1, \
43ca9cbb LP	51	}; \
	52
	53	R8A7790_GPIO(0);
	54	R8A7790_GPIO(1);
	55	R8A7790_GPIO(2);
	56	R8A7790_GPIO(3);
	57	R8A7790_GPIO(4);
	58	R8A7790_GPIO(5);
	59
	60	#define r8a7790_register_gpio(idx) \
	61	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
	62	r8a7790_gpio##idx##_resources, \
	63	ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
	64	&r8a7790_gpio##idx##_platform_data, \
	65	sizeof(r8a7790_gpio##idx##_platform_data))
	66
69e351d0 MD	67	void __init r8a7790_pinmux_init(void)
	68	{
	69	platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
	70	ARRAY_SIZE(pfc_resources));
43ca9cbb LP	71	r8a7790_register_gpio(0);
	72	r8a7790_register_gpio(1);
	73	r8a7790_register_gpio(2);
	74	r8a7790_register_gpio(3);
	75	r8a7790_register_gpio(4);
	76	r8a7790_register_gpio(5);
69e351d0 MD	77	}
69e351d0 MD	78
55d9fab2 MD	79	#define SCIF_COMMON(scif_type, baseaddr, irq) \
	80	.type = scif_type, \
	81	.mapbase = baseaddr, \
	82	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP, \
	83	.irqs = SCIx_IRQ_MUXED(irq)
	84
	85	#define SCIFA_DATA(index, baseaddr, irq) \
	86	[index] = { \
	87	SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
	88	.scbrr_algo_id = SCBRR_ALGO_4, \
	89	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE0, \
	90	}
	91
	92	#define SCIFB_DATA(index, baseaddr, irq) \
	93	[index] = { \
	94	SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
	95	.scbrr_algo_id = SCBRR_ALGO_4, \
	96	.scscr = SCSCR_RE \| SCSCR_TE, \
	97	}
	98
	99	#define SCIF_DATA(index, baseaddr, irq) \
	100	[index] = { \
	101	SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
	102	.scbrr_algo_id = SCBRR_ALGO_2, \
c972f024	103	.scscr = SCSCR_RE \| SCSCR_TE, \
55d9fab2 MD	104	}
55d9fab2 MD	105
d44f8308 UH	106	#define HSCIF_DATA(index, baseaddr, irq) \
	107	[index] = { \
	108	SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
	109	.scbrr_algo_id = SCBRR_ALGO_6, \
	110	.scscr = SCSCR_RE \| SCSCR_TE, \
	111	}
	112
	113	enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
	114	HSCIF0, HSCIF1 };
55d9fab2	115
cde214a8	116	static const struct plat_sci_port scif[] __initconst = {
55d9fab2 MD	117	SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
	118	SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
	119	SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
	120	SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
	121	SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
	122	SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
	123	SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
	124	SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
d44f8308 UH	125	HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
d44f8308 UH	126	HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
55d9fab2 MD	127	};
	128
	129	static inline void r8a7790_register_scif(int idx)
	130	{
	131	platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
	132	sizeof(struct plat_sci_port));
	133	}
	134
cde214a8	135	static const struct renesas_irqc_config irqc0_data __initconst = {
8f5ec0a5 MD	136	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
	137	};
	138
cde214a8	139	static const struct resource irqc0_resources[] __initconst = {
8f5ec0a5 MD	140	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	141	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	142	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	143	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	144	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	145	};
	146
	147	#define r8a7790_register_irqc(idx) \
	148	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
	149	idx, irqc##idx##_resources, \
	150	ARRAY_SIZE(irqc##idx##_resources), \
	151	&irqc##idx##_data, \
	152	sizeof(struct renesas_irqc_config))
	153
cde214a8	154	static const struct resource thermal_resources[] __initconst = {
0b8eeba4 SH	155	DEFINE_RES_MEM(0xe61f0000, 0x14),
	156	DEFINE_RES_MEM(0xe61f0100, 0x38),
	157	DEFINE_RES_IRQ(gic_spi(69)),
	158	};
	159
	160	#define r8a7790_register_thermal() \
	161	platform_device_register_simple("rcar_thermal", -1, \
	162	thermal_resources, \
	163	ARRAY_SIZE(thermal_resources))
	164
cde214a8	165	static const struct sh_timer_config cmt00_platform_data __initconst = {
99ade1a0 MD	166	.name = "CMT00",
	167	.timer_bit = 0,
	168	.clockevent_rating = 80,
	169	};
	170
cde214a8	171	static const struct resource cmt00_resources[] __initconst = {
99ade1a0 MD	172	DEFINE_RES_MEM(0xffca0510, 0x0c),
	173	DEFINE_RES_MEM(0xffca0500, 0x04),
	174	DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
	175	};
	176
	177	#define r8a7790_register_cmt(idx) \
	178	platform_device_register_resndata(&platform_bus, "sh_cmt", \
	179	idx, cmt##idx##_resources, \
	180	ARRAY_SIZE(cmt##idx##_resources), \
	181	&cmt##idx##_platform_data, \
	182	sizeof(struct sh_timer_config))
	183
6dace67f	184	void __init r8a7790_add_dt_devices(void)
0468b2d6	185	{
55d9fab2 MD	186	r8a7790_register_scif(SCIFA0);
	187	r8a7790_register_scif(SCIFA1);
	188	r8a7790_register_scif(SCIFB0);
	189	r8a7790_register_scif(SCIFB1);
	190	r8a7790_register_scif(SCIFB2);
	191	r8a7790_register_scif(SCIFA2);
	192	r8a7790_register_scif(SCIF0);
	193	r8a7790_register_scif(SCIF1);
d44f8308 UH	194	r8a7790_register_scif(HSCIF0);
d44f8308 UH	195	r8a7790_register_scif(HSCIF1);
6dace67f SH	196	r8a7790_register_cmt(00);
	197	}
	198
	199	void __init r8a7790_add_standard_devices(void)
	200	{
	201	r8a7790_add_dt_devices();
8f5ec0a5	202	r8a7790_register_irqc(0);
0b8eeba4	203	r8a7790_register_thermal();
0468b2d6 MD	204	}
0468b2d6 MD	205
512e53bc MD	206	#define MODEMR 0xe6160060
	207
	208	u32 __init r8a7790_read_mode_pins(void)
	209	{
	210	void __iomem *modemr = ioremap_nocache(MODEMR, 4);
	211	u32 mode;
	212
	213	BUG_ON(!modemr);
	214	mode = ioread32(modemr);
	215	iounmap(modemr);
	216
	217	return mode;
	218	}
	219
81b9d535 MD	220	#define CNTCR 0
	221	#define CNTFID0 0x20
	222
ab5fdfd5 MD	223	void __init r8a7790_timer_init(void)
ab5fdfd5 MD	224	{
81b9d535 MD	225	#ifdef CONFIG_ARM_ARCH_TIMER
	226	u32 mode = r8a7790_read_mode_pins();
	227	void __iomem *base;
	228	int extal_mhz = 0;
	229	u32 freq;
	230
	231	/* At Linux boot time the r8a7790 arch timer comes up
	232	* with the counter disabled. Moreover, it may also report
	233	* a potentially incorrect fixed 13 MHz frequency. To be
	234	* correct these registers need to be updated to use the
	235	* frequency EXTAL / 2 which can be determined by the MD pins.
	236	*/
	237
	238	switch (mode & (MD(14) \| MD(13))) {
	239	case 0:
	240	extal_mhz = 15;
	241	break;
	242	case MD(13):
	243	extal_mhz = 20;
	244	break;
	245	case MD(14):
	246	extal_mhz = 26;
	247	break;
	248	case MD(13) \| MD(14):
	249	extal_mhz = 30;
	250	break;
	251	}
	252
	253	/* The arch timer frequency equals EXTAL / 2 */
	254	freq = extal_mhz * (1000000 / 2);
	255
	256	/* Remap "armgcnt address map" space */
	257	base = ioremap(0xe6080000, PAGE_SIZE);
	258
	259	/* Update registers with correct frequency */
	260	iowrite32(freq, base + CNTFID0);
	261	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
	262
	263	/* make sure arch timer is started by setting bit 0 of CNTCR */
	264	iowrite32(1, base + CNTCR);
	265	iounmap(base);
	266	#endif /* CONFIG_ARM_ARCH_TIMER */
ab5fdfd5	267
c4a62a5f	268	clocksource_of_init();
ab5fdfd5 MD	269	}
ab5fdfd5 MD	270
0efd7faa	271	void __init r8a7790_init_early(void)
8333d8c9 MD	272	{
	273	#ifndef CONFIG_ARM_ARCH_TIMER
	274	shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
	275	#endif
	276	}
	277
0468b2d6	278	#ifdef CONFIG_USE_OF
0468b2d6	279
cde214a8	280	static const char * const r8a7790_boards_compat_dt[] __initconst = {
0468b2d6 MD	281	"renesas,r8a7790",
	282	NULL,
	283	};
	284
	285	DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
0efd7faa	286	.init_early = r8a7790_init_early,
ab5fdfd5	287	.init_time = r8a7790_timer_init,
0468b2d6 MD	288	.dt_compat = r8a7790_boards_compat_dt,
	289	MACHINE_END
	290	#endif /* CONFIG_USE_OF */