[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7790.c

/*
 * r8a7790 processor support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
#include <linux/sh_dma.h>
#include <linux/sh_timer.h>
#include <mach/r8a7790.h>
#include <asm/mach/arch.h>
#include "common.h"
#include "dma-register.h"
#include "irqs.h"
#include "rcar-gen2.h"

/* Audio-DMAC */
#define AUDIO_DMAC_SLAVE(_id, _addr, t, r)			\
{								\
	.slave_id	= AUDIO_DMAC_SLAVE_## _id ##_TX,	\
	.addr		= _addr + 0x8,				\
	.chcr		= CHCR_TX(XMIT_SZ_32BIT),		\
	.mid_rid	= t,					\
}, {								\
	.slave_id	= AUDIO_DMAC_SLAVE_## _id ##_RX,	\
	.addr		= _addr + 0xc,				\
	.chcr		= CHCR_RX(XMIT_SZ_32BIT),		\
	.mid_rid	= r,					\
}

static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
	AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
	AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
	AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
	AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
	AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
	AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
	AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
	AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
	AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
	AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
};

#define DMAE_CHANNEL(a, b)			\
{						\
	.offset		= (a) - 0x20,		\
	.dmars		= (a) - 0x20 + 0x40,	\
	.chclr_bit	= (b),			\
	.chclr_offset	= 0x80 - 0x20,		\
}

static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
	DMAE_CHANNEL(0x8000, 0),
	DMAE_CHANNEL(0x8080, 1),
	DMAE_CHANNEL(0x8100, 2),
	DMAE_CHANNEL(0x8180, 3),
	DMAE_CHANNEL(0x8200, 4),
	DMAE_CHANNEL(0x8280, 5),
	DMAE_CHANNEL(0x8300, 6),
	DMAE_CHANNEL(0x8380, 7),
	DMAE_CHANNEL(0x8400, 8),
	DMAE_CHANNEL(0x8480, 9),
	DMAE_CHANNEL(0x8500, 10),
	DMAE_CHANNEL(0x8580, 11),
	DMAE_CHANNEL(0x8600, 12),
};

static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
	.slave		= r8a7790_audio_dmac_slaves,
	.slave_num	= ARRAY_SIZE(r8a7790_audio_dmac_slaves),
	.channel	= r8a7790_audio_dmac_channels,
	.channel_num	= ARRAY_SIZE(r8a7790_audio_dmac_channels),
	.ts_low_shift	= TS_LOW_SHIFT,
	.ts_low_mask	= TS_LOW_BIT << TS_LOW_SHIFT,
	.ts_high_shift	= TS_HI_SHIFT,
	.ts_high_mask	= TS_HI_BIT << TS_HI_SHIFT,
	.ts_shift	= dma_ts_shift,
	.ts_shift_num	= ARRAY_SIZE(dma_ts_shift),
	.dmaor_init	= DMAOR_DME,
	.chclr_present	= 1,
	.chclr_bitwise	= 1,
};

static struct resource r8a7790_audio_dmac_resources[] = {
	/* Channel registers and DMAOR for low */
	DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
	DEFINE_RES_IRQ(gic_spi(346)),
	DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),

	/* Channel registers and DMAOR for hi */
	DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
	DEFINE_RES_IRQ(gic_spi(347)),
	DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
};

#define r8a7790_register_audio_dmac(id)				\
	platform_device_register_resndata(			\
		&platform_bus, "sh-dma-engine", id,		\
		&r8a7790_audio_dmac_resources[id * 3],	3,	\
		&r8a7790_audio_dmac_platform_data,		\
		sizeof(r8a7790_audio_dmac_platform_data))

static const struct resource pfc_resources[] __initconst = {
	DEFINE_RES_MEM(0xe6060000, 0x250),
};

#define r8a7790_register_pfc()						\
	platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
					ARRAY_SIZE(pfc_resources))

#define R8A7790_GPIO(idx)						\
static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
	DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),		\
	DEFINE_RES_IRQ(gic_spi(4 + (idx))),				\
};									\
									\
static const struct gpio_rcar_config					\
r8a7790_gpio##idx##_platform_data __initconst = {			\
	.gpio_base	= 32 * (idx),					\
	.irq_base	= 0,						\
	.number_of_pins	= 32,						\
	.pctl_name	= "pfc-r8a7790",				\
	.has_both_edge_trigger = 1,					\
};									\

R8A7790_GPIO(0);
R8A7790_GPIO(1);
R8A7790_GPIO(2);
R8A7790_GPIO(3);
R8A7790_GPIO(4);
R8A7790_GPIO(5);

#define r8a7790_register_gpio(idx)					\
	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
		r8a7790_gpio##idx##_resources,				\
		ARRAY_SIZE(r8a7790_gpio##idx##_resources),		\
		&r8a7790_gpio##idx##_platform_data,			\
		sizeof(r8a7790_gpio##idx##_platform_data))

static struct resource i2c_resources[] __initdata = {
	/* I2C0 */
	DEFINE_RES_MEM(0xE6508000, 0x40),
	DEFINE_RES_IRQ(gic_spi(287)),
	/* I2C1 */
	DEFINE_RES_MEM(0xE6518000, 0x40),
	DEFINE_RES_IRQ(gic_spi(288)),
	/* I2C2 */
	DEFINE_RES_MEM(0xE6530000, 0x40),
	DEFINE_RES_IRQ(gic_spi(286)),
	/* I2C3 */
	DEFINE_RES_MEM(0xE6540000, 0x40),
	DEFINE_RES_IRQ(gic_spi(290)),

};

#define r8a7790_register_i2c(idx)		\
	platform_device_register_simple(	\
		"i2c-rcar_gen2", idx,		\
		i2c_resources + (2 * idx), 2);	\

void __init r8a7790_pinmux_init(void)
{
	r8a7790_register_pfc();
	r8a7790_register_gpio(0);
	r8a7790_register_gpio(1);
	r8a7790_register_gpio(2);
	r8a7790_register_gpio(3);
	r8a7790_register_gpio(4);
	r8a7790_register_gpio(5);
}

#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq)		\
static struct plat_sci_port scif##index##_platform_data = {		\
	.type		= scif_type,					\
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,		\
	.scscr		= _scscr,					\
};									\
									\
static struct resource scif##index##_resources[] = {			\
	DEFINE_RES_MEM(baseaddr, 0x100),				\
	DEFINE_RES_IRQ(irq),						\
}

#define R8A7790_SCIF(index, baseaddr, irq)				\
	__R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE,			\
		       index, baseaddr, irq)

#define R8A7790_SCIFA(index, baseaddr, irq)				\
	__R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0,	\
		       index, baseaddr, irq)

#define R8A7790_SCIFB(index, baseaddr, irq)				\
	__R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE,			\
		       index, baseaddr, irq)

#define R8A7790_HSCIF(index, baseaddr, irq)				\
	__R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE,			\
		       index, baseaddr, irq)

R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
R8A7790_SCIF(6,  0xe6e60000, gic_spi(152)); /* SCIF0 */
R8A7790_SCIF(7,  0xe6e68000, gic_spi(153)); /* SCIF1 */
R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */

#define r8a7790_register_scif(index)					       \
	platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
					  scif##index##_resources,	       \
					  ARRAY_SIZE(scif##index##_resources), \
					  &scif##index##_platform_data,	       \
					  sizeof(scif##index##_platform_data))

static const struct renesas_irqc_config irqc0_data __initconst = {
	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
};

static const struct resource irqc0_resources[] __initconst = {
	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
};

#define r8a7790_register_irqc(idx)					\
	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
					  idx, irqc##idx##_resources,	\
					  ARRAY_SIZE(irqc##idx##_resources), \
					  &irqc##idx##_data,		\
					  sizeof(struct renesas_irqc_config))

static const struct resource thermal_resources[] __initconst = {
	DEFINE_RES_MEM(0xe61f0000, 0x14),
	DEFINE_RES_MEM(0xe61f0100, 0x38),
	DEFINE_RES_IRQ(gic_spi(69)),
};

#define r8a7790_register_thermal()					\
	platform_device_register_simple("rcar_thermal", -1,		\
					thermal_resources,		\
					ARRAY_SIZE(thermal_resources))

static struct sh_timer_config cmt0_platform_data = {
	.channels_mask = 0x60,
};

static struct resource cmt0_resources[] = {
	DEFINE_RES_MEM(0xffca0000, 0x1004),
	DEFINE_RES_IRQ(gic_spi(142)),
};

#define r8a7790_register_cmt(idx)					\
	platform_device_register_resndata(&platform_bus, "sh-cmt-48-gen2", \
					  idx, cmt##idx##_resources,	\
					  ARRAY_SIZE(cmt##idx##_resources), \
					  &cmt##idx##_platform_data,	\
					  sizeof(struct sh_timer_config))

void __init r8a7790_add_dt_devices(void)
{
	r8a7790_register_cmt(0);
}

void __init r8a7790_add_standard_devices(void)
{
	r8a7790_register_scif(0);
	r8a7790_register_scif(1);
	r8a7790_register_scif(2);
	r8a7790_register_scif(3);
	r8a7790_register_scif(4);
	r8a7790_register_scif(5);
	r8a7790_register_scif(6);
	r8a7790_register_scif(7);
	r8a7790_register_scif(8);
	r8a7790_register_scif(9);
	r8a7790_add_dt_devices();
	r8a7790_register_irqc(0);
	r8a7790_register_thermal();
	r8a7790_register_i2c(0);
	r8a7790_register_i2c(1);
	r8a7790_register_i2c(2);
	r8a7790_register_i2c(3);
	r8a7790_register_audio_dmac(0);
	r8a7790_register_audio_dmac(1);
}

void __init r8a7790_init_early(void)
{
#ifndef CONFIG_ARM_ARCH_TIMER
	shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
#endif
}

#ifdef CONFIG_USE_OF

static const char * const r8a7790_boards_compat_dt[] __initconst = {
	"renesas,r8a7790",
	NULL,
};

DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
	.smp		= smp_ops(r8a7790_smp_ops),
	.init_early	= r8a7790_init_early,
	.init_time	= rcar_gen2_timer_init,
	.dt_compat	= r8a7790_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
Commit	Line	Data
0468b2d6 MD	1	/*
	2	* r8a7790 processor support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Magnus Damm
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20
	21	#include <linux/irq.h>
0468b2d6 MD	22	#include <linux/kernel.h>
0468b2d6 MD	23	#include <linux/of_platform.h>
43ca9cbb	24	#include <linux/platform_data/gpio-rcar.h>
8f5ec0a5	25	#include <linux/platform_data/irq-renesas-irqc.h>
99ade1a0	26	#include <linux/serial_sci.h>
2c578a1b	27	#include <linux/sh_dma.h>
99ade1a0	28	#include <linux/sh_timer.h>
0468b2d6 MD	29	#include <mach/r8a7790.h>
0468b2d6 MD	30	#include <asm/mach/arch.h>
fd44aa5e	31	#include "common.h"
74ac0de8	32	#include "dma-register.h"
b6bab126	33	#include "irqs.h"
62872989	34	#include "rcar-gen2.h"
0468b2d6	35
2c578a1b KM	36	/* Audio-DMAC */
	37	#define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \
	38	{ \
	39	.slave_id = AUDIO_DMAC_SLAVE_## _id ##_TX, \
	40	.addr = _addr + 0x8, \
	41	.chcr = CHCR_TX(XMIT_SZ_32BIT), \
	42	.mid_rid = t, \
	43	}, { \
	44	.slave_id = AUDIO_DMAC_SLAVE_## _id ##_RX, \
	45	.addr = _addr + 0xc, \
	46	.chcr = CHCR_RX(XMIT_SZ_32BIT), \
	47	.mid_rid = r, \
	48	}
	49
	50	static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
	51	AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
	52	AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
	53	AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
	54	AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
	55	AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
	56	AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
	57	AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
	58	AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
	59	AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
	60	AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
	61	};
	62
	63	#define DMAE_CHANNEL(a, b) \
	64	{ \
	65	.offset = (a) - 0x20, \
	66	.dmars = (a) - 0x20 + 0x40, \
	67	.chclr_bit = (b), \
	68	.chclr_offset = 0x80 - 0x20, \
	69	}
	70
	71	static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
	72	DMAE_CHANNEL(0x8000, 0),
	73	DMAE_CHANNEL(0x8080, 1),
	74	DMAE_CHANNEL(0x8100, 2),
	75	DMAE_CHANNEL(0x8180, 3),
	76	DMAE_CHANNEL(0x8200, 4),
	77	DMAE_CHANNEL(0x8280, 5),
	78	DMAE_CHANNEL(0x8300, 6),
	79	DMAE_CHANNEL(0x8380, 7),
	80	DMAE_CHANNEL(0x8400, 8),
	81	DMAE_CHANNEL(0x8480, 9),
	82	DMAE_CHANNEL(0x8500, 10),
	83	DMAE_CHANNEL(0x8580, 11),
	84	DMAE_CHANNEL(0x8600, 12),
	85	};
	86
	87	static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
	88	.slave = r8a7790_audio_dmac_slaves,
	89	.slave_num = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
	90	.channel = r8a7790_audio_dmac_channels,
	91	.channel_num = ARRAY_SIZE(r8a7790_audio_dmac_channels),
	92	.ts_low_shift = TS_LOW_SHIFT,
	93	.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
	94	.ts_high_shift = TS_HI_SHIFT,
	95	.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
	96	.ts_shift = dma_ts_shift,
	97	.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
	98	.dmaor_init = DMAOR_DME,
	99	.chclr_present = 1,
100	.chclr_bitwise = 1,
101	};
102
103	static struct resource r8a7790_audio_dmac_resources[] = {
104	/* Channel registers and DMAOR for low */
105	DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
106	DEFINE_RES_IRQ(gic_spi(346)),
107	DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
108
109	/* Channel registers and DMAOR for hi */
110	DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
111	DEFINE_RES_IRQ(gic_spi(347)),
112	DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
113	};
114
115	#define r8a7790_register_audio_dmac(id) \
116	platform_device_register_resndata( \
117	&platform_bus, "sh-dma-engine", id, \
118	&r8a7790_audio_dmac_resources[id * 3], 3, \
119	&r8a7790_audio_dmac_platform_data, \
120	sizeof(r8a7790_audio_dmac_platform_data))
121
cde214a8	122	static const struct resource pfc_resources[] __initconst = {
69e351d0 MD	123	DEFINE_RES_MEM(0xe6060000, 0x250),
	124	};
	125
8d0b3bf7 MD	126	#define r8a7790_register_pfc() \
	127	platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
	128	ARRAY_SIZE(pfc_resources))
	129
43ca9cbb	130	#define R8A7790_GPIO(idx) \
cde214a8	131	static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
43ca9cbb LP	132	DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
	133	DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
	134	}; \
	135	\
cde214a8 LP	136	static const struct gpio_rcar_config \
cde214a8 LP	137	r8a7790_gpio##idx##_platform_data __initconst = { \
43ca9cbb LP	138	.gpio_base = 32 * (idx), \
	139	.irq_base = 0, \
	140	.number_of_pins = 32, \
	141	.pctl_name = "pfc-r8a7790", \
d93906b8	142	.has_both_edge_trigger = 1, \
43ca9cbb LP	143	}; \
	144
	145	R8A7790_GPIO(0);
	146	R8A7790_GPIO(1);
	147	R8A7790_GPIO(2);
	148	R8A7790_GPIO(3);
	149	R8A7790_GPIO(4);
	150	R8A7790_GPIO(5);
	151
	152	#define r8a7790_register_gpio(idx) \
	153	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
	154	r8a7790_gpio##idx##_resources, \
	155	ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
	156	&r8a7790_gpio##idx##_platform_data, \
	157	sizeof(r8a7790_gpio##idx##_platform_data))
	158
b448c904 KM	159	static struct resource i2c_resources[] __initdata = {
	160	/* I2C0 */
	161	DEFINE_RES_MEM(0xE6508000, 0x40),
	162	DEFINE_RES_IRQ(gic_spi(287)),
	163	/* I2C1 */
	164	DEFINE_RES_MEM(0xE6518000, 0x40),
	165	DEFINE_RES_IRQ(gic_spi(288)),
	166	/* I2C2 */
	167	DEFINE_RES_MEM(0xE6530000, 0x40),
	168	DEFINE_RES_IRQ(gic_spi(286)),
	169	/* I2C3 */
	170	DEFINE_RES_MEM(0xE6540000, 0x40),
	171	DEFINE_RES_IRQ(gic_spi(290)),
	172
	173	};
	174
	175	#define r8a7790_register_i2c(idx) \
	176	platform_device_register_simple( \
db455c78	177	"i2c-rcar_gen2", idx, \
b448c904 KM	178	i2c_resources + (2 * idx), 2); \
b448c904 KM	179
69e351d0 MD	180	void __init r8a7790_pinmux_init(void)
69e351d0 MD	181	{
8d0b3bf7	182	r8a7790_register_pfc();
43ca9cbb LP	183	r8a7790_register_gpio(0);
	184	r8a7790_register_gpio(1);
	185	r8a7790_register_gpio(2);
	186	r8a7790_register_gpio(3);
	187	r8a7790_register_gpio(4);
	188	r8a7790_register_gpio(5);
69e351d0 MD	189	}
69e351d0 MD	190
6319ea50	191	#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
302d8898 LP	192	static struct plat_sci_port scif##index##_platform_data = { \
302d8898 LP	193	.type = scif_type, \
302d8898	194	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP, \
302d8898	195	.scscr = _scscr, \
c0a384f5 LP	196	}; \
	197	\
	198	static struct resource scif##index##_resources[] = { \
	199	DEFINE_RES_MEM(baseaddr, 0x100), \
	200	DEFINE_RES_IRQ(irq), \
d44f8308 UH	201	}
d44f8308 UH	202
302d8898 LP	203	#define R8A7790_SCIF(index, baseaddr, irq) \
302d8898 LP	204	__R8A7790_SCIF(PORT_SCIF, SCSCR_RE \| SCSCR_TE, \
6319ea50	205	index, baseaddr, irq)
302d8898 LP	206
	207	#define R8A7790_SCIFA(index, baseaddr, irq) \
	208	__R8A7790_SCIF(PORT_SCIFA, SCSCR_RE \| SCSCR_TE \| SCSCR_CKE0, \
6319ea50	209	index, baseaddr, irq)
302d8898 LP	210
	211	#define R8A7790_SCIFB(index, baseaddr, irq) \
	212	__R8A7790_SCIF(PORT_SCIFB, SCSCR_RE \| SCSCR_TE, \
6319ea50	213	index, baseaddr, irq)
302d8898 LP	214
	215	#define R8A7790_HSCIF(index, baseaddr, irq) \
	216	__R8A7790_SCIF(PORT_HSCIF, SCSCR_RE \| SCSCR_TE, \
6319ea50	217	index, baseaddr, irq)
302d8898 LP	218
	219	R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
	220	R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
	221	R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
	222	R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
	223	R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
	224	R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
	225	R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
	226	R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
	227	R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
	228	R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
	229
	230	#define r8a7790_register_scif(index) \
c0a384f5 LP	231	platform_device_register_resndata(&platform_bus, "sh-sci", index, \
	232	scif##index##_resources, \
	233	ARRAY_SIZE(scif##index##_resources), \
	234	&scif##index##_platform_data, \
	235	sizeof(scif##index##_platform_data))
55d9fab2	236
cde214a8	237	static const struct renesas_irqc_config irqc0_data __initconst = {
8f5ec0a5 MD	238	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
	239	};
	240
cde214a8	241	static const struct resource irqc0_resources[] __initconst = {
8f5ec0a5 MD	242	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	243	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	244	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	245	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	246	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	247	};
	248
	249	#define r8a7790_register_irqc(idx) \
	250	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
	251	idx, irqc##idx##_resources, \
	252	ARRAY_SIZE(irqc##idx##_resources), \
	253	&irqc##idx##_data, \
	254	sizeof(struct renesas_irqc_config))
	255
cde214a8	256	static const struct resource thermal_resources[] __initconst = {
0b8eeba4 SH	257	DEFINE_RES_MEM(0xe61f0000, 0x14),
	258	DEFINE_RES_MEM(0xe61f0100, 0x38),
	259	DEFINE_RES_IRQ(gic_spi(69)),
	260	};
	261
	262	#define r8a7790_register_thermal() \
	263	platform_device_register_simple("rcar_thermal", -1, \
	264	thermal_resources, \
	265	ARRAY_SIZE(thermal_resources))
	266
711ee6c8 LP	267	static struct sh_timer_config cmt0_platform_data = {
711ee6c8 LP	268	.channels_mask = 0x60,
99ade1a0 MD	269	};
99ade1a0 MD	270
711ee6c8 LP	271	static struct resource cmt0_resources[] = {
	272	DEFINE_RES_MEM(0xffca0000, 0x1004),
	273	DEFINE_RES_IRQ(gic_spi(142)),
99ade1a0 MD	274	};
	275
	276	#define r8a7790_register_cmt(idx) \
711ee6c8	277	platform_device_register_resndata(&platform_bus, "sh-cmt-48-gen2", \
99ade1a0 MD	278	idx, cmt##idx##_resources, \
	279	ARRAY_SIZE(cmt##idx##_resources), \
	280	&cmt##idx##_platform_data, \
	281	sizeof(struct sh_timer_config))
	282
6dace67f	283	void __init r8a7790_add_dt_devices(void)
4e9c4877 LP	284	{
	285	r8a7790_register_cmt(0);
	286	}
	287
	288	void __init r8a7790_add_standard_devices(void)
0468b2d6	289	{
302d8898 LP	290	r8a7790_register_scif(0);
	291	r8a7790_register_scif(1);
	292	r8a7790_register_scif(2);
	293	r8a7790_register_scif(3);
	294	r8a7790_register_scif(4);
	295	r8a7790_register_scif(5);
	296	r8a7790_register_scif(6);
	297	r8a7790_register_scif(7);
	298	r8a7790_register_scif(8);
	299	r8a7790_register_scif(9);
6dace67f	300	r8a7790_add_dt_devices();
8f5ec0a5	301	r8a7790_register_irqc(0);
0b8eeba4	302	r8a7790_register_thermal();
f05b4b52 MD	303	r8a7790_register_i2c(0);
	304	r8a7790_register_i2c(1);
	305	r8a7790_register_i2c(2);
	306	r8a7790_register_i2c(3);
	307	r8a7790_register_audio_dmac(0);
	308	r8a7790_register_audio_dmac(1);
0468b2d6 MD	309	}
0468b2d6 MD	310
0efd7faa	311	void __init r8a7790_init_early(void)
8333d8c9 MD	312	{
	313	#ifndef CONFIG_ARM_ARCH_TIMER
	314	shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
	315	#endif
	316	}
	317
0468b2d6	318	#ifdef CONFIG_USE_OF
0468b2d6	319
cde214a8	320	static const char * const r8a7790_boards_compat_dt[] __initconst = {
0468b2d6 MD	321	"renesas,r8a7790",
	322	NULL,
	323	};
	324
	325	DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
ad09cb83	326	.smp = smp_ops(r8a7790_smp_ops),
0efd7faa	327	.init_early = r8a7790_init_early,
50c517d9	328	.init_time = rcar_gen2_timer_init,
0468b2d6 MD	329	.dt_compat = r8a7790_boards_compat_dt,
	330	MACHINE_END
	331	#endif /* CONFIG_USE_OF */