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0d0771ab HN |
1 | /* |
2 | * r8a7791 processor support | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Electronics Corporation | |
5 | * Copyright (C) 2013 Renesas Solutions Corp. | |
6 | * Copyright (C) 2013 Magnus Damm | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | */ | |
21 | ||
22 | #include <linux/irq.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/of_platform.h> | |
454d320c | 25 | #include <linux/platform_data/irq-renesas-irqc.h> |
e6491d08 | 26 | #include <linux/serial_sci.h> |
1bebd72a | 27 | #include <linux/sh_timer.h> |
0d0771ab | 28 | #include <mach/common.h> |
e6491d08 | 29 | #include <mach/irqs.h> |
0d0771ab HN |
30 | #include <mach/r8a7791.h> |
31 | #include <asm/mach/arch.h> | |
32 | ||
e6491d08 YF |
33 | #define SCIF_COMMON(scif_type, baseaddr, irq) \ |
34 | .type = scif_type, \ | |
35 | .mapbase = baseaddr, \ | |
36 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | |
37 | .irqs = SCIx_IRQ_MUXED(irq) | |
38 | ||
39 | #define SCIFA_DATA(index, baseaddr, irq) \ | |
40 | [index] = { \ | |
41 | SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ | |
42 | .scbrr_algo_id = SCBRR_ALGO_4, \ | |
43 | .scscr = SCSCR_RE | SCSCR_TE, \ | |
44 | } | |
45 | ||
46 | #define SCIFB_DATA(index, baseaddr, irq) \ | |
47 | [index] = { \ | |
48 | SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ | |
49 | .scbrr_algo_id = SCBRR_ALGO_4, \ | |
50 | .scscr = SCSCR_RE | SCSCR_TE, \ | |
51 | } | |
52 | ||
53 | #define SCIF_DATA(index, baseaddr, irq) \ | |
54 | [index] = { \ | |
55 | SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ | |
56 | .scbrr_algo_id = SCBRR_ALGO_2, \ | |
57 | .scscr = SCSCR_RE | SCSCR_TE, \ | |
58 | } | |
59 | ||
60 | #define HSCIF_DATA(index, baseaddr, irq) \ | |
61 | [index] = { \ | |
62 | SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ | |
63 | .scbrr_algo_id = SCBRR_ALGO_6, \ | |
64 | .scscr = SCSCR_RE | SCSCR_TE, \ | |
65 | } | |
66 | ||
67 | enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, | |
68 | SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 }; | |
69 | ||
70 | static const struct plat_sci_port scif[] __initconst = { | |
71 | SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ | |
72 | SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ | |
73 | SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ | |
74 | SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ | |
75 | SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ | |
76 | SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ | |
77 | SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ | |
78 | SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ | |
79 | SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */ | |
80 | SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */ | |
81 | SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */ | |
82 | SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */ | |
83 | SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */ | |
84 | SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */ | |
85 | SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */ | |
86 | }; | |
87 | ||
88 | static inline void r8a7791_register_scif(int idx) | |
89 | { | |
90 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | |
91 | sizeof(struct plat_sci_port)); | |
92 | } | |
93 | ||
1bebd72a MD |
94 | static const struct sh_timer_config cmt00_platform_data __initconst = { |
95 | .name = "CMT00", | |
96 | .timer_bit = 0, | |
97 | .clockevent_rating = 80, | |
98 | }; | |
99 | ||
100 | static const struct resource cmt00_resources[] __initconst = { | |
101 | DEFINE_RES_MEM(0xffca0510, 0x0c), | |
102 | DEFINE_RES_MEM(0xffca0500, 0x04), | |
103 | DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */ | |
104 | }; | |
105 | ||
106 | #define r8a7791_register_cmt(idx) \ | |
107 | platform_device_register_resndata(&platform_bus, "sh_cmt", \ | |
108 | idx, cmt##idx##_resources, \ | |
109 | ARRAY_SIZE(cmt##idx##_resources), \ | |
110 | &cmt##idx##_platform_data, \ | |
111 | sizeof(struct sh_timer_config)) | |
112 | ||
454d320c MD |
113 | static struct renesas_irqc_config irqc0_data = { |
114 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */ | |
115 | }; | |
116 | ||
117 | static struct resource irqc0_resources[] = { | |
118 | DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ | |
119 | DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ | |
120 | DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ | |
121 | DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ | |
122 | DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ | |
123 | DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */ | |
124 | DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */ | |
125 | DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */ | |
126 | DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */ | |
127 | DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */ | |
128 | DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */ | |
129 | }; | |
130 | ||
131 | #define r8a7791_register_irqc(idx) \ | |
132 | platform_device_register_resndata(&platform_bus, "renesas_irqc", \ | |
133 | idx, irqc##idx##_resources, \ | |
134 | ARRAY_SIZE(irqc##idx##_resources), \ | |
135 | &irqc##idx##_data, \ | |
136 | sizeof(struct renesas_irqc_config)) | |
137 | ||
e6491d08 YF |
138 | void __init r8a7791_add_dt_devices(void) |
139 | { | |
140 | r8a7791_register_scif(SCIFA0); | |
141 | r8a7791_register_scif(SCIFA1); | |
142 | r8a7791_register_scif(SCIFB0); | |
143 | r8a7791_register_scif(SCIFB1); | |
144 | r8a7791_register_scif(SCIFB2); | |
145 | r8a7791_register_scif(SCIFA2); | |
146 | r8a7791_register_scif(SCIF0); | |
147 | r8a7791_register_scif(SCIF1); | |
148 | r8a7791_register_scif(SCIF2); | |
149 | r8a7791_register_scif(SCIF3); | |
150 | r8a7791_register_scif(SCIF4); | |
151 | r8a7791_register_scif(SCIF5); | |
152 | r8a7791_register_scif(SCIFA3); | |
153 | r8a7791_register_scif(SCIFA4); | |
154 | r8a7791_register_scif(SCIFA5); | |
1bebd72a MD |
155 | r8a7791_register_cmt(00); |
156 | } | |
157 | ||
4275881f MD |
158 | void __init r8a7791_add_standard_devices(void) |
159 | { | |
160 | r8a7791_add_dt_devices(); | |
454d320c | 161 | r8a7791_register_irqc(0); |
4275881f MD |
162 | } |
163 | ||
1bebd72a MD |
164 | void __init r8a7791_init_early(void) |
165 | { | |
166 | #ifndef CONFIG_ARM_ARCH_TIMER | |
167 | shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */ | |
168 | #endif | |
e6491d08 YF |
169 | } |
170 | ||
0d0771ab HN |
171 | #ifdef CONFIG_USE_OF |
172 | static const char *r8a7791_boards_compat_dt[] __initdata = { | |
173 | "renesas,r8a7791", | |
174 | NULL, | |
175 | }; | |
176 | ||
177 | DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)") | |
1bebd72a | 178 | .init_early = r8a7791_init_early, |
0d0771ab HN |
179 | .dt_compat = r8a7791_boards_compat_dt, |
180 | MACHINE_END | |
181 | #endif /* CONFIG_USE_OF */ |