[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7791.c

/*
 * r8a7791 processor support
 *
 * Copyright (C) 2013  Renesas Electronics Corporation
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>

#include <asm/mach/arch.h>

#include "common.h"
#include "irqs.h"
#include "r8a7791.h"
#include "rcar-gen2.h"

static const struct resource pfc_resources[] __initconst = {
	DEFINE_RES_MEM(0xe6060000, 0x250),
};

#define r8a7791_register_pfc()						\
	platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
					ARRAY_SIZE(pfc_resources))

#define R8A7791_GPIO(idx, base, nr)					\
static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
	DEFINE_RES_MEM((base), 0x50),					\
	DEFINE_RES_IRQ(gic_spi(4 + (idx))),				\
};									\
									\
static const struct gpio_rcar_config					\
r8a7791_gpio##idx##_platform_data __initconst = {			\
	.gpio_base	= 32 * (idx),					\
	.irq_base	= 0,						\
	.number_of_pins	= (nr),						\
	.pctl_name	= "pfc-r8a7791",				\
	.has_both_edge_trigger = 1,					\
};									\

R8A7791_GPIO(0, 0xe6050000, 32);
R8A7791_GPIO(1, 0xe6051000, 32);
R8A7791_GPIO(2, 0xe6052000, 32);
R8A7791_GPIO(3, 0xe6053000, 32);
R8A7791_GPIO(4, 0xe6054000, 32);
R8A7791_GPIO(5, 0xe6055000, 32);
R8A7791_GPIO(6, 0xe6055400, 32);
R8A7791_GPIO(7, 0xe6055800, 26);

#define r8a7791_register_gpio(idx)					\
	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
		r8a7791_gpio##idx##_resources,				\
		ARRAY_SIZE(r8a7791_gpio##idx##_resources),		\
		&r8a7791_gpio##idx##_platform_data,			\
		sizeof(r8a7791_gpio##idx##_platform_data))

void __init r8a7791_pinmux_init(void)
{
	r8a7791_register_pfc();
	r8a7791_register_gpio(0);
	r8a7791_register_gpio(1);
	r8a7791_register_gpio(2);
	r8a7791_register_gpio(3);
	r8a7791_register_gpio(4);
	r8a7791_register_gpio(5);
	r8a7791_register_gpio(6);
	r8a7791_register_gpio(7);
}

#define __R8A7791_SCIF(scif_type, index, baseaddr, irq)			\
static struct plat_sci_port scif##index##_platform_data = {		\
	.type		= scif_type,					\
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,		\
	.scscr		= SCSCR_RE | SCSCR_TE,				\
};									\
									\
static struct resource scif##index##_resources[] = {			\
	DEFINE_RES_MEM(baseaddr, 0x100),				\
	DEFINE_RES_IRQ(irq),						\
}

#define R8A7791_SCIF(index, baseaddr, irq)				\
	__R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)

#define R8A7791_SCIFA(index, baseaddr, irq)				\
	__R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)

#define R8A7791_SCIFB(index, baseaddr, irq)				\
	__R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)

R8A7791_SCIFA(0,  0xe6c40000, gic_spi(144)); /* SCIFA0 */
R8A7791_SCIFA(1,  0xe6c50000, gic_spi(145)); /* SCIFA1 */
R8A7791_SCIFB(2,  0xe6c20000, gic_spi(148)); /* SCIFB0 */
R8A7791_SCIFB(3,  0xe6c30000, gic_spi(149)); /* SCIFB1 */
R8A7791_SCIFB(4,  0xe6ce0000, gic_spi(150)); /* SCIFB2 */
R8A7791_SCIFA(5,  0xe6c60000, gic_spi(151)); /* SCIFA2 */
R8A7791_SCIF(6,   0xe6e60000, gic_spi(152)); /* SCIF0 */
R8A7791_SCIF(7,   0xe6e68000, gic_spi(153)); /* SCIF1 */
R8A7791_SCIF(8,   0xe6e58000, gic_spi(22)); /* SCIF2 */
R8A7791_SCIF(9,   0xe6ea8000, gic_spi(23)); /* SCIF3 */
R8A7791_SCIF(10,  0xe6ee0000, gic_spi(24)); /* SCIF4 */
R8A7791_SCIF(11,  0xe6ee8000, gic_spi(25)); /* SCIF5 */
R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */

#define r8a7791_register_scif(index)					       \
	platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
					  scif##index##_resources,	       \
					  ARRAY_SIZE(scif##index##_resources), \
					  &scif##index##_platform_data,	       \
					  sizeof(scif##index##_platform_data))

static struct sh_timer_config cmt0_platform_data = {
	.channels_mask = 0x60,
};

static struct resource cmt0_resources[] = {
	DEFINE_RES_MEM(0xffca0000, 0x1004),
	DEFINE_RES_IRQ(gic_spi(142)),
};

#define r8a7791_register_cmt(idx)					\
	platform_device_register_resndata(&platform_bus, "sh-cmt-48-gen2", \
					  idx, cmt##idx##_resources,	\
					  ARRAY_SIZE(cmt##idx##_resources), \
					  &cmt##idx##_platform_data,	\
					  sizeof(struct sh_timer_config))

static struct renesas_irqc_config irqc0_data = {
	.irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
};

static struct resource irqc0_resources[] = {
	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
	DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
	DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
	DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
	DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
	DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
};

#define r8a7791_register_irqc(idx)					\
	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
					  idx, irqc##idx##_resources,	\
					  ARRAY_SIZE(irqc##idx##_resources), \
					  &irqc##idx##_data,		\
					  sizeof(struct renesas_irqc_config))

static const struct resource thermal_resources[] __initconst = {
	DEFINE_RES_MEM(0xe61f0000, 0x14),
	DEFINE_RES_MEM(0xe61f0100, 0x38),
	DEFINE_RES_IRQ(gic_spi(69)),
};

#define r8a7791_register_thermal()					\
	platform_device_register_simple("rcar_thermal", -1,		\
					thermal_resources,		\
					ARRAY_SIZE(thermal_resources))

void __init r8a7791_add_dt_devices(void)
{
	r8a7791_register_cmt(0);
}

void __init r8a7791_add_standard_devices(void)
{
	r8a7791_register_scif(0);
	r8a7791_register_scif(1);
	r8a7791_register_scif(2);
	r8a7791_register_scif(3);
	r8a7791_register_scif(4);
	r8a7791_register_scif(5);
	r8a7791_register_scif(6);
	r8a7791_register_scif(7);
	r8a7791_register_scif(8);
	r8a7791_register_scif(9);
	r8a7791_register_scif(10);
	r8a7791_register_scif(11);
	r8a7791_register_scif(12);
	r8a7791_register_scif(13);
	r8a7791_register_scif(14);
	r8a7791_add_dt_devices();
	r8a7791_register_irqc(0);
	r8a7791_register_thermal();
}

#ifdef CONFIG_USE_OF
static const char *r8a7791_boards_compat_dt[] __initdata = {
	"renesas,r8a7791",
	NULL,
};

DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
	.smp		= smp_ops(r8a7791_smp_ops),
	.init_early	= shmobile_init_delay,
	.init_time	= rcar_gen2_timer_init,
	.init_late	= shmobile_init_late,
	.reserve	= rcar_gen2_reserve,
	.dt_compat	= r8a7791_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
Commit	Line	Data
0d0771ab HN	1	/*
	2	* r8a7791 processor support
	3	*
	4	* Copyright (C) 2013 Renesas Electronics Corporation
	5	* Copyright (C) 2013 Renesas Solutions Corp.
	6	* Copyright (C) 2013 Magnus Damm
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	*/
	21
	22	#include <linux/irq.h>
	23	#include <linux/kernel.h>
	24	#include <linux/of_platform.h>
93ff9163	25	#include <linux/platform_data/gpio-rcar.h>
454d320c	26	#include <linux/platform_data/irq-renesas-irqc.h>
e6491d08	27	#include <linux/serial_sci.h>
1bebd72a	28	#include <linux/sh_timer.h>
5201b5a7	29
0d0771ab	30	#include <asm/mach/arch.h>
5201b5a7	31
fd44aa5e	32	#include "common.h"
b6bab126	33	#include "irqs.h"
5201b5a7	34	#include "r8a7791.h"
62872989	35	#include "rcar-gen2.h"
0d0771ab	36
35040127 MD	37	static const struct resource pfc_resources[] __initconst = {
	38	DEFINE_RES_MEM(0xe6060000, 0x250),
	39	};
	40
	41	#define r8a7791_register_pfc() \
	42	platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
	43	ARRAY_SIZE(pfc_resources))
	44
93ff9163 MD	45	#define R8A7791_GPIO(idx, base, nr) \
	46	static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
	47	DEFINE_RES_MEM((base), 0x50), \
	48	DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
	49	}; \
	50	\
	51	static const struct gpio_rcar_config \
	52	r8a7791_gpio##idx##_platform_data __initconst = { \
	53	.gpio_base = 32 * (idx), \
	54	.irq_base = 0, \
	55	.number_of_pins = (nr), \
	56	.pctl_name = "pfc-r8a7791", \
	57	.has_both_edge_trigger = 1, \
	58	}; \
	59
	60	R8A7791_GPIO(0, 0xe6050000, 32);
	61	R8A7791_GPIO(1, 0xe6051000, 32);
	62	R8A7791_GPIO(2, 0xe6052000, 32);
	63	R8A7791_GPIO(3, 0xe6053000, 32);
	64	R8A7791_GPIO(4, 0xe6054000, 32);
	65	R8A7791_GPIO(5, 0xe6055000, 32);
	66	R8A7791_GPIO(6, 0xe6055400, 32);
	67	R8A7791_GPIO(7, 0xe6055800, 26);
	68
	69	#define r8a7791_register_gpio(idx) \
	70	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
	71	r8a7791_gpio##idx##_resources, \
	72	ARRAY_SIZE(r8a7791_gpio##idx##_resources), \
	73	&r8a7791_gpio##idx##_platform_data, \
	74	sizeof(r8a7791_gpio##idx##_platform_data))
	75
35040127 MD	76	void __init r8a7791_pinmux_init(void)
	77	{
	78	r8a7791_register_pfc();
93ff9163 MD	79	r8a7791_register_gpio(0);
	80	r8a7791_register_gpio(1);
	81	r8a7791_register_gpio(2);
	82	r8a7791_register_gpio(3);
	83	r8a7791_register_gpio(4);
	84	r8a7791_register_gpio(5);
	85	r8a7791_register_gpio(6);
	86	r8a7791_register_gpio(7);
35040127 MD	87	}
35040127 MD	88
f72ed4be	89	#define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \
135d0e60 LP	90	static struct plat_sci_port scif##index##_platform_data = { \
135d0e60 LP	91	.type = scif_type, \
135d0e60	92	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP, \
135d0e60	93	.scscr = SCSCR_RE \| SCSCR_TE, \
d95a95a8 LP	94	}; \
	95	\
	96	static struct resource scif##index##_resources[] = { \
	97	DEFINE_RES_MEM(baseaddr, 0x100), \
	98	DEFINE_RES_IRQ(irq), \
e6491d08 YF	99	}
e6491d08 YF	100
135d0e60	101	#define R8A7791_SCIF(index, baseaddr, irq) \
f72ed4be	102	__R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
135d0e60 LP	103
135d0e60 LP	104	#define R8A7791_SCIFA(index, baseaddr, irq) \
f72ed4be	105	__R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
135d0e60 LP	106
135d0e60 LP	107	#define R8A7791_SCIFB(index, baseaddr, irq) \
f72ed4be	108	__R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
135d0e60 LP	109
	110	R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
	111	R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
	112	R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
	113	R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
	114	R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
	115	R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
	116	R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
	117	R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
	118	R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */
	119	R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */
	120	R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */
	121	R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */
	122	R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
	123	R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
	124	R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
	125
	126	#define r8a7791_register_scif(index) \
d95a95a8 LP	127	platform_device_register_resndata(&platform_bus, "sh-sci", index, \
	128	scif##index##_resources, \
	129	ARRAY_SIZE(scif##index##_resources), \
	130	&scif##index##_platform_data, \
	131	sizeof(scif##index##_platform_data))
e6491d08	132
356af68b LP	133	static struct sh_timer_config cmt0_platform_data = {
356af68b LP	134	.channels_mask = 0x60,
1bebd72a MD	135	};
1bebd72a MD	136
356af68b LP	137	static struct resource cmt0_resources[] = {
	138	DEFINE_RES_MEM(0xffca0000, 0x1004),
	139	DEFINE_RES_IRQ(gic_spi(142)),
1bebd72a MD	140	};
	141
	142	#define r8a7791_register_cmt(idx) \
356af68b	143	platform_device_register_resndata(&platform_bus, "sh-cmt-48-gen2", \
1bebd72a MD	144	idx, cmt##idx##_resources, \
	145	ARRAY_SIZE(cmt##idx##_resources), \
	146	&cmt##idx##_platform_data, \
	147	sizeof(struct sh_timer_config))
	148
454d320c MD	149	static struct renesas_irqc_config irqc0_data = {
	150	.irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
	151	};
	152
	153	static struct resource irqc0_resources[] = {
	154	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	155	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	156	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	157	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	158	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	159	DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
	160	DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
	161	DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
	162	DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
	163	DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
	164	DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
	165	};
	166
	167	#define r8a7791_register_irqc(idx) \
	168	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
	169	idx, irqc##idx##_resources, \
	170	ARRAY_SIZE(irqc##idx##_resources), \
	171	&irqc##idx##_data, \
	172	sizeof(struct renesas_irqc_config))
	173
887e8407 MD	174	static const struct resource thermal_resources[] __initconst = {
	175	DEFINE_RES_MEM(0xe61f0000, 0x14),
	176	DEFINE_RES_MEM(0xe61f0100, 0x38),
	177	DEFINE_RES_IRQ(gic_spi(69)),
	178	};
	179
	180	#define r8a7791_register_thermal() \
	181	platform_device_register_simple("rcar_thermal", -1, \
	182	thermal_resources, \
	183	ARRAY_SIZE(thermal_resources))
	184
e6491d08	185	void __init r8a7791_add_dt_devices(void)
5ba55fa8 LP	186	{
	187	r8a7791_register_cmt(0);
	188	}
	189
	190	void __init r8a7791_add_standard_devices(void)
e6491d08	191	{
135d0e60 LP	192	r8a7791_register_scif(0);
	193	r8a7791_register_scif(1);
	194	r8a7791_register_scif(2);
	195	r8a7791_register_scif(3);
	196	r8a7791_register_scif(4);
	197	r8a7791_register_scif(5);
	198	r8a7791_register_scif(6);
	199	r8a7791_register_scif(7);
	200	r8a7791_register_scif(8);
	201	r8a7791_register_scif(9);
	202	r8a7791_register_scif(10);
	203	r8a7791_register_scif(11);
	204	r8a7791_register_scif(12);
	205	r8a7791_register_scif(13);
	206	r8a7791_register_scif(14);
4275881f	207	r8a7791_add_dt_devices();
454d320c	208	r8a7791_register_irqc(0);
887e8407	209	r8a7791_register_thermal();
4275881f MD	210	}
4275881f MD	211
0d0771ab HN	212	#ifdef CONFIG_USE_OF
	213	static const char *r8a7791_boards_compat_dt[] __initdata = {
	214	"renesas,r8a7791",
	215	NULL,
	216	};
	217
	218	DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
687c27b0	219	.smp = smp_ops(r8a7791_smp_ops),
648c687a	220	.init_early = shmobile_init_delay,
cd8344f4	221	.init_time = rcar_gen2_timer_init,
3d65226b	222	.init_late = shmobile_init_late,
f8e81935	223	.reserve = rcar_gen2_reserve,
0d0771ab HN	224	.dt_compat = r8a7791_boards_compat_dt,
	225	MACHINE_END
	226	#endif /* CONFIG_USE_OF */