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0d0771ab HN |
1 | /* |
2 | * r8a7791 processor support | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Electronics Corporation | |
5 | * Copyright (C) 2013 Renesas Solutions Corp. | |
6 | * Copyright (C) 2013 Magnus Damm | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | */ | |
21 | ||
22 | #include <linux/irq.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/of_platform.h> | |
93ff9163 | 25 | #include <linux/platform_data/gpio-rcar.h> |
454d320c | 26 | #include <linux/platform_data/irq-renesas-irqc.h> |
e6491d08 | 27 | #include <linux/serial_sci.h> |
1bebd72a | 28 | #include <linux/sh_timer.h> |
0d0771ab | 29 | #include <mach/common.h> |
e6491d08 | 30 | #include <mach/irqs.h> |
0d0771ab | 31 | #include <mach/r8a7791.h> |
cd8344f4 | 32 | #include <mach/rcar-gen2.h> |
0d0771ab HN |
33 | #include <asm/mach/arch.h> |
34 | ||
35040127 MD |
35 | static const struct resource pfc_resources[] __initconst = { |
36 | DEFINE_RES_MEM(0xe6060000, 0x250), | |
37 | }; | |
38 | ||
39 | #define r8a7791_register_pfc() \ | |
40 | platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \ | |
41 | ARRAY_SIZE(pfc_resources)) | |
42 | ||
93ff9163 MD |
43 | #define R8A7791_GPIO(idx, base, nr) \ |
44 | static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \ | |
45 | DEFINE_RES_MEM((base), 0x50), \ | |
46 | DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ | |
47 | }; \ | |
48 | \ | |
49 | static const struct gpio_rcar_config \ | |
50 | r8a7791_gpio##idx##_platform_data __initconst = { \ | |
51 | .gpio_base = 32 * (idx), \ | |
52 | .irq_base = 0, \ | |
53 | .number_of_pins = (nr), \ | |
54 | .pctl_name = "pfc-r8a7791", \ | |
55 | .has_both_edge_trigger = 1, \ | |
56 | }; \ | |
57 | ||
58 | R8A7791_GPIO(0, 0xe6050000, 32); | |
59 | R8A7791_GPIO(1, 0xe6051000, 32); | |
60 | R8A7791_GPIO(2, 0xe6052000, 32); | |
61 | R8A7791_GPIO(3, 0xe6053000, 32); | |
62 | R8A7791_GPIO(4, 0xe6054000, 32); | |
63 | R8A7791_GPIO(5, 0xe6055000, 32); | |
64 | R8A7791_GPIO(6, 0xe6055400, 32); | |
65 | R8A7791_GPIO(7, 0xe6055800, 26); | |
66 | ||
67 | #define r8a7791_register_gpio(idx) \ | |
68 | platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \ | |
69 | r8a7791_gpio##idx##_resources, \ | |
70 | ARRAY_SIZE(r8a7791_gpio##idx##_resources), \ | |
71 | &r8a7791_gpio##idx##_platform_data, \ | |
72 | sizeof(r8a7791_gpio##idx##_platform_data)) | |
73 | ||
35040127 MD |
74 | void __init r8a7791_pinmux_init(void) |
75 | { | |
76 | r8a7791_register_pfc(); | |
93ff9163 MD |
77 | r8a7791_register_gpio(0); |
78 | r8a7791_register_gpio(1); | |
79 | r8a7791_register_gpio(2); | |
80 | r8a7791_register_gpio(3); | |
81 | r8a7791_register_gpio(4); | |
82 | r8a7791_register_gpio(5); | |
83 | r8a7791_register_gpio(6); | |
84 | r8a7791_register_gpio(7); | |
35040127 MD |
85 | } |
86 | ||
f72ed4be | 87 | #define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \ |
135d0e60 LP |
88 | static struct plat_sci_port scif##index##_platform_data = { \ |
89 | .type = scif_type, \ | |
135d0e60 | 90 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
135d0e60 | 91 | .scscr = SCSCR_RE | SCSCR_TE, \ |
d95a95a8 LP |
92 | }; \ |
93 | \ | |
94 | static struct resource scif##index##_resources[] = { \ | |
95 | DEFINE_RES_MEM(baseaddr, 0x100), \ | |
96 | DEFINE_RES_IRQ(irq), \ | |
e6491d08 YF |
97 | } |
98 | ||
135d0e60 | 99 | #define R8A7791_SCIF(index, baseaddr, irq) \ |
f72ed4be | 100 | __R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq) |
135d0e60 LP |
101 | |
102 | #define R8A7791_SCIFA(index, baseaddr, irq) \ | |
f72ed4be | 103 | __R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq) |
135d0e60 LP |
104 | |
105 | #define R8A7791_SCIFB(index, baseaddr, irq) \ | |
f72ed4be | 106 | __R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq) |
135d0e60 LP |
107 | |
108 | R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ | |
109 | R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ | |
110 | R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ | |
111 | R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ | |
112 | R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ | |
113 | R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */ | |
114 | R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */ | |
115 | R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */ | |
116 | R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */ | |
117 | R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */ | |
118 | R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */ | |
119 | R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */ | |
120 | R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */ | |
121 | R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */ | |
122 | R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */ | |
123 | ||
124 | #define r8a7791_register_scif(index) \ | |
d95a95a8 LP |
125 | platform_device_register_resndata(&platform_bus, "sh-sci", index, \ |
126 | scif##index##_resources, \ | |
127 | ARRAY_SIZE(scif##index##_resources), \ | |
128 | &scif##index##_platform_data, \ | |
129 | sizeof(scif##index##_platform_data)) | |
e6491d08 | 130 | |
356af68b LP |
131 | static struct sh_timer_config cmt0_platform_data = { |
132 | .channels_mask = 0x60, | |
1bebd72a MD |
133 | }; |
134 | ||
356af68b LP |
135 | static struct resource cmt0_resources[] = { |
136 | DEFINE_RES_MEM(0xffca0000, 0x1004), | |
137 | DEFINE_RES_IRQ(gic_spi(142)), | |
1bebd72a MD |
138 | }; |
139 | ||
140 | #define r8a7791_register_cmt(idx) \ | |
356af68b | 141 | platform_device_register_resndata(&platform_bus, "sh-cmt-48-gen2", \ |
1bebd72a MD |
142 | idx, cmt##idx##_resources, \ |
143 | ARRAY_SIZE(cmt##idx##_resources), \ | |
144 | &cmt##idx##_platform_data, \ | |
145 | sizeof(struct sh_timer_config)) | |
146 | ||
454d320c MD |
147 | static struct renesas_irqc_config irqc0_data = { |
148 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */ | |
149 | }; | |
150 | ||
151 | static struct resource irqc0_resources[] = { | |
152 | DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ | |
153 | DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ | |
154 | DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ | |
155 | DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ | |
156 | DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ | |
157 | DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */ | |
158 | DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */ | |
159 | DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */ | |
160 | DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */ | |
161 | DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */ | |
162 | DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */ | |
163 | }; | |
164 | ||
165 | #define r8a7791_register_irqc(idx) \ | |
166 | platform_device_register_resndata(&platform_bus, "renesas_irqc", \ | |
167 | idx, irqc##idx##_resources, \ | |
168 | ARRAY_SIZE(irqc##idx##_resources), \ | |
169 | &irqc##idx##_data, \ | |
170 | sizeof(struct renesas_irqc_config)) | |
171 | ||
887e8407 MD |
172 | static const struct resource thermal_resources[] __initconst = { |
173 | DEFINE_RES_MEM(0xe61f0000, 0x14), | |
174 | DEFINE_RES_MEM(0xe61f0100, 0x38), | |
175 | DEFINE_RES_IRQ(gic_spi(69)), | |
176 | }; | |
177 | ||
178 | #define r8a7791_register_thermal() \ | |
179 | platform_device_register_simple("rcar_thermal", -1, \ | |
180 | thermal_resources, \ | |
181 | ARRAY_SIZE(thermal_resources)) | |
182 | ||
e6491d08 | 183 | void __init r8a7791_add_dt_devices(void) |
5ba55fa8 LP |
184 | { |
185 | r8a7791_register_cmt(0); | |
186 | } | |
187 | ||
188 | void __init r8a7791_add_standard_devices(void) | |
e6491d08 | 189 | { |
135d0e60 LP |
190 | r8a7791_register_scif(0); |
191 | r8a7791_register_scif(1); | |
192 | r8a7791_register_scif(2); | |
193 | r8a7791_register_scif(3); | |
194 | r8a7791_register_scif(4); | |
195 | r8a7791_register_scif(5); | |
196 | r8a7791_register_scif(6); | |
197 | r8a7791_register_scif(7); | |
198 | r8a7791_register_scif(8); | |
199 | r8a7791_register_scif(9); | |
200 | r8a7791_register_scif(10); | |
201 | r8a7791_register_scif(11); | |
202 | r8a7791_register_scif(12); | |
203 | r8a7791_register_scif(13); | |
204 | r8a7791_register_scif(14); | |
4275881f | 205 | r8a7791_add_dt_devices(); |
454d320c | 206 | r8a7791_register_irqc(0); |
887e8407 | 207 | r8a7791_register_thermal(); |
4275881f MD |
208 | } |
209 | ||
0d0771ab HN |
210 | #ifdef CONFIG_USE_OF |
211 | static const char *r8a7791_boards_compat_dt[] __initdata = { | |
212 | "renesas,r8a7791", | |
213 | NULL, | |
214 | }; | |
215 | ||
216 | DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)") | |
687c27b0 | 217 | .smp = smp_ops(r8a7791_smp_ops), |
648c687a | 218 | .init_early = shmobile_init_delay, |
cd8344f4 | 219 | .init_time = rcar_gen2_timer_init, |
0d0771ab HN |
220 | .dt_compat = r8a7791_boards_compat_dt, |
221 | MACHINE_END | |
222 | #endif /* CONFIG_USE_OF */ |