[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7791.c

/*
 * r8a7791 processor support
 *
 * Copyright (C) 2013  Renesas Electronics Corporation
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r8a7791.h>
#include <mach/rcar-gen2.h>
#include <asm/mach/arch.h>

static const struct resource pfc_resources[] __initconst = {
	DEFINE_RES_MEM(0xe6060000, 0x250),
};

#define r8a7791_register_pfc()						\
	platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
					ARRAY_SIZE(pfc_resources))

#define R8A7791_GPIO(idx, base, nr)					\
static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
	DEFINE_RES_MEM((base), 0x50),					\
	DEFINE_RES_IRQ(gic_spi(4 + (idx))),				\
};									\
									\
static const struct gpio_rcar_config					\
r8a7791_gpio##idx##_platform_data __initconst = {			\
	.gpio_base	= 32 * (idx),					\
	.irq_base	= 0,						\
	.number_of_pins	= (nr),						\
	.pctl_name	= "pfc-r8a7791",				\
	.has_both_edge_trigger = 1,					\
};									\

R8A7791_GPIO(0, 0xe6050000, 32);
R8A7791_GPIO(1, 0xe6051000, 32);
R8A7791_GPIO(2, 0xe6052000, 32);
R8A7791_GPIO(3, 0xe6053000, 32);
R8A7791_GPIO(4, 0xe6054000, 32);
R8A7791_GPIO(5, 0xe6055000, 32);
R8A7791_GPIO(6, 0xe6055400, 32);
R8A7791_GPIO(7, 0xe6055800, 26);

#define r8a7791_register_gpio(idx)					\
	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
		r8a7791_gpio##idx##_resources,				\
		ARRAY_SIZE(r8a7791_gpio##idx##_resources),		\
		&r8a7791_gpio##idx##_platform_data,			\
		sizeof(r8a7791_gpio##idx##_platform_data))

void __init r8a7791_pinmux_init(void)
{
	r8a7791_register_pfc();
	r8a7791_register_gpio(0);
	r8a7791_register_gpio(1);
	r8a7791_register_gpio(2);
	r8a7791_register_gpio(3);
	r8a7791_register_gpio(4);
	r8a7791_register_gpio(5);
	r8a7791_register_gpio(6);
	r8a7791_register_gpio(7);
}

#define __R8A7791_SCIF(scif_type, index, baseaddr, irq)			\
static struct plat_sci_port scif##index##_platform_data = {		\
	.type		= scif_type,					\
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,		\
	.scscr		= SCSCR_RE | SCSCR_TE,				\
};									\
									\
static struct resource scif##index##_resources[] = {			\
	DEFINE_RES_MEM(baseaddr, 0x100),				\
	DEFINE_RES_IRQ(irq),						\
}

#define R8A7791_SCIF(index, baseaddr, irq)				\
	__R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)

#define R8A7791_SCIFA(index, baseaddr, irq)				\
	__R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)

#define R8A7791_SCIFB(index, baseaddr, irq)				\
	__R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)

R8A7791_SCIFA(0,  0xe6c40000, gic_spi(144)); /* SCIFA0 */
R8A7791_SCIFA(1,  0xe6c50000, gic_spi(145)); /* SCIFA1 */
R8A7791_SCIFB(2,  0xe6c20000, gic_spi(148)); /* SCIFB0 */
R8A7791_SCIFB(3,  0xe6c30000, gic_spi(149)); /* SCIFB1 */
R8A7791_SCIFB(4,  0xe6ce0000, gic_spi(150)); /* SCIFB2 */
R8A7791_SCIFA(5,  0xe6c60000, gic_spi(151)); /* SCIFA2 */
R8A7791_SCIF(6,   0xe6e60000, gic_spi(152)); /* SCIF0 */
R8A7791_SCIF(7,   0xe6e68000, gic_spi(153)); /* SCIF1 */
R8A7791_SCIF(8,   0xe6e58000, gic_spi(22)); /* SCIF2 */
R8A7791_SCIF(9,   0xe6ea8000, gic_spi(23)); /* SCIF3 */
R8A7791_SCIF(10,  0xe6ee0000, gic_spi(24)); /* SCIF4 */
R8A7791_SCIF(11,  0xe6ee8000, gic_spi(25)); /* SCIF5 */
R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */

#define r8a7791_register_scif(index)					       \
	platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
					  scif##index##_resources,	       \
					  ARRAY_SIZE(scif##index##_resources), \
					  &scif##index##_platform_data,	       \
					  sizeof(scif##index##_platform_data))

static const struct sh_timer_config cmt00_platform_data __initconst = {
	.name = "CMT00",
	.timer_bit = 0,
	.clockevent_rating = 80,
};

static const struct resource cmt00_resources[] __initconst = {
	DEFINE_RES_MEM(0xffca0510, 0x0c),
	DEFINE_RES_MEM(0xffca0500, 0x04),
	DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
};

#define r8a7791_register_cmt(idx)					\
	platform_device_register_resndata(&platform_bus, "sh_cmt",	\
					  idx, cmt##idx##_resources,	\
					  ARRAY_SIZE(cmt##idx##_resources), \
					  &cmt##idx##_platform_data,	\
					  sizeof(struct sh_timer_config))

static struct renesas_irqc_config irqc0_data = {
	.irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
};

static struct resource irqc0_resources[] = {
	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
	DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
	DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
	DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
	DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
	DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
};

#define r8a7791_register_irqc(idx)					\
	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
					  idx, irqc##idx##_resources,	\
					  ARRAY_SIZE(irqc##idx##_resources), \
					  &irqc##idx##_data,		\
					  sizeof(struct renesas_irqc_config))

static const struct resource thermal_resources[] __initconst = {
	DEFINE_RES_MEM(0xe61f0000, 0x14),
	DEFINE_RES_MEM(0xe61f0100, 0x38),
	DEFINE_RES_IRQ(gic_spi(69)),
};

#define r8a7791_register_thermal()					\
	platform_device_register_simple("rcar_thermal", -1,		\
					thermal_resources,		\
					ARRAY_SIZE(thermal_resources))

void __init r8a7791_add_dt_devices(void)
{
	r8a7791_register_scif(0);
	r8a7791_register_scif(1);
	r8a7791_register_scif(2);
	r8a7791_register_scif(3);
	r8a7791_register_scif(4);
	r8a7791_register_scif(5);
	r8a7791_register_scif(6);
	r8a7791_register_scif(7);
	r8a7791_register_scif(8);
	r8a7791_register_scif(9);
	r8a7791_register_scif(10);
	r8a7791_register_scif(11);
	r8a7791_register_scif(12);
	r8a7791_register_scif(13);
	r8a7791_register_scif(14);
	r8a7791_register_cmt(00);
}

void __init r8a7791_add_standard_devices(void)
{
	r8a7791_add_dt_devices();
	r8a7791_register_irqc(0);
	r8a7791_register_thermal();
}

void __init r8a7791_init_early(void)
{
#ifndef CONFIG_ARM_ARCH_TIMER
	shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
#endif
}

#ifdef CONFIG_USE_OF
static const char *r8a7791_boards_compat_dt[] __initdata = {
	"renesas,r8a7791",
	NULL,
};

DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
	.smp		= smp_ops(r8a7791_smp_ops),
	.init_early	= r8a7791_init_early,
	.init_time	= rcar_gen2_timer_init,
	.dt_compat	= r8a7791_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
Commit	Line	Data
0d0771ab HN	1	/*
	2	* r8a7791 processor support
	3	*
	4	* Copyright (C) 2013 Renesas Electronics Corporation
	5	* Copyright (C) 2013 Renesas Solutions Corp.
	6	* Copyright (C) 2013 Magnus Damm
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	*/
	21
	22	#include <linux/irq.h>
	23	#include <linux/kernel.h>
	24	#include <linux/of_platform.h>
93ff9163	25	#include <linux/platform_data/gpio-rcar.h>
454d320c	26	#include <linux/platform_data/irq-renesas-irqc.h>
e6491d08	27	#include <linux/serial_sci.h>
1bebd72a	28	#include <linux/sh_timer.h>
0d0771ab	29	#include <mach/common.h>
e6491d08	30	#include <mach/irqs.h>
0d0771ab	31	#include <mach/r8a7791.h>
cd8344f4	32	#include <mach/rcar-gen2.h>
0d0771ab HN	33	#include <asm/mach/arch.h>
0d0771ab HN	34
35040127 MD	35	static const struct resource pfc_resources[] __initconst = {
	36	DEFINE_RES_MEM(0xe6060000, 0x250),
	37	};
	38
	39	#define r8a7791_register_pfc() \
	40	platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
	41	ARRAY_SIZE(pfc_resources))
	42
93ff9163 MD	43	#define R8A7791_GPIO(idx, base, nr) \
	44	static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
	45	DEFINE_RES_MEM((base), 0x50), \
	46	DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
	47	}; \
	48	\
	49	static const struct gpio_rcar_config \
	50	r8a7791_gpio##idx##_platform_data __initconst = { \
	51	.gpio_base = 32 * (idx), \
	52	.irq_base = 0, \
	53	.number_of_pins = (nr), \
	54	.pctl_name = "pfc-r8a7791", \
	55	.has_both_edge_trigger = 1, \
	56	}; \
	57
	58	R8A7791_GPIO(0, 0xe6050000, 32);
	59	R8A7791_GPIO(1, 0xe6051000, 32);
	60	R8A7791_GPIO(2, 0xe6052000, 32);
	61	R8A7791_GPIO(3, 0xe6053000, 32);
	62	R8A7791_GPIO(4, 0xe6054000, 32);
	63	R8A7791_GPIO(5, 0xe6055000, 32);
	64	R8A7791_GPIO(6, 0xe6055400, 32);
	65	R8A7791_GPIO(7, 0xe6055800, 26);
	66
	67	#define r8a7791_register_gpio(idx) \
	68	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
	69	r8a7791_gpio##idx##_resources, \
	70	ARRAY_SIZE(r8a7791_gpio##idx##_resources), \
	71	&r8a7791_gpio##idx##_platform_data, \
	72	sizeof(r8a7791_gpio##idx##_platform_data))
	73
35040127 MD	74	void __init r8a7791_pinmux_init(void)
	75	{
	76	r8a7791_register_pfc();
93ff9163 MD	77	r8a7791_register_gpio(0);
	78	r8a7791_register_gpio(1);
	79	r8a7791_register_gpio(2);
	80	r8a7791_register_gpio(3);
	81	r8a7791_register_gpio(4);
	82	r8a7791_register_gpio(5);
	83	r8a7791_register_gpio(6);
	84	r8a7791_register_gpio(7);
35040127 MD	85	}
35040127 MD	86
f72ed4be	87	#define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \
135d0e60 LP	88	static struct plat_sci_port scif##index##_platform_data = { \
135d0e60 LP	89	.type = scif_type, \
135d0e60	90	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP, \
135d0e60	91	.scscr = SCSCR_RE \| SCSCR_TE, \
d95a95a8 LP	92	}; \
	93	\
	94	static struct resource scif##index##_resources[] = { \
	95	DEFINE_RES_MEM(baseaddr, 0x100), \
	96	DEFINE_RES_IRQ(irq), \
e6491d08 YF	97	}
e6491d08 YF	98
135d0e60	99	#define R8A7791_SCIF(index, baseaddr, irq) \
f72ed4be	100	__R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
135d0e60 LP	101
135d0e60 LP	102	#define R8A7791_SCIFA(index, baseaddr, irq) \
f72ed4be	103	__R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
135d0e60 LP	104
135d0e60 LP	105	#define R8A7791_SCIFB(index, baseaddr, irq) \
f72ed4be	106	__R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
135d0e60 LP	107
	108	R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
	109	R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
	110	R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
	111	R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
	112	R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
	113	R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
	114	R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
	115	R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
	116	R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */
	117	R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */
	118	R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */
	119	R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */
	120	R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
	121	R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
	122	R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
	123
	124	#define r8a7791_register_scif(index) \
d95a95a8 LP	125	platform_device_register_resndata(&platform_bus, "sh-sci", index, \
	126	scif##index##_resources, \
	127	ARRAY_SIZE(scif##index##_resources), \
	128	&scif##index##_platform_data, \
	129	sizeof(scif##index##_platform_data))
e6491d08	130
1bebd72a MD	131	static const struct sh_timer_config cmt00_platform_data __initconst = {
	132	.name = "CMT00",
	133	.timer_bit = 0,
	134	.clockevent_rating = 80,
	135	};
	136
	137	static const struct resource cmt00_resources[] __initconst = {
	138	DEFINE_RES_MEM(0xffca0510, 0x0c),
	139	DEFINE_RES_MEM(0xffca0500, 0x04),
	140	DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
	141	};
	142
	143	#define r8a7791_register_cmt(idx) \
	144	platform_device_register_resndata(&platform_bus, "sh_cmt", \
	145	idx, cmt##idx##_resources, \
	146	ARRAY_SIZE(cmt##idx##_resources), \
	147	&cmt##idx##_platform_data, \
	148	sizeof(struct sh_timer_config))
	149
454d320c MD	150	static struct renesas_irqc_config irqc0_data = {
	151	.irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
	152	};
	153
	154	static struct resource irqc0_resources[] = {
	155	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	156	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	157	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	158	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	159	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	160	DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
	161	DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
	162	DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
	163	DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
	164	DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
	165	DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
	166	};
	167
	168	#define r8a7791_register_irqc(idx) \
	169	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
	170	idx, irqc##idx##_resources, \
	171	ARRAY_SIZE(irqc##idx##_resources), \
	172	&irqc##idx##_data, \
	173	sizeof(struct renesas_irqc_config))
	174
887e8407 MD	175	static const struct resource thermal_resources[] __initconst = {
	176	DEFINE_RES_MEM(0xe61f0000, 0x14),
	177	DEFINE_RES_MEM(0xe61f0100, 0x38),
	178	DEFINE_RES_IRQ(gic_spi(69)),
	179	};
	180
	181	#define r8a7791_register_thermal() \
	182	platform_device_register_simple("rcar_thermal", -1, \
	183	thermal_resources, \
	184	ARRAY_SIZE(thermal_resources))
	185
e6491d08 YF	186	void __init r8a7791_add_dt_devices(void)
e6491d08 YF	187	{
135d0e60 LP	188	r8a7791_register_scif(0);
	189	r8a7791_register_scif(1);
	190	r8a7791_register_scif(2);
	191	r8a7791_register_scif(3);
	192	r8a7791_register_scif(4);
	193	r8a7791_register_scif(5);
	194	r8a7791_register_scif(6);
	195	r8a7791_register_scif(7);
	196	r8a7791_register_scif(8);
	197	r8a7791_register_scif(9);
	198	r8a7791_register_scif(10);
	199	r8a7791_register_scif(11);
	200	r8a7791_register_scif(12);
	201	r8a7791_register_scif(13);
	202	r8a7791_register_scif(14);
1bebd72a MD	203	r8a7791_register_cmt(00);
	204	}
	205
4275881f MD	206	void __init r8a7791_add_standard_devices(void)
	207	{
	208	r8a7791_add_dt_devices();
454d320c	209	r8a7791_register_irqc(0);
887e8407	210	r8a7791_register_thermal();
4275881f MD	211	}
4275881f MD	212
1bebd72a MD	213	void __init r8a7791_init_early(void)
	214	{
	215	#ifndef CONFIG_ARM_ARCH_TIMER
ce4b6a04	216	shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
1bebd72a	217	#endif
e6491d08 YF	218	}
e6491d08 YF	219
0d0771ab HN	220	#ifdef CONFIG_USE_OF
	221	static const char *r8a7791_boards_compat_dt[] __initdata = {
	222	"renesas,r8a7791",
	223	NULL,
	224	};
	225
	226	DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
687c27b0	227	.smp = smp_ops(r8a7791_smp_ops),
1bebd72a	228	.init_early = r8a7791_init_early,
cd8344f4	229	.init_time = rcar_gen2_timer_init,
0d0771ab HN	230	.dt_compat = r8a7791_boards_compat_dt,
	231	MACHINE_END
	232	#endif /* CONFIG_USE_OF */